JPH05175222A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device of high speed and high performance, by forming a recess on the side surface of a first conductor film turning to a base electrode. CONSTITUTION:An SiGe layer 12 composed of SiGe of about 100nm in thickness to which high concentration (about 5X10<18>cm<-3>) of boron is added is selectively formed by epitaxial growth, only on a poly silicon film 6 exposed on the side surface of an aperture 9 and on an epitaxial layer 11 exposed on the bottom surface of the aperture 9. Since the average distance between the poly silicon layer 6 and the silicon epitaxial layer 11 is long as compared with that of the conventional bipolar transistor, an outer base diffusion layer becomes hard to be formed. Thereby the collector base junction capacitance is remarkably reduced, so that the cutoff frequency of a transistor can be very much improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed and high performance bipolar transistor using a heteroepitaxial technique for a base region and a method for manufacturing the same.

[0002]

2. Description of the Prior Art High performance bipolar transistor devices are
It is used in various fields such as electronic computers, optical communications, and various analog circuits. Recently, several bipolar transistors incorporating heteroepitaxial technology have been proposed, and the cutoff frequency of the prototype bipolar transistor is 80G.
Hz is about to be reached (eg IEEE transon El
ectron Device, vol. ED-38, Feb. 1991, p378, Japanese Patent Laid-Open No. 2-40923, IEDM '90, p13).

A conventional method for manufacturing a bipolar transistor will be described with reference to FIG. First, the P-type silicon substrate 10
Then, the N-type epitaxial layer 103 is formed on the substrate 1 via the N ⁺ impurity layer 102 (see FIG. 5A). After that, the oxide film 4 for element isolation is formed by using the trench technique and the oxide film selective filling technique (see FIG. 5A). Next, after a layer 105 made of, for example, SiGe containing boron is epitaxially grown on the surface of the element region, the oxide film 1 is formed on the entire surface.
06 and a nitride film (Si ₃ N ₄ film) serving as an oxidation resistant mask 1
07 is deposited, and a nitride film 107 and an oxide film 106 are formed on a region where an emitter base is to be formed by using a photoetching technique.
Are left (see FIG. 5 (a)). After that, a polysilicon film 108 is deposited, boron ions are implanted into this polysilicon film 108, and then an oxide film 109 is deposited on the entire surface by a CVD method. Then, the SiGe layer 105 on the emitter base formation planned region is exposed. Until the CVD oxide film 109 and the polysilicon film 10 are formed by using the photo etching technique.
8, the nitride film 107 and the oxide film 106 are opened to provide openings (see FIG. 5A).

After that, an oxide film 110 is formed on the entire surface and is etched back by using anisotropic etching.
The oxide film 110 is left only on the sides of the opening (see FIG. 5B). Then, a high concentration arsenic-added polysilicon film 111 is deposited to fill the opening (see FIG. 5C). Thereafter, heat treatment is performed so that arsenic is diffused into the SiGe layer 105 to form an N-type emitter layer in the SiGe layer 105, and the polysilicon film 10 is also formed.
The boron injected into the N-type epitaxial layer 103 is diffused into the N-type epitaxial layer 103 through the SiGe layer 105 to form the external base region 1.
13 is formed on the N-type epitaxial layer 103 (FIG. 5).
(See (c)). The polysilicon films 108 and 111 are used as a base electrode and an emitter electrode, respectively.

[0005]

In such a conventional manufacturing method, the base layer is formed by the heteroepitaxial technique, and the diffusion layer having a width of 50 nm or less can be formed by the polysilicon emitter technique. Thus, a bipolar transistor that can operate at high speed can be obtained. However, in the conventional method, it is difficult to control the shape of the external base diffusion layer 113, and the collector base capacitance due to the external base diffusion layer becomes large, which hinders the speedup of the bipolar transistor. there were.

The present invention has been made in consideration of the above problems, and an object of the present invention is to provide a high-speed and high-performance semiconductor device and a manufacturing method thereof.

[0007]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a first insulating film and a second conductivity type on a semiconductor substrate having a first conductivity type collector layer and an element isolation region formed therein. First step of sequentially stacking the first conductive film and the second insulating film, and the first insulating film, the first conductive film, and the second insulating film in the emitter base formation region. The second step of forming the opening by removing the film and the metal film until the semiconductor substrate is exposed, and the first conductor film exposed on the side surface of the opening is removed by etching by a predetermined amount. Forming a recess on the side surface of the opening, a fourth step of filling the recess formed on the side surface of the opening with a third insulating film, and a first conductivity type single crystal silicon on the bottom surface of the opening. The silicon film of is selectively formed until the height is almost the same as the upper surface of the first insulating film. 6 of removing the fifth step to length, the third insulating film buried in a recess of the side surface of the opening
And the seventh step of selectively forming a semiconductor layer of the second conductivity type on the silicon film on the bottom surface of the opening and on the exposed side surface of the first conductor film, and on the side surface of the opening. An eighth step of forming a side wall made of a fourth insulating film, a ninth step of forming a second conductive film of the first conductivity type on the entire surface of the semiconductor substrate, and a second step by performing heat treatment. And a tenth step of forming an emitter layer by diffusing first-conductivity-type impurity atoms in the conductor film into the semiconductor layer.

A semiconductor device according to a second aspect of the present invention includes a semiconductor substrate on which a collector layer of the first conductivity type and an element isolation region are formed, a first insulating film, and a second insulating film which are sequentially stacked on the semiconductor substrate. A laminated body composed of a conductive-type first conductive film and a second insulating film; and an opening provided in the laminated body to form an emitter region and connected to the collector layer, Of the first conductive film having an opening width larger than that of the first insulating film, and an upper surface formed at a bottom surface of the opening and having substantially the same height as an upper surface of the first insulating film.
A conductive type single crystal silicon film, a second conductive type semiconductor layer formed on the surface of the single crystal silicon film and the side surface of the first conductor film in the opening, and a second conductive type semiconductor layer formed on the side surface of the opening. Three
A side wall made of an insulating film and a first conductivity type emitter region formed in the semiconductor layer on the bottom surface of the opening.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a first insulating film is formed in a device isolation formation-scheduled region and an inter-electrode separation formation-scheduled region on a semiconductor substrate on which a collector layer of the first conductivity type is formed. A first step of forming an element isolation region, an electrode isolation region, and an intrinsic element region by burying; a second step of forming a base layer made of a second conductivity type semiconductor layer on the entire surface of the substrate; A third step of forming a laminated body in which a second insulating film and an oxidation resistant insulating film are sequentially laminated so as to cover the intrinsic element region on the layer, and a second conductivity type first layer covering the base layer and the laminated body. And a fourth step of forming a conductor film on the intrinsic element region until a base layer is exposed to form an emitter region after forming a third insulating film on the first conductor film. Open the third insulating film, the first conductor film, and the laminated body A fifth step of providing openings Te,
A sixth step of forming a side wall made of a fourth insulating film on the side surface of the opening, and a second conductive film of the first conductivity type formed on the entire surface of the semiconductor substrate, and then the second conductive film being used as a base. First in layer
A seventh step of forming a first conductivity type emitter region in the base layer by diffusing a conductivity type impurity.

A semiconductor device according to a fourth invention comprises a semiconductor substrate having a first conductivity type intrinsic element region and an element isolation region, and a second conductivity type semiconductor layer formed on the semiconductor substrate. And a laminated body in which the first insulating film and the oxidation resistant insulating film are sequentially laminated on the base layer so as to cover the intrinsic element region, and the second laminated body formed so as to cover the laminated body and the base layer. A conductive type first conductor film, a second insulating film formed on the first conductor film, and an emitter region on the intrinsic element region until the base layer is exposed to form an emitter region; An opening provided by opening the second insulating film, the first conductor film, and the stacked body, and a side wall formed of a third insulating film on a side surface of the opening,
And a first conductivity type emitter region formed in the base layer on the bottom surface of the opening.

[0011]

According to the method of manufacturing a semiconductor device of the first aspect of the invention configured as described above, the opening width of the first conductor film serving as the base electrode is reduced by forming the recess on the side surface of the first conductor film. The insulating film is formed to have a width larger than that of the insulating film, the single crystal silicon film serving as the collector region is embedded in the opening of the first insulating film, and the semiconductor layer serving as the base layer is formed on the single crystal silicon film and on the first insulating film. 1 is formed on the side surface of the conductor film.
As a result, the average distance between the first conductor film and the single crystal silicon film can be made longer than in the conventional case, and the first conductor film and the single crystal silicon film are interposed via the semiconductor layer. It is possible to suppress the diffusion of the second conductivity type impurities into the film.

Therefore, the collector-base capacitance can be greatly reduced, the cutoff frequency can be greatly improved, and a high-speed and high-performance semiconductor device can be obtained.

According to the semiconductor device of the second aspect of the invention configured as described above, the opening width of the first conductor film serving as the base electrode is larger than the opening width of the first insulating film. A single crystal silicon film to be a collector region is buried in the opening of the first insulating film, and a semiconductor layer to be a base layer is formed on the single crystal silicon film and on the side surface of the first conductor film. There is. As a result, the average distance between the first conductor film and the single crystal silicon film can be made longer than in the conventional case, and the first conductor film and the single crystal silicon film are interposed via the semiconductor layer. It is possible to suppress the diffusion of the second conductivity type impurities into the film.

Therefore, the collector-base capacitance can be greatly reduced, the cutoff frequency can be greatly improved, and a high-speed and high-performance semiconductor device can be obtained.

According to the method of manufacturing a semiconductor device of the third invention having the above-mentioned structure, the laminated body is formed on the base layer so as to cover the intrinsic element region which becomes the collector region, and the laminated body is further formed. A first conductor film serving as a base electrode is formed so as to cover the body and the base layer. This makes the first
It is possible to suppress the diffusion of the second conductivity type impurity from the conductor film to the intrinsic element region through the base layer. Therefore, the collector-base capacitance can be greatly reduced, the cutoff frequency can be greatly improved, and a high-speed and high-performance semiconductor device can be obtained.

Further, according to the semiconductor device of the fourth aspect of the invention configured as described above, the laminated body is formed on the base layer so as to cover the intrinsic element region serving as the collector region,
Further, a first conductor film serving as a base electrode is formed so as to cover the laminated body and the base layer. This makes the first
It is possible to suppress the diffusion of the second conductivity type impurity from the conductor film to the intrinsic element region through the base layer. Therefore, the collector-base capacitance can be greatly reduced, the cutoff frequency can be greatly improved, and a high-speed and high-performance semiconductor device can be obtained.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a method of manufacturing a semiconductor device according to the first invention will be described with reference to FIGS. 1 and 2 are cross-sectional views showing a manufacturing process of a semiconductor device manufactured according to this embodiment.

First, a high-concentration impurity layer 2 containing N-type high-concentration impurities is formed on a P-type silicon substrate 1, and then an oxide film for element isolation is formed by using a trench technique and an oxide film selective burying technique. A trench region 4 is formed (see FIG. 1A). Next, using the CVD method, a thickness of 500
A CVD oxide film 5 having a thickness of about nm is formed on the entire surface of the substrate, and then a polysilicon film 6 is grown to have a thickness of about 400 nm on the entire surface of the substrate. Then, for example, boron is ion-implanted into the polycrystalline silicon film 6 under the conditions of a dose amount of 50 KeV and 1.0 × 10 ¹⁶ cm ^-2 , and then a CVD oxide film 7 is deposited by the CVD method (see FIG. )reference). After annealing at 900 ° C. for about 30 minutes, for example, a metal film 8 made of aluminum and having a thickness of about 100 nm is formed (FIG. 1).
(See (a)). Next, the metal film 8, the CVD oxide film 7, and the polysilicon film 6 are formed on the region that will later become the emitter base region.
Then, the CVD oxide film 5 is removed using an anisotropic etching technique until the high-concentration impurity layer 2 on the substrate 1 is exposed to form an opening 9 having an opening width of about 1 μm (see FIG. 1A). ).

Next, the polysilicon film 6 and the high-concentration impurity layer 2 exposed on the side surface and the bottom surface of the opening are removed by etching by about 150 nm by isotropic reactive plasma etching. Then, a recess (not shown) having a depth of about 150 nm is formed in the exposed portion of the side surface of the opening 9 of the polysilicon film 6 and the high-concentration impurity layer 2.
After that, the CVD oxide film 10 is deposited on the entire surface by using the CVD method, and then the other portion is formed by reactive ion etching so that the CVD oxide film 10 remains only in the recessed portion formed on the side surface of the opening 9. The CVD oxide film 10 is removed by etching (see FIG. 1B).

Next, only on the high-concentration impurity layer 2 exposed on the bottom surface of the opening 9, the single-crystal silicon epitaxial layer 11 doped with N-type at a low concentration (approximately 1.0 × 10 ¹⁶ cm ^-3 ) is formed. Is grown until its thickness is approximately equal to the thickness of the CVD oxide film 5 plus the depth of the depression (see FIG. 1 (c)). That is, the epitaxial layer 11
Has an almost same height as the upper surface of the CVD oxide film 5.
At this time, since the N-type high concentration impurity layer 2 is connected to the collector contact (not shown), the low concentration epitaxial layer 11 forms a part of the collector. After that, for example, by immersing in an NH ₄ F solution, the opening 9
The CVD oxide film 10 left in the depressions on the side surface of is removed (see FIG. 1C). At this time, a part of the CVD oxide film 7 exposed on the side surface of the opening 9 is also removed. Thereafter, the aluminum film 8 is removed by, for example, immersing in a mixed solution of sulfuric acid and hydrogen peroxide (see FIG. 1C).

Next, only the polysilicon film 6 exposed on the side surface of the opening 9 and the epitaxial layer 11 exposed on the bottom surface of the opening 9 are selectively epitaxially grown to a high concentration of about 100 nm ( 5 × 10 ¹⁸ cm ^-3 )
SiGe layer 12 made of SiGe to which boron is added
Are formed (see FIG. 2A).

Subsequently, a CVD oxide film 13 having a thickness of about 200 nm is deposited on the entire surface of the substrate by the CVD method and is etched by reactive ion etching to form the CVD oxide film 13 only on the side surface of the opening 9. Is left (see FIG. 2B). After that, a polysilicon film 14 having a thickness of about 200 nm
And a dose amount of arsenic of 5 is formed on the polysilicon film 14.
Ion implantation is performed under the conditions of 0 KeV and 1.0 × 10 ¹⁶ cm ^-2 , and a desired heat treatment is performed to obtain a polysilicon film 1.
The arsenic added to 4 is diffused into the epitaxial layer 12 to form the N-type emitter region 15 and the internal base region (see FIG. 2C). Subsequently, after depositing a metal film made of, for example, aluminum on the entire surface of the substrate, patterning is performed to form a wiring layer and form a bipolar transistor (not shown).

In the bipolar transistor thus formed, since the average distance between the polysilicon layer 6 and the silicon epitaxial layer 11 is longer than that of the conventional bipolar transistor, the epitaxial layer 11 has an external base diffusion layer. Is less likely to be formed, and thus the collector-base junction capacitance is greatly reduced, the cutoff frequency of the transistor is greatly improved, and a high-speed and high-performance bipolar transistor can be obtained.

The external base and the polysilicon film 6
And the internal base is linked by the SiGe layer 12 containing a high concentration of boron.

Although the epitaxial layer 12 is made of the material of SiGe in the above embodiment, a hetero material having a band gap smaller than that of silicon may be used.

Next, a sectional view of an embodiment of the semiconductor device according to the second invention is shown in FIG. In the semiconductor device of this embodiment, an N-type high-concentration impurity layer 2 and a trench region 4 for element isolation are formed on a P-type silicon substrate 1. Then, a CVD oxide film 5, a boron-doped polysilicon film 6, and a CVD oxide film 7 are sequentially stacked. In these laminated films, an opening is provided to connect to the high concentration impurity layer 2, and the opening width of the opening is larger in the polysilicon film 6 than in the CVD oxide film 5. Then, in the opening of the CVD oxide film 5, an epitaxial layer 11 of single crystal silicon doped with a low concentration N-type impurity is formed. Then, a semiconductor layer 12 made of SiGe highly doped with boron is formed on the epitaxial layer 11 and the side surface of the polysilicon film 6, and a side wall 13 made of a CVD oxide film is further formed on the side surface of the opening. ing. Then, the CVD oxide films 7 and 13
A high-concentration arsenic-doped polysilicon layer 14 is formed so as to cover the SiGe layer 12, and arsenic, which is an impurity, is diffused from the polysilicon film 14 into the SiGe layer 12 to form an emitter region.

The semiconductor device of this embodiment thus constituted has the same effect as the manufactured semiconductor device of the first invention.

Next, an embodiment of a method of manufacturing a semiconductor device according to the third invention will be described with reference to FIGS. Figure 3
4A and 4B are cross-sectional views showing the manufacturing process of the semiconductor device manufactured according to this embodiment.

First, a high-concentration impurity layer 22 containing N-type high-concentration impurities is formed on a P-type silicon substrate 21, and an N-type relatively low concentration (approximately 1.0 × 10 ¹⁶ cm 2) is further formed thereon. ^-3
After the epitaxial layer 23 is formed by vapor phase epitaxy, a trench region 24 as an element isolation and an oxide film 24a are formed by using a trench technique and an oxide film selective burying technique (FIG. )reference). The isolation oxide film 24a is formed in the inter-electrode isolation region that isolates the intrinsic element region 23a and the collector contact portion (not shown). Further, since the high-concentration impurity layer 22 is connected to the collector contact (not shown), the epitaxial layer 23 forms a part of the collector.

Next, a high concentration (approximately 5 ×) having a thickness of about 100 nm is epitaxially grown on the entire surface of the silicon substrate 21.
SiGe layer 25 with boron added to about 10 ¹⁸ cm ⁻³ )
And a CVD oxide film 26 having a thickness of about 50 nm as an insulating film and a silicon nitride film (Si ₃ having a thickness of about 100 nm) as an oxidation resistant insulating film are formed thereon.
N ₄ film) 9 is formed. Next, by using reactive plasma etching, the nitride film 27 in the region other than the intrinsic element region 23a is formed.
Is removed until the underlying CVD oxide film 26 is exposed. At this time, the remaining nitride film 27 covers the intrinsic element region 23a. Next, using the remaining nitride film 27 as a mask, the oxide film in the region other than the intrinsic element region 23a is removed by etching using, for example, an NH ₄ F solution until the underlying SiGe layer 25 is exposed. After that, a polysilicon film 28 having a thickness of about 400 nm is formed on the entire surface (see FIG. 3A). Then, the polysilicon film 28 is doped with boron at a dose amount of 50 KeV.
Ion implantation is performed under the condition of 1 × 10 ¹⁶ cm ^-2 (Fig. 3
(See (a)).

Next, a CVD oxide film 29 having a thickness of about 300 nm is formed on the polysilicon film 28 by the CVD method, and then CV on the region corresponding to the emitter diffusion region is formed.
The D oxide film 29, the polysilicon film 28, the nitride film 27, and the CVD oxide film 26 are removed by etching using anisotropic etching until the underlying SiGe layer 25 is exposed, and an opening 30 having an opening width of about 1 μm is formed. Are formed (see FIG. 3B).

Subsequently, after the CVD oxide film 31 is entirely deposited by the CVD method, another portion of the CVD oxide film 31 is formed by anisotropic etching so that the CVD oxide film 31 remains only on the side surface of the opening 30. It is removed by etching (see FIG. 4A). Next, a polysilicon film 32 having a thickness of about 200 nm is deposited on the entire surface, and arsenic is ion-implanted into the polysilicon film 32 under the conditions of a dose amount of 50 KeV and 1 × 10 ¹⁶ cm ^-2 , and then a desired heat treatment is performed. By applying the polysilicon film 32
The arsenic implanted in the substrate is diffused into the epitaxial layer 25 made of SiGe to form an N-type emitter region and an internal base region (see FIG. 4B). Then, a metal film made of, for example, aluminum is formed on the entire surface of the substrate. After deposition, the metal film is patterned to form a wiring layer to form a bipolar transistor (not shown).

In the bipolar transistor formed as described above, the nitride film 27 and the CVD oxide film 2 are formed.
Since 6 completely covers the intrinsic element region 23a, the diffusion of boron from the polysilicon film 28 to the intrinsic element region 23a due to the subsequent heat treatment is eliminated, and the external base diffusion layer is not formed. That is, the nitride film 27 as an etching stopper also plays a role of preventing diffusion of boron. As a result, the collector-base junction capacitance is greatly reduced, and the cutoff frequency of the bipolar transistor can be greatly improved, so that a high-speed bipolar transistor can be obtained.

The external base polysilicon film 28 and the internal base links are formed by the epitaxial layer 25 to which boron is added at a high concentration. In general, when the co-doped non-selective epitaxial technique is used, the concentration of impurities (boron in this embodiment) tends to be higher on the oxide film than on silicon. Therefore, the boron concentration in the epitaxial layer 25 is in the internal base region ( A link with the external base can be sufficiently secured by fitting it together just below the opening 30). In other words, in order to secure the link, it is not necessary to dope boron with such a high concentration that the transistor characteristics deteriorate.

In the above embodiment, the epitaxial layer 25 is made of a material made of SiGe to which boron is added at a high concentration, but a hetero material having a bandgap smaller than that of silicon may be used.

Next, FIG. 4B shows a sectional view of an embodiment of the semiconductor device according to the fourth invention. In the semiconductor device of this embodiment, an N-type high-concentration impurity layer 22 and an N-type relatively low-concentration epitaxial layer 23 are formed on a P-type silicon substrate 21, and an element isolation region 2 made of an oxide film is formed.
4 and the inter-electrode separation region 24a are formed. In addition,
The inter-electrode separation region 24a separates the intrinsic element region 23a from the collector contact portion (not shown).

Further, SiGe containing a high concentration of boron is added.
The layer 25 is formed so as to cover the intrinsic element region 23a, the element isolation region 24, and the inter-electrode isolation region 24a. Then, the SiGe layer 2 is formed so that the stacked body including the CVD oxide film 26 and the Si ₃ N ₄ film 27 covers the intrinsic element region 23a.
5, a polysilicon film 28 and a CVD oxide film 29 to which boron is added are stacked so as to cover the stacked body and the SiGe layer 25. And SiGe
CVD over intrinsic device region 23a until layer 25 is exposed
Oxide film 29, polysilicon film 28, Si ₃ N ₄ film 27,
An opening is provided in the CVD oxide film 26, and a side wall 31 made of a CVD oxide film is provided on the side surface of the opening. Further, an N-type emitter region 33 is formed in the SiGe layer 25 on the bottom surface of the opening, and an N-type polysilicon film 32 serving as an emitter electrode connected to the emitter region 33 is formed so as to fill the opening. Has been done.

It goes without saying that the semiconductor device of this embodiment has the same effects as the semiconductor device manufactured by the manufacturing method of the third invention.

Although the NPN type bipolar transistor has been described in the above-described embodiments, the PNP type bipolar transistor can be similarly made high speed and high performance.

[0040]

According to the present invention, a high speed and high performance semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1 is a process sectional view of a semiconductor device manufactured by a first invention.

FIG. 2 is a process cross-sectional view of a semiconductor device manufactured by the first invention.

FIG. 3 is a process sectional view of a semiconductor device manufactured by the third invention.

FIG. 4 is a process cross-sectional view of a semiconductor device manufactured by the third invention.

FIG. 5 is a process sectional view showing a conventional manufacturing method.

[Explanation of symbols]

 1 Silicon substrate (P type) 2 High concentration impurity layer (N type) 4 Element isolation region 5 CVD oxide film 6 Polysilicon film (P type) 7 CVD oxide film 9 Opening 11 Epitaxial layer (N type) 12 SiGe layer ( P type) 13 CVD oxide film 14 Polysilicon film (N type) 15 Emitter region

[Procedure amendment]

[Submission date] March 19, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

A conventional method for manufacturing a bipolar transistor will be described with reference to FIG. First, the P-type silicon substrate 10
Then, the N-type epitaxial layer 103 is formed on the substrate 1 via the N ⁺ impurity layer 102 (see FIG. 5A). After that, the oxide film 4 for element isolation is formed by using the trench technique and the oxide film selective filling technique (see FIG. 5A). Next, after a layer 105 made of, for example, SiGe containing boron is epitaxially grown on the surface of the element region, the oxide film 1 is formed on the entire surface.
06 and a nitride film (Si ₃ N ₄ film) 1 serving as an oxidation resistant mask
07 is deposited, and a nitride film 107 and an oxide film 106 are formed on a region where an emitter base is to be formed by using a photoetching technique.
Are left (see FIG. 5 (a)). After that, a polysilicon film 108 is deposited, boron ions are implanted into this polysilicon film 108, and then an oxide film 109 is deposited on the entire surface by a CVD method. Then, the SiGe layer 105 on the emitter base formation planned region is exposed. Until the CVD oxide film 109 and the polysilicon film 10 are formed by using the photo etching technique.
8, the nitride film 107 and the oxide film 106 are opened to provide openings (see FIG. 5A). As another method of providing this opening, first, the CVD oxide film 109 and the polysilicon film 108 are opened by using a photoetching technique until the nitride film 107 is exposed, and then the exposed nitride film 107 is heated with phosphorus. Solution etching is performed with an acid or the like to expose the oxide film 106.
Alternatively, the etching may be performed by solution etching with a ₄ F solution or the like until the SiGe layer 105 is exposed.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

Next, a CVD oxide film 29 having a thickness of about 300 nm is formed on the polysilicon film 28 by the CVD method, and then CV on the region corresponding to the emitter diffusion region is formed.
The D oxide film 29, the polysilicon film 28, the nitride film 27, and the CVD oxide film 26 are removed by etching using anisotropic etching until the underlying SiGe layer 25 is exposed, and an opening 30 having an opening width of about 1 μm is formed. Are formed (see FIG. 3B). As another method of forming the opening 30, first, the CVD oxide film 29 and the polysilicon film 28 are opened by using a photoetching technique until the nitride film 27 is exposed, and then the exposed nitride film 27 is heated. Solution etching with phosphoric acid or the like to expose the CVD oxide film 26,
This exposed CVD oxide film 26 may be etched by solution etching with an NH ₄ F solution or the like until the SiGe layer 25 is exposed.

Claims (4)

[Claims] 1. A first insulating film, a second conductive type first conductive film, and a second insulating film are formed on a semiconductor substrate on which a first conductive type collector layer and an element isolation region are formed. A first step of sequentially laminating, and an opening by removing the first insulating film, the first conductor film, and the second insulating film in the emitter base formation region until the semiconductor substrate is exposed. Second forming part
And a third step of removing a predetermined amount of the first conductor film exposed on the side surface of the opening to form a recess on the side surface of the opening, and forming on the side surface of the opening. A fourth step of filling the formed recess with a third insulating film, and a silicon film made of single-crystal silicon of the first conductivity type on the bottom surface of the opening to have a height substantially equal to that of the upper surface of the first insulating film. And a step of selectively growing the third insulating film buried in the recess on the side surface of the opening, and a step of exposing the bottom surface of the opening on the silicon film and exposing the silicon film. Doing 1st
A seventh step of selectively forming a second conductivity type semiconductor layer on the side surface of the conductor film, an eighth step of forming a side wall made of a fourth insulating film on the side surface of the opening, A ninth step of forming a second conductive film of the first conductivity type on the entire surface of the semiconductor substrate, and a first step in the second conductive film by performing heat treatment.
A tenth step of forming an emitter layer by diffusing conductivity type impurity atoms into the semiconductor layer, the method of manufacturing a semiconductor device. 2. A semiconductor substrate on which a collector layer of the first conductivity type and an element isolation region are formed, and a first insulating film and a first conductor of the second conductivity type, which are sequentially stacked on the semiconductor substrate. A laminate comprising a film and a second insulating film, and an opening provided in the laminate to form an emitter region and connected to the collector layer, A first conductivity type having an opening whose opening width is larger than the opening width of the first insulating film and an upper surface which is formed on the bottom surface of the opening and has substantially the same height as the upper surface of the first insulating film. A single crystal silicon film, a second conductivity type semiconductor layer formed on the surface of the single crystal silicon film and a side surface of the first conductor film in the opening, and formed on a side surface of the opening. Formed in the semiconductor layer on the sidewall of the third insulating film and on the bottom surface of the opening. The semiconductor device according to claim and the emitter region of the first conductivity type, in that it comprises to be. 3. An element isolation region and an electrode isolation by burying a first insulating film in an element isolation formation scheduled region and an electrode isolation formation scheduled region on a semiconductor substrate on which a collector layer of the first conductivity type is formed. Forming a region and an intrinsic element region
And a second step of forming a base layer made of a semiconductor layer of the second conductivity type on the entire surface of the substrate, and a second insulating film and an oxidation resistant insulating film on the base layer so as to cover the intrinsic element region. A third step of forming a laminated body in which films are sequentially laminated, a fourth step of forming a second conductive type first conductor film covering the base layer and the laminated body, and the first conductivity After forming a third insulating film on the body film, the third insulating film, the first conductor film, and the stack on the intrinsic element region until the base layer is exposed to form an emitter region. A fifth step of opening the body to provide an opening, a sixth step of forming a side wall made of a fourth insulating film on a side surface of the opening, and a second conductivity type second step on the entire surface of the semiconductor substrate. After forming the conductive film, the first conductive type impurities are diffused from the second conductive film to the base layer. First in the base layer by making
A seventh step of forming a conductive type emitter region, and a method of manufacturing a semiconductor device. 4. A semiconductor substrate having a first conductivity type intrinsic element region and an element isolation region formed thereon, a base layer made of a second conductivity type semiconductor layer formed on the semiconductor substrate, and the intrinsic element. A laminated body in which a first insulating film and an oxidation resistant insulating film are sequentially laminated on the base layer so as to cover the region, and a second conductivity type first formed so as to cover the laminated body and the base layer. Conductor film, a second insulating film formed on the first conductor film, and the second insulating film on the intrinsic element region until the base layer is exposed to form an emitter region. Insulation film, first
And an opening provided by opening the conductor film and the laminated body, a side wall made of a third insulating film formed on a side surface of the opening, and formed in the base layer on the bottom surface of the opening. A first conductivity type emitter region, and a semiconductor device.