JPH05175193A - Formation of circuit pattern of semiconductor device - Google Patents

Abstract

PURPOSE:To form a fine pattern on the foundation difference in level with high accuracy by freely combining the respective advantages at the time of pattern formation by means of a multilayer resist process and a positive type resist together with a negative type resist according to the pattern shape to be formed. CONSTITUTION:In the case a region 92 is to be exposed after forming a slit pattern 91 and a second upper layer resist 6b on a first upper layer resist 6a by using a negative type photoresist, and a second upper layer resist 6b is a positive type photoresist, a lower layer resist pattern 100 is formed. Here, since the lower layer resist pattern 100 is formed by a multilayer resist process so as to be little influenced by the foundation difference in level while generating little rounding of a corner part. This method is effective for the circuit pattern formation of an element region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to a semiconductor device (hereinafter referred to as L
The present invention relates to a method of forming a circuit pattern in a photolithography process using a resist film, which is a manufacturing process of (SI).

[0002]

2. Description of the Related Art Conventionally, as a method of forming a circuit pattern in a photolithography process in the manufacture of an LSI, a photoresist containing an organic material as a main component is formed in a thin film on the surface of a wafer-like semiconductor substrate, and a circuit pattern to be formed is formed. A corresponding photomask is used, the photoresist film is subjected to an exposure treatment, and then subjected to a development treatment. In the exposure processing, for example, single wavelength light in the far ultraviolet region is often used, but it is also known that an electron beam is used.
In that case, the photomask is not used, and the circuit pattern is directly drawn on the photoresist by the electron beam.

After further exposure and development, the photoresist becomes a resist pattern corresponding to the circuit pattern, and the resist pattern is used as a masking material for etching the underlying film and implanting impurities into the underlying film (ion implantation).
Is applied.

As described above, the exposure processing is also known when, for example, a single wavelength light in the far ultraviolet region is used, an electron beam is used, or an X-ray or an ion beam is used. However, it is common to use a single-wavelength light in the far ultraviolet region or an electron beam, and it has been put to practical use.

Photoresists are generally classified into two types, a positive type resist in which exposed portions are removed by a developing process, and a reverse exposed portion remains in the developing process and an unexposed portion is left. Negative resists that are removed are known, and both have been put to practical use.

[0006] Usually, an LSI is formed by overlapping circuit patterns of many layers, and therefore, there are many cases where the underlying layer on which the resist pattern is formed has a structural step. Further, the LSI is always required to have high speed and high integration, and it is an essential technique to form a finer circuit pattern with high accuracy even on a step.

[0007]

However, in the conventional circuit pattern forming method, more specifically, in the resist pattern forming method in the photolithography process, for example, the minimum dimension of the circuit pattern to be formed is 0.6 to 0.8μ
When it was about m, it was not a big problem, but the miniaturization of the circuit pattern progressed and the minimum dimension of the circuit pattern to be formed was, for example, around 0.5 μm.
When the thickness is 0.5 μm or less, some problems described below cannot be ignored.

An example of the problem will be described with reference to FIG.

151 and 152 are structural stepped portions 153.
A stepped upper part 151 and a stepped lower part 1
A resist pattern 154 that intersects with the step portion 153 is formed on 52.

FIG. 15 (a) is a sectional view seen from the side, FIG.
15B is a plan view seen from above, and FIG. 15C is a perspective view seen obliquely from above. The resist pattern 154 has a different film thickness between the upper step 151 of the base and the lower step 152, so that the dimension is slightly different.
At 53, a dimensional variation locally occurs. Therefore, the dimensional accuracy of the resist pattern 154 at the portion having the underlying step 153 is significantly reduced.

A multi-layer resist pattern is generally known as a method for solving the deterioration of the dimensional accuracy of the resist pattern caused by the influence of such a step difference in the underlying layer. An example will be described with reference to FIGS. 16 and 17.

Reference numeral 155 denotes a first resist film (hereinafter referred to as a lower layer resist) formed to flatten the steps of the bases 151 and 152, and the surface of the lower layer resist 155 is considerably flattened. 156 is the lower layer resist 15
5, which is an intermediate layer formed on the entire surface of 5 and is capable of spin coating, which is called spin-on-glass (hereinafter referred to as SOG), or a chemical vapor deposition (hereinafter referred to as CVD) method. It may also be a refractory metal film such as a tungsten film formed by a sputtering method. 157 is a second resist film formed on the entire surface of the intermediate layer 156 (hereinafter referred to as an upper layer resist)
That is, this is a portion where a pattern corresponding to the circuit pattern is formed by exposure and development processing. The intermediate layer 156 may not be necessary depending on the material of the upper layer resist 157 and the lower layer resist 155, but in the example shown here, a three layer structure (lower layer resist 155, intermediate layer 156, upper layer resist 157) is shown. ..

The formation of a multi-layer resist (three-layer resist) pattern is shown in FIGS. 17A to 17D in the order of steps and will be described. FIG. 17A shows a base 1 having a step portion 153.
51, 152, a lower layer resist 155, an intermediate layer 156,
With the upper layer resist 157 formed, the upper layer resist 157 is exposed and developed to form a resist pattern 157 '(FIG. 17B).
Further, the intermediate layer 156 is etched using the upper layer resist pattern 157 'as a mask material, and the upper layer resist pattern 157' is transferred onto the intermediate layer 156 (FIG. 1).
7 (c)). Further, the lower layer resist 155 is subjected to etching treatment using the upper layer resist pattern 157 'and the intermediate layer pattern 156' as a mask material, and the upper layer resist pattern 157 'is transferred to the lower layer resist 155 (FIG. 17 (d)). .. Here, if a positive photoresist is used as the lower layer resist 155, after the lower layer resist 155 is subjected to exposure processing (entire exposure processing) using the upper layer resist pattern 157 'and the intermediate layer pattern 156' as mask materials. Even after the development process, the pattern formation of the lower layer resist 155 can be similarly performed.

As shown in FIGS. 17 (a) to 17 (d) above, the influence of the underlying step can be remarkably reduced when the pattern of the upper resist 157 is formed by using the multi-layer resist process. 16 (b) and FIG.
As shown in FIG. 6 (c), the base step portion 153 and the step upper portion 1
It is possible to remarkably suppress the deterioration of the dimensional accuracy on the 51 and the lower part of the step 152. It is generally known that the effect of the step difference in the underlying layer can be reduced by using the multi-layer resist process, but there are some problems that are difficult to solve even by using the multi-layer resist process. Will be explained.

FIG. 18 (a) is a graph showing the correlation between the exposure energy applied to the resist during the exposure process for a general positive type resist and the dimension of the resist pattern after the development process. FIG. 18B is a graph showing a similar correlation in a general negative resist. Generally, the amount of change in the dimension of the resist pattern becomes smaller as the exposure energy increases. Therefore, as a condition for obtaining a more stable dimension, for example, for a very thin line pattern, use a positive type resist. For very fine slit patterns and minute contact patterns, a negative resist is used, and patterning is performed with higher dimensional accuracy by patterning in a region where the dimensional change of the resist pattern with large exposure energy is small. Will be possible. However, when forming a very small resist pattern whose minimum dimension is, for example, about 0.5 μm or less, the circuit pattern shape is different from the designed one in addition to the dimensional accuracy. It may happen. In particular, the roundness at the corners of the pattern becomes the main cause.

In FIG. 19A, when a positive resist is used for forming a rectangular pattern, FIG.
Will be described with reference to an example in which a negative resist is used to form a contact pattern of multiple small rectangles.

In FIG. 19 (a), an area not shown by the exposure light is shown in an area 191a. 192a
Indicates a resist pattern when the exposure energy is low, 193a indicates a resist pattern when an appropriate exposure energy is applied, and 194a indicates a resist pattern when an excessive exposure energy is applied. Generally, the dimensional change amount in the long side direction is larger than the dimensional change amount in the short side direction in the rectangular pattern, and when excessive exposure energy is applied, the resist patterns 192a, 193a in the short side direction, The amount of dimensional change of 194a does not change so much, but the amount of dimensional change in the long side direction becomes significantly large, which eventually changes the shape of the rectangular pattern. This phenomenon is particularly caused when the pattern size in the short side direction is, for example, about 0.5 μm, and when a minute resist pattern is formed, the shape change is large and the change amount is about 0.2 μm or more. There is also.

In FIG. 19 (b), the region 191b is also a region not irradiated with light for exposure,
It is an example regarding formation of a contact pattern when a negative resist pattern is used. 192b shows a resist pattern when the exposure energy is low.
93b shows a resist pattern when an appropriate exposure energy is applied, and 194b shows a resist pattern when an excessive exposure energy is applied. In this case as well, the dimension of the contact pattern is, for example, 0.
In the case of about 5 to 0.6 μm or less, the resist patterns 192b, 193b, 194
The shape of b is circular even if the design shape of the contact pattern is rectangular. Therefore, for example, when the dimension of the contact pattern in the short side direction is formed to be the optimum dimension, However, the dimension may become extremely small, and a dimension change amount of about 0.2 μm or more may occur. In this case, of course, the area of the contact pattern becomes significantly smaller than the designed value, so even if the circuit pattern is formed after the etching process in particular, the electrical resistance value in the contact pattern is not designed. There are variations compared to the value of, and the value becomes extremely high.
However, if the energy applied during exposure is set low so that a certain area of the contact pattern can be obtained, the dimensional accuracy will be reduced and the contact pattern will be formed in a substantially circular shape. The dimension in the side direction becomes a value considerably larger than the design value, which causes a problem that there is no margin at the time of superposition. As described above, the causes thereof are rounded at the corners of the circuit pattern, and the influence cannot be ignored as the size of the circuit pattern becomes finer. Especially 0.
It has become a serious problem in forming a circuit pattern having a dimension of about 5 μm or less.

According to the present invention, when the minimum dimension of the above-mentioned circuit pattern is, for example, about 0.5 μm or even 0.5 μm or less, a minute pattern is formed with high precision even on a step of the base, for example, Even if a multi-layer resist process is used or a positive resist or a negative resist is used depending on the shape of the circuit pattern, the problem that cannot be solved by any means, that is, the resist pattern has a rounded corner portion At the same time, it is difficult to form the long-side dimension and the short-side dimension of the pattern at the same time with high accuracy, and the problem that the pattern shape changes at the same time. It is an object of the present invention to provide a method for forming a resist pattern that can solve all problems.

[0020]

The present invention is directed to a resist pattern forming method in a photolithography process, which is a manufacturing process of LSI, in which a multi-layer resist process generally used and pattern formation using a positive type resist and a negative type resist are formed. The advantages of each time are freely combined depending on the pattern shape to be formed.

[0021]

Since the present invention employs the above-described forming method, the resist having a minimum dimension of about 0.5 μm or less, even if there is a structural step on the base on which the resist pattern is to be formed. It is possible to form a resist pattern with a high degree of accuracy and with a significantly reduced shape change caused by rounding the corners of the pattern.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Three typical embodiments of the present invention are shown in FIGS. 1, 2 and 3 and will be described in order.

In FIGS. 1 to 3, reference numerals 1 and 2 are bases having a step portion 3 on the structure, and a lower layer resist 4 film is first formed on the step upper portion 1 and the step lower portion 2.
The surface of the lower layer resist 4 is almost flattened. An intermediate layer 5 is formed on the lower layer resist 4, and an upper layer resist 6a is formed on the intermediate layer 5 (FIG. 1A). First, as shown in FIGS. 1B, 2A and 3A, the upper layer resist 6a is exposed and developed to form an upper layer resist pattern 6a '.

First, the first embodiment will be described.

From FIG. 1B, the upper layer pattern 6 is further formed.
The intermediate layer 5 is etched by using a'as a mask, and the upper layer pattern 6a 'is transferred onto the intermediate layer 5, that is, the intermediate layer 5 is patterned (FIG. 1C).

Further, an upper layer resist film 6b is formed again on the lower layer resist 4 and the intermediate layer pattern 5'patterned as described above (FIG. 1 (d)). Here, when a mixed layer (referred to as an interlayer) is formed between the lower layer resist 4 and the second upper layer resist 6b, for example, when the lower layer resist 4 has high solubility in the solvent of the second upper layer resist 6b. It is known that the generation of an interlayer can be significantly reduced by performing a surface treatment or the like using a hydrocarbon such as n-heptane or n-hexane in advance. Depending on the combination of 6b and the lower layer resist 4, it can be processed as required.

Further, the second upper layer resist 6b is exposed and developed to form a second upper layer resist pattern 6b '(FIG. 1 (e)). Further, the intermediate layer pattern 5'is etched by using the second upper layer resist pattern 6b 'as a mask, and the intermediate layer pattern 5'is formed.
Then, the common portion with the second upper layer resist pattern 6b 'is transferred, and then the second resist pattern 6b' is removed (FIG. 1 (f)).

Further, with the intermediate layer pattern 5 '' formed in the common portion of the first resist pattern 6a 'and its pattern and the second resist pattern 6b' as an etching mask, the lower resist 4 is exposed to oxygen, for example. When an etching process using plasma or the like is performed, the intermediate layer pattern 5 ″ is transferred onto the lower layer resist 4 (see FIG. 1).
(G)).

The method of forming a resist pattern according to the embodiment shown in FIGS. 1 (a) to 1 (g) further includes a positive type resist and a negative type resist for the first upper layer resist 6a and the second upper layer resist 6b. By using both resists, the effect can be expected in the following four different embodiments according to the circuit pattern to be formed.

4, FIG. 5, FIG. 6, FIG. 9, FIG.
An example will be described below.

A positive photoresist is used as the first upper layer resist 6a, and the line pattern 4 is formed as shown in FIG. 4 (a).
1 is formed, and after the second upper layer resist 6b is formed, the second upper layer resist 6b in FIG. The lower resist pattern 4'is formed as shown by 50 in FIG. 5 (a). Since the lower layer resist pattern 4'in FIG. 1 is formed by the multi-layer resist process, it is hardly affected by the step shape of the base, and the corners are hardly rounded. In addition, the dimensional accuracy in the vertical direction and the horizontal direction also has the first upper layer resist pattern 6a and the second upper layer resist pattern 6a.
Since the optimum processing can be performed each time the exposure processing in (b) is performed, it is possible to form almost the same as the designed one. Therefore, the finally formed lower layer resist pattern 50 has substantially the same dimensions and shape as the designed one. As an application to the actual circuit pattern,
An example will be described with reference to FIGS. Reference numeral 51 denotes a base substrate or the surface of a silicon oxide film, on which a first electrode pattern 52 is formed. For example, a first interlayer insulating film 53 having a silicon oxide film as a main component is formed,
A second electrode pattern 54 is formed on the inter-layer insulating film 53. Further, a second interlayer insulating film 55 is formed, and contact patterns 56 and 57 are formed on the first interlayer insulating film 53 and the second interlayer insulating film 55. 56
The contact pattern shown in is the first electrode pattern 52.
The contact pattern 57 is formed on the second electrode pattern 54. Further, a thin film 58 for forming a wiring material is formed on the entire surface, and a resist pattern 59 for forming the wiring pattern is formed. In the case where the resist pattern 59 for forming the wiring pattern is formed, the first embodiment of the present invention is effective.

In the next embodiment, a positive type photoresist is used as the first upper layer resist 6a in FIG.
As shown in (a), a line pattern 41 is formed,
When the second upper layer resist 6b is a negative type resist,
The lower layer resist pattern 4'is formed as shown in FIG.

The resist pattern 60 having the shape shown in FIG. 6A is applied to an actual circuit pattern as shown in FIG.
An example will be described in (b).

Reference numeral 61 is an element region, 62 is an element isolation region, and 63 is a gate electrode pattern. Although not shown, an interlayer insulating film is formed on the entire surface, and 64a, 6
Reference numeral 4b is a contact pattern formed on the interlayer insulating film. 64a is formed in the element region 61 and 64b is formed in the gate electrode pattern 63.

This embodiment is particularly effective for forming the gate electrode 63.

As a third embodiment, a negative type photoresist is used as the first upper layer resist 6a in FIG. 1, a slit pattern 91 is formed as shown in FIG. 9A, and a second upper layer resist 6b is formed. When the exposure process is performed in the area 92 shown in FIG. 9 (b) after the formation of the second upper layer resist 6b and the second upper layer resist 6b is a positive photoresist, the lower layer resist pattern 4'is Figure 10
It is formed as shown at 100 in (a). Since the lower layer resist pattern 4'is formed by the multi-layer resist process as well, it is hardly affected by the step of the underlying layer and the corners are hardly rounded. In the first and second embodiments, The obtained effect can be expected in this embodiment as well.

As an application to an actual circuit pattern, FIG.
An example will be described with reference to 0 (b) and FIG. 10
1 is an element region, 102 is an element isolation region, and 103
Is a gate electrode pattern. An interlayer insulating film 104 is formed, and a contact pattern 104 is formed on the interlayer insulating film. Further, the wiring pattern 105 is formed.

This embodiment is particularly effective when the element region 101 is formed.

In the fourth embodiment, a negative type photoresist is used as the first upper layer resist 6a in FIG. 1, and a slit pattern 91 is formed as shown in FIG. In the case where a negative type resist is also used as the resist 6b, the lower layer resist pattern 4'is formed as shown in FIG. 11 (a).

As an application of the resist pattern 110 having the shape shown in FIG. 11A to an actual circuit pattern,
Embodiments will be described with reference to FIGS. 11B and 11C.
111 is an element region, 112 is an element isolation region, and 11
3, 115 and 116 are the first interlayer insulating film and the second, respectively.
And the third interlayer insulating film, 114 is the first wiring pattern, and 117 is the contact pattern formed on the first, second, and third interlayer insulating films 113, 115, and 116. Is. Reference numeral 118 is a thin film that forms the second wiring material and is formed on the entire surface. A resist pattern 119 for forming the wiring pattern is formed.

This embodiment is effective in the case of forming a wiring pattern.

The second embodiment different from the first embodiment described above
A typical embodiment of the above will be described with reference to FIG.

FIG. 2A shows the upper resist pattern 6a '.
Is formed, the intermediate layer 5 is further etched using the upper layer pattern 6a 'as a mask, and the upper layer pattern 6a' is transferred to the intermediate layer 5 (FIG. 2B).
Further, a second exposure process is applied to the lower layer resist 4 (FIG. 2 (c)). The lower layer resist 4 in the region below the upper layer resist pattern 6a 'or the intermediate layer pattern 5'is not exposed with respect to the exposed region 7a. That is, the lower layer resist 4 is exposed except for the upper layer pattern 6a '.
The area 4b on which a has been applied is exposed (FIG. 2C).

Further, development processing is applied to the lower layer resist 4. In this case, when a positive photoresist is used as the lower layer resist 4, it is formed as shown in FIG. 2D, and when a negative photoresist is used, it is formed as shown in FIG. 2E.

In the case of this embodiment, the pattern formed by exposing the lower layer resist by exposure is affected by the step difference of the underlying layer, but the upper layer resist pattern is formed by the multi-layer resist structure. Hardly receives.

In the resist pattern forming method according to the embodiment shown in FIGS. 2A to 2E, both the positive resist and the negative resist are used for the upper layer resist 6a and the lower layer resist 4. With respect to the circuit pattern to be formed, the effect can be expected in the following four different embodiments.

FIG. 4, FIG. 7, FIG. 8, FIG. 9, FIG.
An example will be described below.

A positive type resist is used for the upper layer resist 6a, and the line pattern 41 shown in FIG.
When the lower layer resist is exposed in the area indicated by 42 in FIG. 4B after being formed on the upper layer resist 6a and the intermediate layer 5 in FIG. The resist pattern 4'is shown in FIG.
It is formed in a cross shape as shown at 70 in (a). The pattern portion formed by the exposure processing of the upper layer resist is hardly affected by the step shape of the underlying layer, but the pattern portion formed by the exposure processing of the lower layer resist is affected by the step shape of the underlying layer. However, the roundness of the corner hardly occurs, and the number of steps is smaller than that of the four types of the first embodiment, so that it can be sufficiently applied depending on the circuit pattern forming step. It will be described as four types of examples of the second example.

The resist pattern 70 having the shape shown in FIG. 7A is applied to an actual circuit pattern as shown in FIG.
An embodiment will be described with reference to FIGS. Reference numeral 71 is a base substrate or the surface of a silicon oxide film, and 72 is a first electrode pattern. A first interlayer insulating film 73 is formed, and a first wiring pattern 74 is formed thereon. Further, a second interlayer insulating film 75 is formed, and contact patterns 76 are formed on the first and second interlayer insulating films 73 and 74.
Are formed. Further, a second wiring pattern 77 is formed.

This embodiment is effective in the case where the first wiring pattern 74 is formed.

In the next embodiment, a positive type resist is used for the upper layer resist 6a in FIG. 2, a line pattern 41 is formed as shown in FIG. 4 (a), and a negative type resist is used for the lower layer resist 4. In this case, the lower resist pattern 4'is formed as shown in FIG.

The resist pattern 80 having the shape shown in FIG. 8A is applied to an actual circuit pattern as shown in FIG.
An embodiment will be described with reference to FIGS.

Reference numeral 81 is a base substrate or a silicon oxide film surface, reference numeral 82 is a gate electrode pattern, and 83, 85, 87.
Are first, second and third interlayer insulating films. 84 is the first wiring pattern, 86 is the second wiring pattern, and 89 is the third
Is a wiring pattern. A first contact pattern 88a is formed on the gate electrode pattern 82, and a second contact pattern 88b is formed on the first wiring pattern 84.
It is electrically connected to the third wiring pattern 89 via 8b.

This embodiment is effective in the case of forming the second wiring pattern.

In the third embodiment, the negative resist of the upper resist 6a in FIG. 2 is used, and the slit pattern 91 is formed as shown in FIG. 9A, and the lower resist 4 in FIG. In the case where a resist is used, the lower layer resist pattern 4'is formed as shown at 120 in FIG. As an application of the resist pattern 120 having the shape shown in FIG. 12A to an actual circuit pattern, an embodiment will be described with reference to FIGS. 12B and 12C. 121 is an element region, 122 is an element isolation region, 123 is a gate electrode pattern, 124 is a first interlayer insulating film, and a first contact pattern 125.
Numeral 126 in which is formed is a wiring pattern, a second interlayer insulating film 127 is formed, and a second contact pattern 128 is formed in the first and second interlayer insulating films. Further, a second wiring pattern 129 is formed.

In this embodiment, the wiring pattern 1 is used.
This is effective when 26 is formed.

In the fourth embodiment, a negative type resist is used for the upper layer resist 6a in FIG. 2, a slit pattern 91 is formed as shown in FIG. 9A, and a negative type resist is also used for the lower layer resist. In this case, a contact pattern is formed on the lower layer resist pattern 4'as shown by 130 in FIG. 13 (a). The contact pattern 130 shown in FIG. 13A is most likely to be applied to an actual circuit pattern. For example, FIG.
As shown in (b), very normal wiring patterns 131, 1
Patterns 133a, 1 for electrically connecting 32, 134
33b, and contact patterns 56, 57, 64a, 64 in all the embodiments shown to date.
b, 76, 88a, 88b, 104, 117, 125,
It can also be applied to 128, and its effect is very large.

A method according to the present invention which is different from the method applied to the four kinds of embodiments of the first embodiment and the method applied to the four kinds of embodiments of the second embodiment described above. The pattern forming method of the third embodiment will be described with reference to FIG.

FIG. 3A shows the upper resist pattern 6.
a'is formed, and in this case, it is a base having two steps 3a and 3b, and the bottom of the step has a slit shape in a very small area. When a relatively large step is formed in a slit shape in such a very small area as described above, it is applicable to the case where the photoresist inside the slit (the lower layer resist 4 in this example) is difficult to remove. is there.

From FIG. 3 (a), the pattern transfer to the intermediate layer 5 and the upper layer resist pattern 6a 'are removed (see FIG. 3).
(B)) is the same as the first embodiment shown in FIG. 1 until the second upper layer resist 6b is formed (FIG. 3C), but the second upper layer resist 6b is formed. Exposure process 7b
Is for normal exposure, and further for the bottom of the step of the base, especially where the lower layer resist 4 is difficult to remove.
By performing additional exposure separately from the pattern formation, the lower layer resist 4 can be already considerably thinned after the development processing of the second upper layer resist 6b.

FIGS. 14A to 14C show an embodiment as an application to actual pattern formation. However, in this case, a positive photoresist is used for the lower layer resist 4 and the second upper layer resist 6b.

First, a line pattern as shown by 140 in FIG. 14A is formed on the intermediate layer 5 to form a positive type resist as the second upper layer resist 6b, and then FIG.
As shown in (b), the exposure processing is applied to the area 140 '. Thereafter, patterns up to the lower layer resist 4 are formed in the order shown in FIG.

Reference numeral 141 is an element region, 142 is an element isolation region, and 143 and 145 are first and second wiring patterns. 144 and 146 are first and second interlayer insulating films, and 147 is a material for forming a third wiring pattern and is formed over the entire surface. The resist patterns 4 ', 5', 6b "are patterns corresponding to the wiring patterns, and are examples in which there is a structural underlying step as shown in FIG. 14C between the patterns.

[0064]

As described in detail above, according to the manufacturing method of the present invention, a positive or negative resist is used in the formation of a circuit pattern of a semiconductor device in consideration of the shape and accuracy of the final circuit pattern. Since the patterning is performed by the combined multi-layer resist, the influence of the underlying step can be reduced, and a circuit pattern having a dimension of 0.5 μm or less with very little error in design accuracy can be manufactured.
Therefore, highly reliable LSI can be manufactured with high yield.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a second embodiment of the present invention.

FIG. 3 is a third embodiment of the present invention.

FIG. 4 is a pattern example (1).

FIG. 5 Pattern example (2)

FIG. 6 is a pattern example (3).

FIG. 7 is a pattern example (4).

FIG. 8 is a pattern example (5).

FIG. 9 is a pattern example (6).

FIG. 10 is a pattern example (7).

FIG. 11 is a pattern example (8).

FIG. 12 is a pattern example (9).

FIG. 13 is a pattern example (10).

FIG. 14 is a pattern example (11).

FIG. 15 Problems of Conventional Example

FIG. 16 Conventional Example 1

FIG. 17 Conventional Example 2

FIG. 18: Correlation diagram of exposure energy and resist pattern size

FIG. 19: Example of rectangular pattern

[Explanation of symbols]

 1, 2 Underlayer 3 Stepped portion 4 Lower layer resist 5 Intermediate layer resist 6 Upper layer resist

Claims (3)

[Claims] 1. When forming a circuit pattern of a semiconductor device, a positive type resist and a negative type resist are combined on a base layer formed on a semiconductor substrate in consideration of the shape and accuracy of the final pattern. And forming a resist film of three or more layers of an upper layer, an intermediate layer and a lower layer, patterning the resist film of the upper layer, patterning the intermediate layer using the pattern as a mask, and then again patterning the intermediate layer. A method for forming a circuit pattern of a semiconductor device, comprising: forming a resist film on the upper surface containing the resist, patterning the resist film with a pattern different from the pattern, and using the mask as a mask to pattern the intermediate layer and the lower layer resist. 2. When forming a circuit pattern of a semiconductor device, a positive type resist and a negative type resist are combined on a base layer formed on a semiconductor substrate in consideration of the shape and accuracy of the final pattern. In addition, an upper layer, an intermediate layer, and a lower layer of three or more resist films are formed, the upper resist film is patterned, the intermediate layer is patterned using the pattern as a mask, and then an exposure region different from the pattern formation is formed. 2. A method for forming a circuit pattern of a semiconductor device, which comprises subjecting the lower layer resist to an exposure treatment to pattern the lower layer resist. 3. When a circuit pattern of a semiconductor device is formed, a positive type resist and a negative type resist are combined on a base layer formed on a semiconductor substrate in consideration of the shape and accuracy of the final pattern. And forming a resist film of three or more layers of an upper layer, an intermediate layer and a lower layer, patterning the resist film of the upper layer, patterning the intermediate layer using the pattern as a mask, and then again patterning the intermediate layer. A semiconductor film characterized in that a resist film is formed on the upper surface including the above, and the resist film is exposed to a portion where the lower layer resist is difficult to be removed due to the influence of the step of the underlying layer, and the lower layer resist is patterned. Method for forming circuit pattern of device.