JPH05173952A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To provide the data transmission equipment which receives data, which is transmitted through plural parallel input-side transmission lines, up to the limit of storage capability of transmission lines and transmit transmission data groups to an output-side transmission line in the order of arrival and arbitrates the output in the case of staying of transmission data groups to transmit them to the output-side transmission line. CONSTITUTION:It is detected by a contention detecting part 7 whether the difference of arrival time between data 1 and 2 inputted to two data transmission groups 10 to 30 and 40 to 60 provided in parallel is within the range of a certain time difference or not; and if it is within this range, data arriving later is temporarily stopped in the data transmission line 20 or 50. An arbitration control part 80 arbitrates data with respect to the output order in accordance with data congestion in data transmission lines 10 to 30 and 40 to 60 and outputs data to an output-side data transmission line 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device, and more particularly to a data transmission device for serially transmitting data transmitted through a plurality of parallel input side transmission lines to an output side transmission line. Regarding the improvement of.

[0002]

2. Description of the Related Art In a data processing device using an electronic computer or the like, a plurality of processing devices are connected by communication by digital signals. Then, when the data processing is distributed and processed by a plurality of processing devices, the results obtained by each processing device are sent to a second processing device different from these processing device groups, and the second processing device The process is executed using the plurality of received results. As such a data transmission device, there is one disclosed in Japanese Patent Laid-Open No. 62-17486. Further, as another example of the data transmission device, there is one disclosed in JP-A-1-108660.
The data transmission device described in Japanese Patent Application Laid-Open No. 62-174856 has an arbitration function of which data is transmitted when two sets of data are simultaneously input and the time difference is within a fixed time. Not not. On the other hand, JP-A-1-
In the data transmission device described in Japanese Patent No. 108660,
An arbitration function is provided so that the arrival time difference between the two sets of data is within a fixed time difference range, regardless of the time difference.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the data transmission device described in Japanese Patent No. 74856, the time required to process the distributed data differs depending on the received data and the content of the processing required for the device. Are not always sent in the same order and at the same time intervals. Further, if the transmission path itself can be provided with a buffer function that reduces the retention of the transmission data group caused by the variation in the processing time in the second processing device as much as possible, the hardware amount of the processing device can be reduced. it can.

Therefore, the main object of the present invention is to be able to receive data transmitted via a plurality of parallel input side transmission lines up to the limit of the capacity of the transmission lines and to arrive at the transmission data group. It is an object of the present invention to provide a data transmission device capable of sequentially transmitting to an output side transmission line, arbitrating the output when there is a stay in a transmission data group, and transmitting to the output side transmission line.

[0005]

The present invention is a data transmission device for serially transmitting a plurality of data transmitted via a plurality of parallel input side transmission lines to an output side transmission line. A conflict detection means for detecting that two sets of data exist on arbitrary two sets of transmission lines among a plurality of parallel transmission lines and that the arrival time difference between the two sets of data is within a certain time difference range. In response to the transmission permission signal sent from the output side transmission path, the transmission order having the conflict detection function is arbitrated in the output order depending on the data congestion of each of the plurality of parallel input side transmission paths, Arbitration control means for transmitting to the transmission path on the output side.

[0006]

The data transmission device according to the present invention responds to the transmission permission signal sent from the transmission line on the output side.
Arrangement is performed so that the arrival order of data and the retention of data may be mitigated in a plurality of transmission paths having a contention detection function, and the data sent from the corresponding transmission path is physically It is possible to sequentially transmit to the output side transmission line within the transfer time peculiar to the transmission line without receiving the delay time required for the arbitration control even if the capacity is limited.

[0007]

1 is a schematic block diagram of an embodiment of the present invention. Referring to FIG. 1, two data transmission lines 10 and 2 are provided.
0, 30 and 40, 50, 60 are provided in parallel to detect whether or not the arrival time difference between the data 1 and the data 2 which are the inputs to the data transmission lines 10 and 40 is within a certain time difference range. Therefore, the competition detection unit 70 is provided. The conflict detection unit 70 does not adjust the time when the arrival time difference between the data 1 and the data 2 is outside the fixed time difference range, and adjusts the time when the arrival time difference is within the fixed time difference range. The data transmission path 20 or 50 is temporarily stopped until it is out of the range of a certain time difference.

The arbitration control unit 80 receives the transmission permission signal AK100 from the data transmission line 100, which is the output side transmission line, in response to the parallel input side transmission lines 10, 20,
The output order is arbitrated according to the congestion degree of the respective data of 30 and 40, 50, 60, and the data is output to the data transmission line 100.

Next, a specific operation of the embodiment shown in FIG. 1 will be described. In the initial state, the data transmission path 100 on the output side is in a state capable of receiving data.
The ck signal AK100 is returned to the arbitration control unit 80. The arbitration control unit 80 uses the data transmission path 100 on the output side.
Receiving the Ack signal AK100 from the data transmission line 30
And 60 output Ack signals AK30 and AK60. The Ack signals AK30 and AK60 do not permit transmission to the data transmission line 100 at the same time, but one of them permits transmission to the data transmission line 100. In this embodiment, for example, consider a state in which the data transmission line 60 is permitted and the data transmission line 30 is prohibited. When data arrives at the data transmission line 10, the data and the transmission signal c10 are transmitted to the data transmission line 2
The transmission signal c10 is transmitted to the data transmission line 30 via 0, and is also transmitted to the arbitration control unit 80. The arbitration control unit 80 confirms that there is no data in the data transmission path 60, and when there is no data, permits the data transmission path 30 to perform data transmission to the data transmission path 100.
Data transmission to the data transmission line 100 is prohibited for the data transmission line 60.

The data transmission line 30 is the data transmission line 100.
The data is transmitted to the data transmission line 100 because the transmission to the data transmission line 100 is permitted. When the data passes through the data transmission line 100, the Ack signal AK30 is returned from the data transmission line 100 to the data transmission line 30 via the arbitration control unit 80, and the data transmission line 30 sends the data to the data transmission line 100. Allow Next, when the data arrives at the data transmission line 40, the data and the transmission signal c20 are transmitted to the data transmission line 60 via the data transmission line 50, and the transmission signal c20 is also transmitted to the arbitration control unit 80. It The arbitration control unit 80 confirms that there is no data in the data transmission line 30, and if there is no data, the data transmission line 6
0 is permitted to transmit data to the data transmission line 100, and data transmission line 1 is transmitted to the data transmission line 30.
Data transmission to 00 is prohibited. Since the data transmission path 60 is permitted to be transmitted to the data transmission path 100, it transmits data to the data transmission path 100. And the data transmission line 1
When the data passes 00, the Ack signal AK60 is returned from the data transmission line 100 to the data transmission line 60 via the arbitration control unit 80, and the data transmission from the data transmission line 60 is permitted.

Next, the case where the data 2 is input later than the data 1 will be described. When the data arrives at the data transmission line 10, the transmission signal c10 is sent to the data transmission line 20 and also to the contention detection unit 70, and the contention detection unit 70 arrives at the data transmission line 40 within a certain time difference. When the data exists, the data 2 is temporarily stopped on the data transmission path 50, and when the data 1 passes through the data transmission path 20, the data 2 stopped on the data transmission path 50 starts to move. In this way, the conflict detection unit 70 detects the degree of competition between the data 1 and the data 2 and temporarily suspends the data having a late arrival time on the data transmission path 20 or the data transmission path 50 to prevent malfunction in the arbitration control unit 80. To prevent.

FIG. 2 is a more specific block diagram of an embodiment of the present invention, and FIG. 3 is a transfer control unit 11 shown in FIG.
4 is a concrete block diagram of the above, and FIG. 4 is a concrete block diagram of the transfer control unit 101 shown in FIG.

First, with reference to FIGS. 2 to 4, a specific configuration of an embodiment of the present invention will be described. Figure 1 above
The data transmission paths 10, 20, 30, 40, 50 and 60 shown in FIG.
1, 51, 61 and data holding circuits 12, 22, 32, 4
2, 52, 62. Transfer control unit 1
1, 21, 31, 41, 51 and 61 respectively perform handshake transfer control by one transmission signal input, one transmission permission signal input, one transmission signal output and one transmission permission signal output. Further, the transfer control unit 101 has a built-in function of taking the logical sum of two different transmission signal inputs, and the transfer control units 11, 21, 3 are used for transfer control.
Handshake control similar to 1, 41, 51 and 61 is performed. More specifically, the transfer control unit 11 includes two-input NAND gates 111 and 115, a three-input NAND gate 112 and inverters 113 and 115 as shown in FIG. 3, and other transfer control units 21, 31, 41. , 51, 61
Is also configured in the same manner as the transfer control unit 11. As shown in FIG. 4, the transfer control unit 101 uses the 2-input NAND gate 12
It includes 4- and 3-input NAND gates 121 and 122 and an inverter 123.

As shown in FIG. 2, the conflict detection section 70 includes a D type flip-flop 71, 72, an AND gate 73,
74, 75, 76, NOR gate 77, and driver 7
8 and an OR gate 79. The arbitration control unit 80 is NA
ND gates 81, 82, 83, 84 and AND gate 8
5,86 and D type flip-flops 87,88 and NO
R gates 89 and 90 are included.

Next, the operation of the embodiment shown in FIG. 2 will be described. In the initial state, the reset signal is applied to the transfer control units 11, 21, 31, 41, 51, 61 and 101, the AND gates 75, 76, 85, 86 and the NAND gates 82, 83. As a result, the transfer control units 11, 21, 31, 41, 51 and 61 are each reset to the initial level, the Q1 output of each is set to the “H” level, and the Q2 output is also set to the “H” level. Transfer control unit 10
When 1 is reset, its Q1 output becomes "H" level and Q2 output becomes "L" level. The output of the NAND gate 82 becomes "H" level by the reset signal, and the NAND gate 82 is input to the NAND gate 81 forming the flip-flop. The remaining inputs of the NAND gate 81 are all at "H" level because the transfer control units 21, 31, 51, 61 are reset, and the NAND gate 81
Output becomes "L" level, and NAND gates 81 and 8
The previous flip-flop composed of 2 becomes stable.

The output of the NAND gate 83 is at "H" level because the output of the flip-flop of the previous stage, which is composed of the NAND gates 83 and 84, receives the output of the flip-flop of the previous stage and the reset signal is input to the NAND gate 83. , The output of the NAND gate 80 becomes the “L” level, and the flip-flop in the subsequent stage is also stabilized. Since the output of the NAND gate 83 is given to the input of the NOR gate 89, the output of the NOR gate 89 becomes "L" level, and the data transmission to the data transmission path 100 is prohibited. Output of NAND gate 80 is NO
By being applied to the input of the R gate 90, the output of the NOR gate 90 becomes "H" level, and the data transmission line 1
Data transmission to 00.

The output of the NAND gate 73 becomes "L" level when the reset signal is input, the D type flip-flop 71 is set, its Q output becomes "H" level, and the output of the OR gate 79 also becomes "H". "H" level, and the output of the AND gate 75 becomes "H" level.

In this state, the data 1 is applied to the data holding circuit 12, and the pulse signal c10 is applied to the transfer control unit 1.
1 is given to the AND gate 75, since the Q2 output of the transfer control unit 21 is at the “H” level.
Output becomes "H" level, and its Q1 output becomes "L" level. The Q1 output of the transfer controller 11 is the transfer controller 2
1 becomes a clock pulse of the data holding circuit 12, and the content of the data 1 is the data holding circuit 12
Is output to Qi. The transfer control unit 21 is the transfer control unit 31.
Of the data holding circuit 22 becomes a clock pulse of the data holding circuit 22 while the Q1 output of the transfer control unit 21 is transmitted to the transfer control unit 31 because the Q2 output of the The content of Qi of the holding circuit 12 is output to Qi of the data holding circuit 22.

The Q1 output of the transfer control section 21 and the Q2 output of the transfer control section 31 are input to the NAND gate 81, and the output of the NAND gate 81 is changed from the "H" level to the "L" level. NAND gate 8
2 and 83 are input. The output of the NAND gate 82 becomes "H" because the input becomes "L" level.
It becomes the level and stabilizes the flip-flop of the previous stage.
Further, the output of the NAND gate 83 changes from the “H” level to the “L” level, and its output is the NAND gate 84.
Will be input. The input of the NAND gate 84 is "L"
When it becomes the level, its output becomes the “H” level and stabilizes the flip-flop in the subsequent stage.

The "L" level signal output from the NAND gate 83 becomes an input to the NOR gate 89, and the transmission enable signal from the transfer control unit 101 is activated, so that the Q1 output of the transfer control unit 31 becomes "L". To level,
It is transmitted to the transfer control unit 101. When the transmission permission signal AK is at "H" level, the Q1 output of the transfer control unit 101 becomes "L" level and becomes a clock pulse of the data holding circuit 102, and the content of Di of the data holding circuit 102 is output to Qi. It During the period when the transfer control unit 31 is outputting to the transfer control unit 101, the NAND gate 84
Since the "H" level signal of the output of is held as the output of the flip-flop of the subsequent stage and is input to the NOR gate 90, the output of the NOR gate 90 holds the "L" level,
By detecting the output from the transfer control unit 61 to the transfer control unit 101 and setting the Q output of the D-type flip-flop 88 to the “L” level by the output of the transfer control unit 31, the output Qi of the data holding circuit 62 is changed. Is set to high impedance so as not to collide with the Qi output of the data holding circuit 32.

Next, when the data 2 is applied to the data holding circuit 42 and the pulse signal c20 is applied to the transfer control section 41, the operation is the same as the above-mentioned operation associated with the input of the data 1 and is omitted. ..

Next, after the initial state, data 2 is data 1
The case in which the input is a little later than the case described below will be described.
The data 1 is supplied to the data holding circuit 12, the pulse signal c10 is supplied to the transfer control unit 11, and is also supplied to the clock input terminal of the D type flip-flop 71 and the D input terminal of the D type flip-flop 72. The data 2 input a little later than the data 1 is supplied to the data holding circuit 42 until the pulse signal c10 returns from the "L" level to the "H" level again. When the pulse signal c20 is given to the transfer control unit 41, the D input of the D-type flip-flop 72 is at "L" level, so when the pulse signal c10 returns from "L" level to "H" again, Q
The output becomes the “L” level, the output of the AND gate 76 also becomes the “L” level, and the pulse transmitted to the transfer control unit 41 is not sent to the transfer control unit 51 and is stopped by the transfer control unit 41.

The Q1 output of the transfer controller 11 is the transfer controller 2
When it is transmitted to 1, the output of the AND gate 74 becomes the “L” level, the Q output of the D type flip-flop 72 is set, the pulse stopped by the transfer control unit 41 is permitted to be transferred again, and the transfer control unit 51 Transferred to. The operation when the data 1 is input slightly later than the data 2 is the same, and therefore the description thereof is omitted.

When data 1 and data 2 are input at exactly the same time, the Q outputs of the D type flip-flops 71 and 72 both become "L" level, and AN
Since the output of the D gate 76 becomes the “L” level, the data transmitted to the transfer control unit 41 is prohibited, and the output of the NOR gate 77 becomes the “H” level, so that the OR gate 7
Since the output of 9 becomes "H" level and the output of the AND gate 75 also becomes "H" level, the data transmitted to the transfer control unit 11 is permitted. The subsequent operation is the same as when the two data inputs are deviated. If data 1 and data 2 are thus conflictingly input, NA
ND gates 81 and 82 flip-flops and N
The data input late is temporarily stopped by the flip-flops of the AND gates 83 and 84.

As described above, according to this embodiment, when only the data 1 exists and the data 2 does not exist in the state where the data transmission line 100 on the output side is open, the data 1 is sequentially output. Only 2 exists, data 1
If there is not, the data 2 is sequentially output. Also,
When the data 1 and the data 2 are transmitted with the maximum transfer capacity of the data transmission line, the data transmission line 100 cannot be processed, and therefore the data transmission lines 30, 20 and 10 and the data transmission lines 60, 50 and 40. Data is accumulated in the. In this case, the data transmission line 30 and the data transmission line 60 alternately transmit the data on each transmission line to the data transmission line 100.
To transmit.

[0026]

As described above, according to the present invention, even when data on a plurality of parallel transmission lines are transmitted at arbitrary time intervals and asynchronously with each other, transmission is permitted from the data transmission line on the output side. By performing arbitration by the arbitration control means in response to a signal being sent, data is received up to the limit of the physical accommodation capacity of the transmission line, and there is no delay time required for arbitration control, and the output side transmission line Can be sequentially transmitted. Therefore, it is possible to realize a highly reliable arbitration mechanism as well as high-speed transmission.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is a concrete block diagram of an embodiment of the present invention.

FIG. 3 is a specific block diagram of a transfer control unit 11 shown in FIG.

FIG. 4 is a specific block diagram of the transfer control unit 101 shown in FIG.

[Explanation of symbols]

 10-60,100 Data transmission path 11-61,101 Transfer control part 12-62,102 Data holding circuit 70 Contention detection part 80 Arbitration control part

Claims (1)

[Claims] 1. A data transmission device for serially transmitting a plurality of data transmitted via a plurality of parallel input side transmission lines to an output side transmission line, wherein the plurality of parallel transmissions are provided. Contention detecting means for detecting that there are two sets of data on arbitrary two sets of transmission paths in the path and the number of arrival times of the two sets of data is within a certain time difference, and the output side In response to the transmission permission signal sent from the transmission line, the transmission line having the contention detection function is arbitrated in the output order by the data congestion of each of the plurality of parallel input side transmission lines, and the output side is arbitrated. Characterized by comprising arbitration control means for transmitting to the transmission line of
Data transmission equipment.