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JPH05167016A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JPH05167016A
JPH05167016A JP33360091A JP33360091A JPH05167016A JP H05167016 A JPH05167016 A JP H05167016A JP 33360091 A JP33360091 A JP 33360091A JP 33360091 A JP33360091 A JP 33360091A JP H05167016 A JPH05167016 A JP H05167016A
Authority
JP
Japan
Prior art keywords
film
poly
polycrystalline silicon
grain size
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33360091A
Other languages
Japanese (ja)
Other versions
JP3153921B2 (en
Inventor
Yoichi Ejiri
洋一 江尻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP33360091A priority Critical patent/JP3153921B2/en
Publication of JPH05167016A publication Critical patent/JPH05167016A/en
Application granted granted Critical
Publication of JP3153921B2 publication Critical patent/JP3153921B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To equalize the grain size of polycrystal silicon by a method wherein an amorphous silicon film formed to be heat-treated is recrystalized to be turned into a polycrystal silicon. CONSTITUTION:Poly-Si is deposited on a LOCOS oxide film 1 to form a poly-Si film 2. Next, the whole surface is implanted with BF2<+> in concentration corresponding to specified resistivity. Successively, the whole surface is implanted with Si<+> by low temperature ion implanting method. Through these procedures, the poly-Si film 2 is made almost amorphous to form an -Si film 2a. Next, this film 2a is cut out in specific shape to form an alpha-Si film pattern 2b. Later, SiO2 is deposited to form an SiO2 film 5. Successively, the whole body is annealed to recrystallize and crystalize the alpha-Si film pattern 2b for turning into poly-Si 6. Through these recrystallizing method by annealing step, the grain size of poly-Si 6 can be almost equalized thereby enabling the fluctuation in the resistivity to be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置及びその製造
方法に係り、特にシリコン(Si)のグレーンサイズ
(粒径)を均一にして抵抗率の変動を低減させた多結晶
シリコン(ポリシリコン:Poly−Si)を用いた半
導体装置及びその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to polycrystalline silicon (polysilicon: poly: silicon) having a uniform grain size (grain size) of silicon (Si) to reduce fluctuations in resistivity. The present invention relates to a semiconductor device using Poly-Si) and a manufacturing method thereof.

【0002】[0002]

【従来の技術】ポリシリコンは、MOSデバイスにおい
てゲート電極としてよく用いられるが、その他抵抗体と
しても用いられる。このPoly−Si抵抗体はシリコ
ンを熱分解する減圧CVD法等によって絶縁膜上に選択
的に堆積形成することができるため、微細化可能、寄生
容量小、基板バイアス効果耐性大等の利点を有する。従
って、単結晶シリコン(Single Si)中への不純物の拡
散を利用して形成する拡散抵抗体と比較してPoly−
Si抵抗体は有利であり、広く利用されている。
Polysilicon is often used as a gate electrode in MOS devices, but is also used as a resistor. Since this Poly-Si resistor can be selectively deposited and formed on the insulating film by a low pressure CVD method that thermally decomposes silicon, it has advantages such as miniaturization, small parasitic capacitance, and large substrate bias effect resistance. . Therefore, compared with a diffusion resistor formed by utilizing the diffusion of impurities into single crystal silicon (Single Si),
Si resistors are advantageous and widely used.

【0003】しかし、一方Poly−Si抵抗体は、形
成されるPoly−Si膜の線幅、膜厚、導入される不
純物濃度、グレインサイズ(粒径)、グレインバンダリ
ー(粒界)等抵抗値を決定するパラメータが多く抵抗精
度の点では不利である。
On the other hand, a poly-Si resistor has a line width, a film thickness, an impurity concentration to be introduced, a grain size (grain size), a grain boundary (grain boundary) and the like resistance value of the formed poly-Si film. Since there are many parameters that determine, it is disadvantageous in terms of resistance accuracy.

【0004】上記抵抗値を決定するパラメータのうちグ
レインサイズは、製造プロセス工程中の熱処理によって
成長(粗大化)が進む。
Among the parameters that determine the resistance value, the grain size is grown (coarsened) by the heat treatment during the manufacturing process.

【0005】Poly−Siのグレイン成長は、成長前
の結晶性に左右されるが、その結晶性をコントロールす
ることは困難であり、抵抗値のバラツキを招く。
The grain growth of Poly-Si depends on the crystallinity before the growth, but it is difficult to control the crystallinity and the resistance value varies.

【0006】[0006]

【発明が解決しようとする課題】グレインサイズの均一
化は、アモルファス(非晶質)シリコンを再結晶するこ
とによって可能である。
The grain size can be made uniform by recrystallizing amorphous silicon.

【0007】従来、ポリシリコン等のSi層中にある種
のイオンをイオン注入(II)することによって一部を
アモルファス層に変える技術は知られている。しかしな
がらこのようにして形成されたアモルファス層は多くの
結晶欠陥を含む構造を有するものであって、完全なアモ
ルファス層とは言えない。従って、従来は抵抗率の精度
の向上は、グレインサイズのコントロールという面から
はなかなか困難であった。
Conventionally, there is known a technique of partially implanting an ion into a Si layer such as polysilicon by implanting (II) certain ions into an amorphous layer. However, the amorphous layer thus formed has a structure containing many crystal defects and cannot be said to be a completely amorphous layer. Therefore, conventionally, it has been difficult to improve the accuracy of the resistivity from the viewpoint of controlling the grain size.

【0008】そこで本発明は、Poly−Siのグレイ
ンサイズのコントロールという面から抵抗率の変動を低
減したPoly−Si抵抗体を有する半導体装置及びそ
の製造方法を提供することを目的とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device having a Poly-Si resistor in which the fluctuation of the resistivity is reduced from the viewpoint of controlling the grain size of Poly-Si, and a manufacturing method thereof.

【0009】[0009]

【課題を解決するための手段】上記課題は本発明によれ
ば、多結晶シリコンからなる抵抗体を有する半導体装置
において、前記多結晶シリコンのグレインサイズの均一
化を図り、抵抗率の変動を低減せしめたことを特徴とす
る半導体装置によって解決される。
According to the present invention, in the semiconductor device having a resistor made of polycrystalline silicon, the grain size of the polycrystalline silicon is made uniform to reduce the variation in resistivity. The problem is solved by a semiconductor device characterized by being hampered.

【0010】更に、上記課題は本発明によれば、多結晶
シリコンからなる抵抗体を有する半導体装置の製造方法
において、絶縁基板上に多結晶シリコン膜を形成する工
程と、前記多結晶シリコン膜内に不純物イオンを所定量
注入する工程と、次に−50℃以下の低温度でシリコン
をイオン注入して前記多結晶シリコン膜をアモルファス
シリコン膜に変える工程と、前記アモルファスシリコン
膜を所定形状にパターニング形成した後、全面に層間絶
縁膜を形成する工程と、熱処理することによって前記ア
モルファスシリコン膜を再結晶化して多結晶シリコンに
変える工程、を含むことを特徴とする半導体装置の製造
方法によって解決される。
Further, according to the present invention, in the method for manufacturing a semiconductor device having a resistor made of polycrystalline silicon, a step of forming a polycrystalline silicon film on an insulating substrate; A step of implanting a predetermined amount of impurity ions into the substrate, a step of implanting silicon at a low temperature of −50 ° C. or lower to change the polycrystalline silicon film into an amorphous silicon film, and patterning the amorphous silicon film into a predetermined shape. A method for manufacturing a semiconductor device is characterized by including a step of forming an interlayer insulating film on the entire surface after formation, and a step of recrystallizing the amorphous silicon film by heat treatment to convert it into polycrystalline silicon. It

【0011】[0011]

【作用】本発明によれば、抵抗体を構成するポリシリコ
ン(Poly−Si)を一旦、−50以下の低温(アモ
ルファス化及び実作業性の点から−200℃程度が最も
好ましい)でSiイオン(Si+)を注入しているた
め、Poly−Siがほぼアモルファス(非晶質)シリ
コン(a−Si)に変化する。−50℃以上の高温で
は、ボイドの発生や多結晶シリコンが完全にアモルファ
ス化されない等の不具合を生ずる。
According to the present invention, the polysilicon (Poly-Si) which constitutes the resistor is once exposed to Si ions at a low temperature of -50 or less (about 200 ° C. is most preferable from the viewpoint of amorphization and practical workability). Since (Si + ) is injected, Poly-Si changes into almost amorphous silicon (a-Si). At a high temperature of −50 ° C. or higher, defects such as generation of voids and polycrystalline silicon not being completely amorphized occur.

【0012】従って、この後、再結晶するための熱処理
を行うとアモルファス状態からの各々の結晶成長速度が
ほぼ一定となるため、熱処理後得られるPoly−Si
のグレインサイズはほぼ均一なものが得られる。このよ
うにほぼ均一なグレインサイズのPoly−Siを得る
ことができるため、抵抗率の変動要因の一つをコントロ
ールすることができる。
Therefore, if a heat treatment for recrystallization is performed thereafter, each crystal growth rate from the amorphous state becomes almost constant, so that Poly-Si obtained after the heat treatment is obtained.
The grain size of is almost uniform. As described above, since Poly-Si having a substantially uniform grain size can be obtained, one of the factors that cause the change in resistivity can be controlled.

【0013】[0013]

【実施例】以下、本発明の実施例を図面に基づいて詳細
に説明する。
Embodiments of the present invention will now be described in detail with reference to the drawings.

【0014】図1は本発明に係る多結晶シリコン(Po
ly−Si)抵抗体の一実施例を示す断面図である。
FIG. 1 shows polycrystalline silicon (Po) according to the present invention.
FIG. 4 is a cross-sectional view showing an example of a ly-Si) resistor.

【0015】図1に示すように、本実施例の抵抗体が、
SiO2からなるLOCOS酸化膜1上にPoly−S
i6によって構成されている。Poly−Si6の配線
方向端部には、層間絶縁膜としてのSiO2膜5を介し
て電極10a,10b(コンタクトホール7a,7b)
が形成されている。
As shown in FIG. 1, the resistor of the present embodiment is
Poly-S is formed on the LOCOS oxide film 1 made of SiO 2.
i6. Electrodes 10a and 10b (contact holes 7a and 7b) are formed at the ends of the Poly-Si 6 in the wiring direction via a SiO 2 film 5 as an interlayer insulating film.
Are formed.

【0016】抵抗体としてのPoly−Si6は後に詳
述するが、厚さが150nmであり、所定の抵抗値を得
るためにBF2 +がイオン注入されている。
Poly-Si6 as a resistor will be described in detail later, but has a thickness of 150 nm, and BF 2 + is ion-implanted to obtain a predetermined resistance value.

【0017】また、本実施例の抵抗体は図示していない
が、MOS Tr等に好ましく構成される。
Although not shown, the resistor according to the present embodiment is preferably formed in a MOS Tr or the like.

【0018】図2は、図1に示した一実施例の前半工程
断面図である。
FIG. 2 is a sectional view of the first half step of the embodiment shown in FIG.

【0019】図2(a)に示すように、通常プロセスフ
ローに沿ってLOCOS酸化膜1上に、CVD(化学的
気相成長)法により150nmの厚さにポリシリコン
(Poly−Si)を堆積してPoly−Si膜2を形
成する。Poly−Si2膜はPoly−Si抵抗体形
成用の膜である。
As shown in FIG. 2A, polysilicon (Poly-Si) is deposited to a thickness of 150 nm on the LOCOS oxide film 1 by the CVD (Chemical Vapor Deposition) method along the normal process flow. Then, the Poly-Si film 2 is formed. The Poly-Si2 film is a film for forming a Poly-Si resistor.

【0020】Poly−Si膜2を形成した後、図2
(b)に示すように、通常のイオン注入(II)技術に
よりフッ化ボロンイオン(BF2 +)を所望の抵抗率に対
応した濃度分、例えばドーズ(dose)量、1×1014
5×1016/cm2注入エネルギー30KeVで全面に
注入する。この際、図示はしないが電極取り出し部に
は、レジストマスクを用いて高濃度に注入する。
After forming the Poly-Si film 2, as shown in FIG.
As shown in (b), boron fluoride ion (BF 2 + ) is added by a normal ion implantation (II) technique in a concentration corresponding to a desired resistivity, for example, a dose amount of 1 × 10 14 to
Implantation is performed on the entire surface with an implantation energy of 5 × 10 16 / cm 2 of 30 KeV. At this time, although not shown, a high concentration is injected into the electrode extraction portion using a resist mask.

【0021】次に図2(c)に示すように、低温イオン
注入法を用いて−200℃の低温条件下でシリコンイオ
ン(Si+)を、ドース量5×1014/cm2、注入エネ
ルギー70KeVで全面に、注入する。この低温度イオ
ン注入によってPoly−Si膜2は、ほぼアモルファ
ス化し、アモルファスシリコン(a−Si)膜2aが形
成される。
Next, as shown in FIG. 2 (c), silicon ions (Si + ) were added at a dose of 5 × 10 14 / cm 2 and an implantation energy under the low temperature condition of −200 ° C. by using the low temperature ion implantation method. Implant all over at 70 KeV. By this low-temperature ion implantation, the Poly-Si film 2 becomes almost amorphous and an amorphous silicon (a-Si) film 2a is formed.

【0022】次に、フォトリソ技術及びRIEエッチン
グによってa−Si膜2aを所定形状パターンにカット
して、図3(a)に示すように、a−Si膜パターン2
bを形成する。その後、層間絶縁膜として全面に二酸化
シリコン(SiO2)をCVD法により300〜400
nmの厚さに堆積して、SiO2膜5を形成し、次に通
常のプロセスフローにより図示はしないが、他の素子
(例えばMOSトランジスタ)を形成する。その後、6
00℃程度の温度でアニール(Furnace Anneal,ランプ
Anneal あるいは レーザー Anneal等)処理を施してa
−Si膜パターン2bの再結晶化及び結晶成長を起こさ
せ、図3(b)に示すようにPoly−Si6に変化さ
せる。この結晶成長は、注入不純物イオン(ドーパン
ト)のBF2 +中のフッ素(F)の影響により留まる。こ
のアニール処理による再結晶化では、Poly−Siグ
レインサイズは、ほぼ均一の大きさになった。これは、
Poly−Siが低温IIによってアモルファス(非晶
質)化された結果、結晶化に全く差がない状態から結晶
成長を起こさせることができるからである。
Next, the a-Si film 2a is cut into a predetermined pattern by photolithography and RIE etching, and as shown in FIG. 3A, the a-Si film pattern 2 is formed.
b is formed. After that, silicon dioxide (SiO 2 ) is deposited on the entire surface as an interlayer insulating film by the CVD method in the range of 300 to 400.
The SiO 2 film 5 is deposited to a thickness of nm, and then another element (for example, a MOS transistor) is formed by a normal process flow although not shown. Then 6
Anneal at a temperature of about 00 ℃ (Furnace Anneal, lamp
Anneal or laser anneal, etc.)
Re-crystallization and crystal growth of the -Si film pattern 2b are caused to change to Poly-Si6 as shown in FIG. 3 (b). This crystal growth remains due to the influence of fluorine (F) in BF 2 + of the implanted impurity ions (dopant). In the recrystallization by this annealing treatment, the Poly-Si grain size became almost uniform. this is,
This is because, as a result of Poly-Si being made amorphous by the low temperature II, it is possible to cause crystal growth from a state in which there is no difference in crystallization.

【0023】次に図3(c)に示すように、絶縁膜のS
iO2膜5の2箇所にコンタクトホール7a、7bを形
成した後、全面にスパッタ蒸着法によりTi/TiN/
Al−SiあるいはPoly−Si/WSix(タング
ステンシリサイド)等の各々多層構造メタル10を形成
し、リングラフィ技術により該メタルをパターニングし
て図1に示したように、電極10a、10bを形成す
る。
Next, as shown in FIG. 3C, S of the insulating film is
After forming the contact holes 7a and 7b at two places of the iO 2 film 5, Ti / TiN /
A multi-layer structure metal 10 such as Al-Si or Poly-Si / WSix (tungsten silicide) is formed, and the metal is patterned by a linography technique to form electrodes 10a and 10b as shown in FIG.

【0024】このようにして、グレインサイズがほぼ均
一で、バラツキが小さく高精度のPoly−Si抵抗体
を有するMOSトランジスタを完成させた。
In this way, a MOS transistor having a highly accurate Poly-Si resistor having a substantially uniform grain size and a small variation was completed.

【0025】一方、電極取り出し部のPoly−Siに
ついても低温IIそしてアニールの如き同様の方法を用
いて高精度で高性能なPoly−Siデバイスが実現さ
れる。
On the other hand, also for Poly-Si at the electrode take-out portion, a highly accurate and high-performance Poly-Si device can be realized by using a similar method such as low temperature II and annealing.

【0026】[0026]

【発明の効果】以上説明したように、本発明によればグ
レインサイズがほぼ均一で抵抗率のバラツキが少ない多
結晶シリコン(Poly−Si)抵抗体を有するBi
polar型、MOS型及びBiCMOS型 LSI等
の半導体装置を得ることができる。
As described above, according to the present invention, Bi having a polycrystalline silicon (Poly-Si) resistor having a substantially uniform grain size and a small variation in resistivity.
Semiconductor devices such as polar type, MOS type and BiCMOS type LSI can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るPoly−Si抵抗体の一実施例
を示す断面図である。
FIG. 1 is a sectional view showing an example of a Poly-Si resistor according to the present invention.

【図2】図1に示した一実施例の前半工程断面図であ
る。
FIG. 2 is a first half process sectional view of the embodiment shown in FIG.

【図3】図1に示した一実施例の後半工程断面図であ
る。
FIG. 3 is a sectional view of a second half process of the embodiment shown in FIG.

【符号の説明】[Explanation of symbols]

1 LOCOS酸化膜(SiO2) 2 Poly−Si膜 2a アモルファスシリコン(a−Si)膜 2b a−Si膜パターン 5 SiO2膜 6 Poly−Si 7a,7b コンタクトホール 10 多層構造メタル 10a,10b 電極1 LOCOS oxide film (SiO 2) 2 Poly-Si film 2a amorphous silicon (a-Si) film 2b a-Si film pattern 5 SiO 2 film 6 Poly-Si 7a, 7b contact hole 10 multilayer metal 10a, 10b electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 多結晶シリコンからなる抵抗体を有する
半導体装置において、 前記多結晶シリコンのグレインサイズの均一化を図り、
抵抗率の変動を低減せしめたことを特徴とする半導体装
置。
1. A semiconductor device having a resistor made of polycrystalline silicon, wherein the grain size of the polycrystalline silicon is made uniform,
A semiconductor device characterized by reducing fluctuations in resistivity.
【請求項2】 多結晶シリコンからなる抵抗体を有する
半導体装置の製造方法において、 絶縁基板上に多結晶シリコン膜を形成する工程と、 前記多結晶シリコン膜内に不純物イオンを所定量注入す
る工程と、 次に−50℃以下の低温度でシリコンをイオン注入して
前記多結晶シリコン膜をアモルファスシリコン膜に変え
る工程と、 前記アモルファスシリコン膜を所定形状にパターニング
形成した後、全面に層間絶縁膜を形成する工程と、 熱処理することによって前記アモルファスシリコン膜を
再結晶化して多結晶シリコンに変える工程、 を含むことを特徴とする半導体装置の製造方法。
2. A method of manufacturing a semiconductor device having a resistor made of polycrystalline silicon, the step of forming a polycrystalline silicon film on an insulating substrate, and the step of implanting a predetermined amount of impurity ions into the polycrystalline silicon film. Next, a step of ion-implanting silicon at a low temperature of −50 ° C. or lower to change the polycrystalline silicon film into an amorphous silicon film, and after patterning the amorphous silicon film into a predetermined shape, an interlayer insulating film is formed on the entire surface. And a step of heat-treating to recrystallize the amorphous silicon film to convert it into polycrystalline silicon.
JP33360091A 1991-12-17 1991-12-17 Method for manufacturing semiconductor device Expired - Lifetime JP3153921B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33360091A JP3153921B2 (en) 1991-12-17 1991-12-17 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33360091A JP3153921B2 (en) 1991-12-17 1991-12-17 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH05167016A true JPH05167016A (en) 1993-07-02
JP3153921B2 JP3153921B2 (en) 2001-04-09

Family

ID=18267860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33360091A Expired - Lifetime JP3153921B2 (en) 1991-12-17 1991-12-17 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3153921B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004319613A (en) * 2003-04-14 2004-11-11 Semiconductor Energy Lab Co Ltd D / A conversion circuit, semiconductor device incorporating the same, and manufacturing method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004363234A (en) 2003-06-03 2004-12-24 Renesas Technology Corp Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004319613A (en) * 2003-04-14 2004-11-11 Semiconductor Energy Lab Co Ltd D / A conversion circuit, semiconductor device incorporating the same, and manufacturing method thereof
JP4511803B2 (en) * 2003-04-14 2010-07-28 株式会社半導体エネルギー研究所 D / A conversion circuit and method of manufacturing semiconductor device incorporating the same

Also Published As

Publication number Publication date
JP3153921B2 (en) 2001-04-09

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