JPH0516183B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device provided with a redundant function, and particularly relates to an improvement that enables efficient wiring switching when using the redundant function. [Technical Background of the Invention and its Problems] FIG. 1 is a circuit diagram of a conventional semiconductor device having a redundant function. In the figure, 1 to 3 are the original functional circuit blocks, and 4 is a redundant circuit that is used in place of the original functional circuit blocks 1 to 3 when one of them cannot be used due to a failure or other reason. This is a functional circuit block for The above-mentioned original functional circuit blocks 1 to 3 are connected to other functional circuit blocks (not shown) via fuse elements 5 to 7 exclusively for cutoff, and the above-mentioned redundant functional circuit block 4 is connected via a fuse element 8 exclusively for connection. Combined with other functional circuit blocks. As shown in the cross-sectional view of FIG. 2, each of the fuse elements 5 to 7 dedicated to shutoff has a uniform silicon oxide film 12 formed on the surface of a silicon semiconductor substrate 11 by a thermal oxidation method. Further, a polysilicon (polycrystalline silicon) layer 13 is formed on this layer by CVD method, and N-type impurities such as phosphorus or arsenic or P-type impurities such as boron are introduced into this layer to lower the resistance. It is formed by removing polysilicon layer 13 in areas other than desired locations using an etching technique. Furthermore, the fuse element 8 dedicated to the above connection is, for example, ``1981 IEEE
International Solid-State Circuits
Conference P.14~15 “HI-CMOS 4K
Static RAM "O.Minato el.Hitachi", the detailed structure of which is shown in FIG. 22 is formed, and then a polysilicon layer is formed on this by CVD method, and N-type impurities such as phosphorus or arsenic or P-type impurities such as boron are introduced into areas other than the desired areas to lower the resistance. polysilicon layer 2
3 and 24, and a polysilicon layer 25 which is not doped with impurities and maintained in a high resistance state is formed between both polysilicon layers 23 and 24. Therefore, in the initial state after manufacturing the device, the fuse elements 5 to 7 dedicated to shutoff shown in FIG.
are electrically connected, and the original functional circuit blocks 1 to 3 are connected to other functional circuit blocks via these fuse elements 5 to 7. Further, in the initial state, the fuse element 8 for connection only shown in FIG. 3 is electrically cut off, and the redundant functional circuit block 4 is not connected to other functional circuit blocks. Next, in such a situation, if any one of the original functional circuit blocks 1 to 3 cannot be used due to a failure or the like and redundant functional circuit block 4 is to be used instead, first An energy beam such as a laser beam is irradiated onto the surface of a fuse element dedicated to cutoff, which is connected to an original functional circuit block that cannot be used, to heat it and melt the polysilicon layer 13. In addition, the surface of the fuse element 8 dedicated for connection is also irradiated with energy beams,
Impurities in the polysilicon layers 23 and 24 are removed from the polysilicon layers 23 and 24 without blowing out the polysilicon layers 23 to 25 by applying energy weaker than the energy applied to the above-mentioned cut-off fuse element.
5 and changes the polysilicon layer 25 from a high resistance state to a low resistance state. Through such operations, the faulty one among the original functional circuit blocks 1 to 3 is separated from the other functional circuit blocks, and redundant functional circuit block 4 is newly connected in its place. As a result, the wiring switching is completed, and the functional circuit block that is defective, ie, has a failure, etc., is effectively put into a dormant state, and the redundant functional circuit block 4 starts operating in its stead. In a conventional semiconductor device with such a configuration,
When using the redundant functional circuit block 4, it is necessary to heat two locations: one of the fuse elements 5 to 7 dedicated to cutoff and the fuse element 8 dedicated to connection. Moreover, since the energy used for heating is different, for example, a fuse element 5 dedicated to shutoff
Even if the fuse element 8 dedicated for connection to the fuse element 8 is arranged close to the fuse element 8, it is not possible to irradiate the energy beam and heat the fuse element 8 at the same time. Therefore, the conventional method has a drawback in that wiring cannot be switched efficiently. Next, the drawbacks of this conventional device will be explained using a specific device. FIG. 4 shows one memory cell 35 , which is composed of two CMOS inverters 31, 32 and a pair of MOS transistors 33, 34 for data transmission, and stores one bit of data, along with its peripheral parts. , 37 are MOS transistors for chip selection, 38 are chip selection lines, 3
9, 40 are MOS transistors for column selection, 41
is a column selection line, and 42 is a row selection line. In such a configuration, the memory cell 35 is accessed by selecting both the column selection line 41 and the row selection line 42. FIG. 5 shows a circuit system as shown in FIG. 1 used in a decoder for selecting each column selection line or each row selection line of a memory in which a large number of memory cells having the configuration shown in FIG. 4 are provided. It is designed to add redundant functions. In Figure 5, 5
1, 52, and 53 are column selection lines 4 in FIG. 4, respectively.
1 or row selection lines 42, and the original memory cells are connected to the ends of these selection lines. Also, 54 is the column selection line 41 or the row selection line 4.
2, and a redundant memory cell to be replaced when the original memory cell is defective is connected to the end of this selection line. Above selection line 5
The decoding parts for driving MOS transistors 1, 52, and 53 each have the same circuit configuration, including a precharge MOS transistor 56 to which a signal from a precharge control line 55 is applied, and a column address MOS transistor 56 connected in series to this MOS transistor 56. A plurality of MOS transistors 58 for decoding are selectively supplied with the signals of address signal lines 57 to which signals and their inverted signals or row address signals and their inverted signals are transmitted, and a discharge transistor further connected in series with these MOS transistors 58. A discharge MOS transistor 60 to which the signal of the control line 59 is applied, one end of which is connected to the series connection point A of the precharge MOS transistor 56 and one decoding MOS transistor 58, is shown in FIG. A fuse element 61 dedicated to interrupting the configuration as shown, an inverter 62 connected between the other end of this fuse element 61 and the selection line 51 or 52 or 53, and a pull-up element connected to the output end of this inverter 62. It is composed of a resistor 63. Further, the decoding section for driving the selection line 54 connected to the redundant memory cell is supplied with the signal of the precharge control line 55 via the fuse element 64 dedicated for connection, which has the configuration shown in FIG. MOS transistor 65 for pre-charge, this
A gate pull-down resistor 66 of the MOS transistor 65 is connected in series with the MOS transistor 65, and the signal on the address signal line 57 is connected to the third
A plurality of decoding devices selectively provided through each fuse element 67 dedicated to connection in the configuration shown in the figure.
MOS transistors 68, a MOS transistor 69 for discharging which is further connected in series with these MOS transistors 68 and supplied with the signal of the discharge control line 59, and a MOS transistor 69 for pre-charging and one MOS transistor 68 for decoding connected in series. Inverter 7 connected between connection line point B and the connection line 54
Consists of 0. In the initial state of such a decoder, all fuse elements 61 are set to a connected state, and all other fuse elements 64 and 67 are set to a cut-off state. In this state, when the precharge control line 55 is at the "L" level, the precharge MOS transistors 56 are turned on, each point A is precharged to the "H" level, and the selection lines 51, 52, 5
Since the signal No. 3 is at the "L" level, the column selection line 41 or row selection line 42 shown in FIG. 4 is not accessed. However, due to the address line 57, all MOS transistors 5 in a specific decoding section are
8 is turned on, and when the discharge control line 59 is at the "H" level and the discharge MOS transistor 60 is turned on, the point A of this decode section is discharged to the "L" level. One of them is “H”
The column selection line 41 or row selection line 42 shown in FIG. 4 is accessed as a level. In such a state, the selection lines 51, 52,
When any of the memory cells to which 53 is connected becomes defective due to a failure or the like, it is necessary to use a redundant memory cell. In this case, first, one of the fuse elements 67 is electrically connected and a specific combination of address signals is set.
so that it is supplied to the MOS transistor 68,
Further, the fuse element 61 connected to the defective memory cell via the inverter 62 is electrically cut off, and the fuse element 64 is electrically connected. As a result, the selection line 51 of the decoder portion where the fuse element 61 is electrically cut off
Alternatively, 52 or 53 is always at the "L" level, and this selection line is not accessed. On the other hand,
Since the MOS transistor 65 is connected to the precharge control line 55 via the fuse element 64, after precharging at point B, the selection line 54 goes to the “H” level or “L” level depending on the combination of address signals on the address signal line 57. ” level, and when it is at the “H” level, a redundant memory cell is selected. At this time, since the gate of the MOS transistor 65 is always pre-downed by the resistor 66, its threshold voltage or It is necessary to set the resistances of resistor 66 and fuse element 64. That is, the resistance value of the resistor 66 is R ₁ ,
Assuming that the resistance value of the fuse element 64 is R ₂ and the "H" level voltage on the precharge control line 55 is V ₁ , the MOS transistor 65 is turned off by the voltage of R ₁ /R ₁ +R ₂ V ₁ . The threshold voltage of the MOS transistor 65 or the resistance value of the resistor 66 and the resistance value of the fuse element 64 may be determined. As described above, in such a decoder, when using redundant memory cells, at least the selection lines 51, 52, 5 connected to the defective memory cell are
Any one of the fuse elements 61 on the signal system of No. 3
The two fuses, one and the fuse element 64, must be heated separately, which has the disadvantage that wiring cannot be switched efficiently. [Object of the Invention] The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to provide a semiconductor device that can efficiently switch wiring when using a redundant function. . [Summary of the Invention] According to an embodiment of the present invention, a pair of P ⁺ type regions are formed at a predetermined interval in the surface region of an N type semiconductor substrate, and an N ⁺ type region is formed between the pair of P ⁺ regions. This first wiring means is provided at a plurality of locations, and the P ⁺ type regions of each one of these first wiring means are formed to extend and connect to each other. The other P ⁺ type regions are extended and connected to each other, and second wiring means made of polysilicon is formed in the vicinity of each of the first wiring means via an insulating film, and irradiated with an energy beam. When any one of the first wiring means is set to a cut-off state due to heating by
A semiconductor device is provided in which wiring means are connected. [Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. FIG. 6 is a configuration diagram of a semiconductor device according to the present invention. In FIG. 6, reference numerals 81, 82, and 83 are original functional circuit blocks, and 84 is a substitute for the original functional circuit blocks 81 to 83 when any of them cannot be used due to a failure or the like. This is a redundant functional circuit block used for Further, in the figure, 85 is a P ⁺ type region formed continuously on the surface region of the N type semiconductor substrate,
Similarly, 86 is another P ⁺ type region formed separately from this P ⁺ type region 85. The pair of P ⁺ type regions 85, 86 are formed so as to be close to each other at three predetermined locations, and the pair of P ⁺ type regions 85, 86 are set to maintain a constant interval at each of these locations. and the pair of P ⁺ type regions 85,
The surface area of the substrate at each approach point of 86 has an impurity concentration higher than that of the substrate.
N ⁺ type regions 87, 88, and 89 are formed, respectively. A pair of P ⁺ type regions 85, 86 at each approach point and this pair of P ⁺ type regions 85, 8
Each of the N ⁺ type regions 87, 88, and 89 sandwiched by N.sup.6 constitutes wiring means 90 , 91 , and 92 . In the initial state, each of these wiring means 90 , 91 , 92 has an N ⁺ type region 87 or 88 or 8 having a different conductivity type between the pair of P ⁺ type regions 85, 86.
9 exists, a pair of P ⁺ type regions 85,
86 is electrically cut off. On the other hand, at a location where the pair of P ⁺ type regions 85 and 86 are close to each other, a conductive layer 93 made of polysilicon extends in a direction intersecting a line connecting P ⁺ type regions 85 and 86 via an insulating film. , 94 and 95 are formed. These conductive layers 93, 94,
Since impurities are introduced into the conductive layer 95 to lower its resistance, both ends of the conductive layers 93, 94, and 95 are electrically connected in the initial state. And the one original functional circuit block 81
is connected to the above 1 through the wiring 96 made of aluminum.
The conductive layer 93 is connected to one end of the conductive layer 93.
The other end of 3 is connected to another functional circuit block (not shown) via another wiring 97 made of aluminum. The other original functional circuit block 82 is connected to one end of the one conductive layer 94 through a wiring 98 made of aluminum, and the other end of this conductive layer 94 is connected to another not shown circuit block 82 through a wiring 99 made of aluminum. coupled to functional circuit blocks. Similarly, the remaining original functional circuit block 83 is connected to one end of the conductive layer 95 through a wiring 100 made of aluminum.
The other end is connected to another functional circuit block (not shown) via a wiring 101 made of aluminum. The redundant functional circuit block 84 is connected to one of the two via wiring 102 made of aluminum.
It is connected to the P ⁺ type region 85, and the other P ⁺ type region 86 is connected to another functional circuit block (not shown) via a wiring 103 made of aluminum. FIG. 7 shows the one wiring means 90 and the conductive layer 93.
A cross-sectional view taken along the line A-A' at a point where the two intersect with each other is shown. In the figure, reference numeral 104 denotes an N-type semiconductor substrate, and the pair of P ⁺ type regions 85 and 86 are formed at a predetermined interval on the surface region of this substrate 104 by a diffusion method or ^the like. An N ⁺ type region 87 is formed between regions 85 and 86. Also, near this N ⁺ type region 87, crystal lattice defects are present in order to increase the diffusion coefficient of impurities when diffusing P type impurities from P ⁺ type regions 85 and 86 to N ⁺ type region 89, as will be described later. Hydrogen ions are implanted to increase the Further, the conductive layer 93 is formed on the surface of the substrate 104 with an insulating film 105 interposed therebetween. Further, in FIG. 7, 106 is a field insulating film, and 107 is a protective insulating film. In a semiconductor device having such a configuration, in an initial state after manufacturing, the wiring means 90 , 91 , 92
The pair of P ⁺ type regions 85 and 86 are electrically disconnected. Incidentally, each of the wiring means 90 , 91 , and 92 has a MOS transistor structure, as exemplified by one wiring means 90 shown in FIG. 94,9
When a voltage higher than a certain value is applied to 5, a pair of P ⁺
An inversion layer may be formed on the surface of the substrate 104 between the type regions 85 and 86, and the pair of P ⁺ type regions 85 and 86 may become electrically connected. However, since N ⁺ type regions 87, 88, and 89 are formed between P ⁺ type regions 85 and 86, and the threshold voltage in these parts is set high, the conductive layers 93, 94, and 95 are normally The applied voltage is such that the above-mentioned inversion layer does not occur. On the other hand, in the initial state, the conductive layers 93, 94, 95
is a continuous state with no breaks. Therefore, in this initial state, the original functional circuit block 81 is connected to other functional circuit blocks through the wiring 96, the conductive layer 93, and the wiring 97 in series, and the wiring 98, the conductive layer 94, and the wiring 97 are connected in series.
9 in series, the original functional circuit block 82 is connected to other functional circuit blocks, and similarly the wiring 1
The original functional circuit block 83 is connected to other functional circuit blocks through the conductive layer 95 and wiring 101 in series, and at this time, the redundant functional circuit block 84 is not connected to any functional circuit block and is separated. state. Next, in such a state, one original functional circuit block 81 cannot be used due to a failure or the like, and the redundant functional circuit block 81 is replaced.
4, the area surrounded by the wiring in FIG. 6, that is, the area where the wiring means 90 and the conductive layer 93 intersect, is heated. This heating is performed by, for example, irradiating the second harmonic light of an Nd:YAG laser in a pulsed manner for several nanoseconds to several microseconds with a wavelength of about 5320 Å and an energy density of about 8 μjoule. By irradiating the laser beam, part of the conductive layer 93 and the insulating film 107 located thereon is dissolved. Furthermore, since the thermal energy during this laser beam irradiation is extremely large, P type impurities are diffused from the pair of P ⁺ type regions 85 and 86 in the wiring means 90 to the N ^{+ type region 87, and both regions 85 and 86 are diffused into the N +} type region 87. merge into one in this part. FIG. 8 is a sectional view showing the state after laser beam irradiation, and corresponds to FIG. 7 described above. In addition, P ⁺ type region 85,
86 can be easily fused since there are many crystal lattice defects near the N ⁺ type region 87. In the state after laser beam irradiation, the pair of P ⁺ type regions 85 and 86 of the wiring means 90 are electrically connected, and the conductive layer 93 is cut and electrically disconnected, so that the wiring cannot be switched. In this case, the faulty original functional circuit block 8
1 is separated, and a redundant functional circuit block 84 is connected to other functional circuit blocks via wiring means 90. When switching the wiring in this way, conventionally it was necessary to irradiate the laser beam with different energies at least twice, but in the above embodiment, it can be done with one irradiation. It can be done efficiently. Furthermore, even when other original functional circuit blocks 82 and 83 different from those described above cannot be used, the original functional circuit blocks 82 and 83 that cannot be used can be irradiated with a laser beam in the same manner as described above.
Instead of 83, a redundant functional circuit block 84 can be connected to another functional circuit block.
This means that the original functional circuit blocks 81 to 83
If any one of the wires connecting the redundant functional circuit block 84 and other functional circuit blocks is cut, the wires between the redundant functional circuit block 84 and the other functional circuit blocks are connected. The connection result of one wire in response to the wire cutoff operation changes as if it were an OR logic result, making it extremely easy to switch the wire from a defective circuit block to a normal circuit block. FIG. 9 shows a circuit configuration diagram of an application example of the present invention, and similarly to FIG. 5, the present invention is applied to a decoder. 5 in Figure 9
The difference from the figure is that the semiconductor device shown in FIG. 6 is used instead of the three fuse elements 61 and one fuse element 64. That is, the wirings 97, 99, 101 are
It is connected to each point A which is a series connection point of the MOS transistor 56 and one MOS transistor 58, the wiring 96, 98, 100 is connected to the input end of each inverter 62, the wiring 103 is connected to the precharge control line 55, Wiring 102 is connected to the gate of MOS transistor 65. In a decoder having such a configuration, the selection line 5
If the memory cell connected to the memory cell 1 is defective, the portion where the wiring means 90 and the conductive layer 93 intersect (FIG. 6) may be heated. Due to this heating, the conductive layer 93 is fused and the wirings 96 and 97 are cut off, so that the output of the selection line 51 is always at "L" level, and the memory cells connected to this selection line 51 are not accessed. Also, due to this heating, a pair of P ⁺ type regions 85 and 86 are formed in the wiring means 90.
The pair of P ⁺ type regions 85, 86 and the wirings 102, 10 are fused and electrically connected.
3, the precharge control line 55 is connected to the gate of the MOS transistor 65, so after precharging at point B, the selection line 54 is connected to the address signal line 5.
It is set to “H” level or “L” level depending on the combination of address signals in 7.
When the signal at point B is at the "L" level, the selection line 54 goes to the "H" level and the redundant memory cell is selected. On the other hand, when the memory cells connected to the other selection lines 52 and 53 are defective, the wiring means 91 and 9
2 and conductive layers 94 and 95 (sixth
(Fig.) can be heated. Also in this case, when cutting the conductive layers 94 and 95, a pair of
Since the P ⁺ type regions 85 and 86 are fused and electrically connected, the redundant memory cell connected to the selection line 54 is selected. Also in this case, there is a change in which the wirings 102 and 103 are connected by cutting any one of the wirings 96 and 97, 98 and 99, and 100 and 101, that is, the connection between the wirings 102 and 103. The connection result of one wire in response to a cutoff operation changes as if it were an OR logic result. In addition, in the decoder of FIG. 9, one of the two fuse elements 67 dedicated to connection must be in a connected state, and when using redundant memory cells, One of them is set to a connected state and the other one is set to a disconnected state.
For this reason, a circuit element having a structure as shown in FIG. 10 may be used instead of the pair of fuse elements 67 dedicated for connection. That is, the element shown in FIG.
For example, a pair of P ⁺ type regions 112 and 113 are formed at a predetermined distance on the surface area of an N type semiconductor substrate 111.
A conductive layer 114 made of polysilicon is formed on the conductive layer 114 with an insulating film interposed therebetween, and a pair of P ⁺ type regions 122,
123, and a pair of P ⁺ type regions 112,1
N-type impurities and hydrogen ions are implanted into the surface of the substrate 111 between the substrates 13 and 13 as necessary. One end of the P ⁺ type region 112 and the conductive layer 114 are connected to two address lines 57 to which one address signal and its inverted signal are respectively applied, and the other P ⁺ type region 113 and the conductive layer 114 The other end is connected to the gate of one MOS transistor 68. The initial state of such a circuit element is 1
Two address signal lines 57 are connected to the gate of one MOS transistor 68 via a conductive layer 114. When it becomes necessary to supply the signal of the remaining one address signal line 57 to the MOS transistor 68, the conductive layer 114 is fused in the middle by irradiating the laser beam in the same manner as described above, and at the same time the pair of address signal lines 57 are
By diffusing and fusing the P ⁺ type regions 112 and 113, the remaining address signal lines 57 are connected to the above through the fused pair of P ⁺ type regions 112 and 113.
It will be connected to the gate of MOS transistor 68. FIG. 11 is a block diagram of a decoder corresponding to FIG. 9, in which an element having the configuration shown in FIG. 10 is used in place of the pair of connection-only fuse elements 67. In this case, since the "H" level or "L" level signal on the address signal line 57 is applied to the gate of the MOS transistor 68 via each element, when the signal on the discharge control line 59 is at the "H" level, the point B becomes the "L" level, which may cause the selection line 54 to become the "H" level. Therefore, in the decoder shown in FIG.
It is necessary to insert a fuse element 67 exclusively for connection between the gate of the MOS transistor 69 and the gate of the MOS transistor 69. Note that this invention is not limited to the above-described embodiments, and various modifications are possible. For example, in FIG. 6, each wiring means 90 , 9
A pair of P ⁺ type regions 85 and 86 forming 1 and 92
The explanation has been made for the case where each of them is formed by extending the same semiconductor region, but in this case, as shown in FIG. 12, the P ⁺ type regions 85 and 86 are formed separately, and one P ⁺ type region 85 and the other P ⁺ type regions 86 may be interconnected by wirings 121 and 122 made of aluminum or the like, respectively. Further, in the cross-sectional view shown in FIG. 7, a conductive layer 93 made of polysilicon is connected to a pair of P ⁺ type regions 85, 8.
13 shows an example in which the laser beam is formed at a position overlapping the N ⁺ type region 87 formed between the two regions. As shown in the cross-sectional view of FIG ^. 14, a part of the conductive layer 93 may overlap with the N ⁺ type region 87, or as shown in the cross-sectional view of FIG. They may be configured so that they do not overlap closely. Further, in the above embodiment, the wiring is switched by irradiating with a laser beam, but this may be done by irradiating with another energy beam, such as an electron beam. Furthermore, although heating is performed from the outside, it is also possible to provide some kind of heating element inside the semiconductor device and heat it internally. Furthermore, although the case has been described in which the conductive layers 93 to 95 are formed of polysilicon, they may be formed of a metal or alloy whose melting point is lower than that of the insulating layer 105, such as aluminum or aluminum-silicon. It's okay. Further, in the above embodiment, a pair of P ⁺ type regions 85, 8
6, the P type impurity was diffused from both regions 85 and 86 into the N ⁺ type regions 87, 88, and 89.
In the configuration shown in FIGS. 13 and 14, both regions 85 and 86 can be fused by diffusion from only one P ⁺ type region 85. Furthermore, we have explained the case where hydrogen ions are implanted in the N ⁺ type regions 87, 88, and 89 for the purpose of increasing the lattice defects of the crystal. Alternatively, inert ions such as radon ions may be implanted. [Effects of the Invention] As described above, according to the present invention, a semiconductor device can be provided that can efficiently switch wiring when using a redundant function.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional semiconductor device with a redundant function, Figures 2 and 3 are cross-sectional views showing details of a portion of the conventional device, and Figure 4 is a general memory cell and its surroundings. Circuit diagram of section 5
The figure is a circuit configuration diagram when the conventional device of FIG. 1 is applied to a decoder, FIG. 6 is a configuration diagram of an embodiment of the present invention, and FIG. 7 is a sectional view taken along the line A-A'.
Figure 8 shows A in Figure 6 after switching the wiring.
- A sectional view taken along the line A', FIG. 9 is a circuit configuration diagram when the present invention is applied to a decoder, FIG. 10 is a diagram showing another example of a part thereof, and FIG. 11 is shown in FIG. 9. Circuit configuration diagram showing another example of a decoder, 1st
FIG. 2 is a block diagram of another embodiment of the present invention, and FIGS. 13 and 14 are other sectional views taken along line A-A' in FIG. 6, respectively. 81-83...Original functional circuit block, 84
...Functional circuit block for redundancy, 85, 86, 1
12,113...P ⁺ type region, 87-89...N ⁺
Mold area, 90-92...Wiring means, 93-95,
114... Conductive layer, 96-103... Wiring, 10
4,111N type semiconductor substrate, 105...insulating film, 106...field insulating film, 107...protective insulating film.

Claims (1)

[Claims] 1. First and second semiconductor regions of one conductivity type arranged and formed at a predetermined interval on the surface region of a semiconductor substrate of the other conductivity type, and sandwiched between the first and second semiconductor regions. It is formed on the surface region of the substrate and has a higher impurity concentration than the substrate, and is made up of a third semiconductor region of copper electrotype.In the initial state, it is electrically cut off and can be irradiated with energy rays. The impurities contained in the third semiconductor region are diffused into the first and second semiconductor regions by the heat generated by the irradiation, and the first and second semiconductor regions are fused, thereby selectively connecting the plurality of semiconductor regions. a first wiring means; a second wiring means for connecting the first semiconductor regions of the plurality of first wiring means; and a second wiring means for connecting the second semiconductor regions of the plurality of first wiring means. a third wiring means; and a conductive layer formed in the vicinity of the first wiring means via an insulating film, which are electrically connected in an initial state and provide an energy line to the first wiring means. A semiconductor device comprising: a plurality of fourth wiring means that are selectively brought into a cut-off state by melting a conductive layer due to heat generated during irradiation. 2. The semiconductor device according to claim 1, wherein the energy beam is either a laser beam or an electron beam. 3. The semiconductor according to claim 1, wherein the third semiconductor region has a threshold voltage such that an inversion layer is not generated by a normal voltage applied to the conductive layer of the fourth wiring means. Device. 4. The method according to claim 1, wherein at least one ion among hydrogen ions, helium ions, argon ions, krypton ions, xenon ions, and radon ions is implanted as the impurity into the third semiconductor region. Semiconductor equipment. 5. The semiconductor device according to claim 1, wherein the conductive layer of the fourth wiring means is made of a metal or an alloy whose melting point is lower than that of the insulating film.