JPH05160803A - Multiplexer - Google Patents

Abstract

PURPOSE:To attain early recovery of a fault by specifying the fault location of a multiplexer implementing the time slot exchange control of a time slot in data transmitter having plural communication channels. CONSTITUTION:The multiplexer is provided with plural line adaptor sections 5A, 5B, 5C, 6A, 6B, 6C accommodating plural communication channels. The line adaptor sections are inter-coupled by a multiplexer/demultiplexer section 3A through highways 4a, 4b subjected to time slot exchange control. Each line adaptor section and the multiplexer/demultiplexer section 3A are provided with a unit parity monitoring storage section 32. The highways 4a, 4b are provided respectively with highway parity monitoring storage sections 29a, 29b. At the time of the occurrence of a fault, data error monitoring information stored in each line adaptor section, the multiplexer/demultiplexer section 3A and the highways 4a, 4b are mutually compared by a monitoring storage section 1 and a fault location section 10 locates a fault location based on the result of comparison.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing device used by connecting to a communication network that requires early resolution of communication failures.

[0002]

2. Description of the Related Art FIG. 5 shows the structure of a conventional multiplexer.

In FIG. 5, 1 is a supervisory control unit, 1a is a network management device, 2 is a control bus, and 3 is a demultiplexing unit. 4a and 4b are highways, 5a, 5b, 5c and 6
a, 6b, 6c are line corresponding parts, 7 is a timing supply part,
Reference numeral 7a is a network synchronizer, and 8 is a clock bus.

FIG. 6 shows the line corresponding parts 5a, 5b, 5c, 6
The constituent blocks of a, 6b, and 6c are shown.

In FIG. 6, 11 is a line driver / receiver, 12 is a frame control circuit, 13a and 13b are frame memories (upstream) and frame memories (downstream), 1
4a and 14b are a control memory (upstream) and a control memory (downstream). 15a is a highway driver, 15b
Is a highway receiver, 16 is a clock receiver, 17
Is a control bus interface circuit, 18 is a parity monitoring circuit, and 19 is a parity calculation circuit.

Next, the operation of the conventional multiplexing device will be described with reference to FIGS. In FIG. 5, the supervisory control unit 1 monitors the operation of the entire device and sets the information (time slot number etc.) necessary for multiplexing under the control of the network management device 1a.
a, 5b, 5c and line corresponding parts 6a, 6b, 6c,
This is performed for the demultiplexing unit 3.

The control bus 2 transmits the setting information.
The demultiplexing unit 3 performs time slot exchange between the time slot on the highway 4a and the time slot on the highway 4b in order to interconnect the highway 4a and the highway 4b according to the setting information of the monitoring control unit 1. A plurality of time slots are formed on the highway 4a and the highway 4b. The data of each time slot has a frame format data structure, and a parity bit is arranged for each time slot. Line corresponding parts 5a, 5
b, 5c, 6a, 6b, and 6c perform frame transmission / reception of a communication line such as a subscriber line or a connection line to a transmission device, and at the same time, transmit the transmission frame on the communication line according to the setting information from the supervisory control unit 1. The channel signal is transmitted to the time slot on the highway 4a or the highway 4b, or conversely, the time slot on the highway 4a or the highway 4b is received and transmitted as the channel signal of the frame on the communication line. The timing supply unit 7 generates various timing signals required in the device from the reference clock received from the network synchronizer 7a, and demultiplexes the demultiplexing unit 3, the line corresponding units 5a, 5b and 5c and the line corresponding units 6a and 6a.
b, 6c. The clock bus 8 transmits the timing signal generated by the timing supply unit 7.

In FIG. 6, the frame control circuit 12 is
The channel signal of the transmission frame received from the line driver / receiver 11 is written in the frame memory (upstream) 13a, or the channel signal stored in the frame memory (downstream) 13b is read out and configured as a transmission frame, and the line driver -Transmit to the receiver 11.

Further, the frame control circuit 12 transmits information regarding abnormalities and maintenance of transmission / reception transmission frames to the control bus 2.

The control memories 14a and 14b are the monitoring control unit 1.
In order to exchange the channel signal of the transmission frame and the time position of the time slot of the highways 4a and 4b by the control bus 2, the read address and the write address of the frame memory are successively supplied. The highway driver 15a and the highway receiver 15b set by the control bus 2 are controlled to be opened / closed by the control memory 14a and the control memory 14b in synchronization with the time slot of the highway (up) and the highway.

The clock receiver 16 receives various timing signals supplied from the clock bus and supplies them to each block in the line interface.

The control bus interface circuit 17 performs interface processing between each block in the line corresponding units 5a, 5b, 5c, 6a, 6b, 6c and the control bus.

The parity calculation circuit 19 constantly calculates the parity of the signal in the frame memory and outputs only the parity on the highway (upstream).

The parity monitoring circuit 18 calculates the parity from the data of the time slot received from the highway (downstream) and compares it with the parity of the highway (downstream) received from the highway (downstream). At that time, if there is a difference between the calculated parity and the parity received from the highway (downstream), it is determined that some failure has occurred. This failure is caused by the control bus interface circuit 1
Monitor control unit 1 only when parity is abnormal through 7
Will be notified.

As described above, even in the conventional multiplexing device, it is possible to recognize the fault occurring in the device by detecting the parity abnormality.

[0016]

However, in this conventional multiplexer, the data error test is performed only inside the line interface that receives the data of the time slot from the highway. There is a problem that it is not possible to identify the cause point such as a transmission error, a failure of each circuit unit connected to the highway, or a failure of the highway itself.

The present invention solves such a conventional problem, and an object of the present invention is to provide an excellent multiplexer which can identify the cause of a data error and can quickly resolve a failure. ..

[0018]

In order to achieve this object, a multiplexer of the present invention comprises a plurality of line corresponding parts for accommodating a plurality of communication lines, and the demultiplexing means between the plurality of line corresponding parts. A multiplexer connected by a highway that is time slot exchange controlled by means of: control means for allocating channel data of transmission frames on the plurality of communication lines to a time slot on the highway in the line interface; When allocating channel data to time slots on the highway, data error verification information is added, and conversely, when data is distributed from the highway to the time slots of each line corresponding part, data errors added to the data of each time slot. Data for comparing and collating and storing verification information and data error verification information recalculated from the above data Monitoring and storing means, the demultiplexing means is provided with data error monitoring and storing means for each time slot before and after the time slot exchange, and for the highway, highway data error for each time slot input and output thereto. Monitoring information storage means is provided, and when a failure occurs, the updating of the data error monitoring information by the data error monitoring means of the line corresponding part and the demultiplexing part and the highway data error monitoring information storage means is temporarily stopped, and the stored contents thereof are retained. And a failure determining means for determining the cause of the failure.

[0019]

With such a configuration, the multiplexer of the present invention can detect the data error monitoring information for each time slot on the highway for each circuit part in the device, and the data for each circuit part can be detected. The fault location can be specified by mutually comparing and collating the error monitoring information.

[0020]

EXAMPLE FIG. 1 shows the configuration of an example. In FIG. 1, the same components as those shown in FIG. 5 are designated by the same reference numerals.

In FIG. 1, a highway parity monitoring storage unit 29a and a highway parity monitoring storage unit 29b are newly provided as compared with the configuration of the conventional example shown in FIG.

FIG. 2 shows line corresponding parts 5A, 5B, 5C, 6
The block diagram of A, 6B, and 6C is shown. Conventional line corresponding parts 5a, 5b, 5c, 6a, 6 shown in FIG.
Compared with b and 6c, a unit parity monitoring storage unit 32 having a configuration within the frame of a dotted line, in which a parity storage unit (upstream) 30 and a parity storage unit (downstream) 31 are added to the conventional parity monitoring circuit 18 and parity calculation circuit 19 Is provided.

The demultiplexing unit 3A has a circuit similar to that of the unit / parity monitoring storage unit 32 in addition to the configuration of the conventional example (not particularly shown).

FIG. 3 shows a highway parity monitoring storage unit 2.
The configuration of 9a or 29b is shown. These highway parity monitoring storage units are provided corresponding to highways (uplink) and highways (downlink).

In FIG. 3, 41a is a parity calculation monitoring circuit (upstream), 41b is a parity calculation monitoring circuit (downstream), 42a and 42b are memories, 43a and 43b are address generation circuits, and 44a and 44b are clock receivers. 45a and 45b are highway receivers, and 46 is a control bus interface.

The highways 4a and 4b are shown in FIGS.
As shown in, each has a highway 4a (uphill), a highway 4a (downhill), a highway 4b (uphill), and a highway 4b (downhill).

Next, the operation of the multiplexer of the embodiment will be described. As shown in FIG. 2, the line corresponding parts 5A, 5
In B, 5C, 6A, 6B, and 6C, the parity monitoring circuit 18 and the parity calculation circuit 19 respectively include a parity storage unit (downstream) 30 and a parity storage unit (upstream) 31.
It is connected to the.

The parity storage means (upstream) 31 is the parity information p calculated by the parity calculation circuit 19 when transmitting data to the designated time slot on the highway.
1 is stored in association with the time slot number. The parity storage means (downstream) 30 stores the parity information p2 of the data of each time slot received through the highway transmitted by the parity monitoring circuit 18, the parity information p3 recalculated by the parity monitoring circuit 18, and the parity information p2. Information q indicating whether or not the parity information p3 matches is stored in association with a corresponding reception time slot number from the highway.

The parity storage means (upstream) 30
The information stored in the parity storage means (downstream) 31 can be read by the fault isolation unit 10 shown in FIG. 1 through the control bus interface circuit 17.

The highway parity monitoring storage unit 29a or 29b in FIG. 1 includes the parity information p4 of each time slot on the highway of the highway (up) or the highway (down) and the parity calculation monitoring circuit (up) 41a or the parity calculation monitoring. Circuit (down) 41
The parity information p5 recalculated by b and the information r indicating whether or not the parity information p4 and the parity information p5 match are written in the memory 42a or 42b. The address generation circuits 43a and 43b are connected to the memory 42
The addresses a and 42b are generated and instructed so as to correspond to the highway time slot number 1: 1. The control bus interface 46 performs processing so that the fault isolation unit 10 can refer to the memories 42a and 42b.

The parity calculation monitoring circuit (upstream) 41
a or the parity calculation monitoring circuit (downstream) 41b detects the parity abnormality, the line corresponding part control signal line 33a
Or 33b to notify the occurrence to the line corresponding units 5A, 5B, 5C connected to the highway 4a or 4b to temporarily stop the update of the parity storage unit of each unit parity monitoring storage unit, and control the demultiplexing unit. Signal line 3
The demultiplexing unit 3A is also notified by 4a or 34b to temporarily stop the update of the parity storage unit of each unit parity monitoring storage unit.

Therefore, the line corresponding parts 5A, 5B, 5C, 6
A, 6B, and 6C of each unit parity monitoring storage unit 32 includes parity monitoring information of each line corresponding unit in the parity storage unit 30 or 31, and parity monitoring of the demultiplexing unit in each parity storage unit of the demultiplexing unit 3A. Information is retained.

Highway parity monitoring storage unit 29a, 2
At the same time, 9b sends a fault interrupt signal to the fault deciding section 10 through the fault interrupt signal line 35.

Upon receiving the fault interruption signal, the fault isolation unit 10 receives each parity storage unit in the demultiplexing unit 3A.
Line corresponding parts 5A, 5B, 5C and line corresponding parts 6A, 6
B and 6C highway parity monitoring storage units 29a and 29
By checking the parity information stored in b, it is possible to determine the failure point in the multiplexing device. The situation will be described below.

In FIG. 4, the parity monitoring information of each unit parity monitoring storage unit of the line corresponding units 5A, 5B and 5C of the multiplexer according to the embodiment, the parity of the parity storage unit of the unit monitoring storage unit of the demultiplexing unit 3A. The update information is temporarily stopped for each of the monitor information and the parity monitor information in the memory 42a of the highway parity monitor storage unit 29a.

In FIG. 4 (a), the communication lines held in the parity storage unit 31 of the line interface unit 5A are connected to the highway bus 4.
Time slots 1, 2, 3, 10 between a (up)
The result p1 of the parity calculation circuit 19 of the above data and FIG.
FIG. 4B shows the result p1 of the parity calculation circuit 19 of the data on the time slots 7 and 8 between the communication line held in the parity storage unit 31 of the line corresponding unit 5B and the highway bus 4a (up), and FIG. In c), the time slots 4, 5 between the communication line held in the parity storage unit 31 of the line corresponding unit 5C and the highway bus 4a (upstream).
The result p1 of the parity calculation circuit 19 of the data on 12 is shown.

In FIG. 4D, the parity information p4 of each time slot of the highway bus 4a (up) held in the memory 42a of the highway parity monitoring storage unit 29a and the parity calculation monitoring circuit (up) 41a. The parity information p5 recalculated by and the information r indicating whether or not the parity information p4 and the parity information p5 match are shown.

FIG. 4E shows the parity information p6 of the highway bus 4a (upstream) data stored in the unit parity monitoring storage unit on the side of the highway bus 4A in the demultiplexing unit 3A and the parity monitoring circuit. The parity calculation result information p7 and the information s indicating whether or not the parity information p6 and the parity calculation result information p7 match are shown.

In FIG. 4 (f), the data corresponding to the time slots 10 and 12 on the highway bus 4A (uplink) is time slot-exchanged by the demultiplexing unit 3A so as to correspond to the lines through the highway (downlink) time slots 10 and 12. Highway 4a (downlink) held in the parity storage unit 30 of the line interface 5A when transmitting to the unit 5A
And the highway 4a held in the parity storage unit 30 by the parity monitoring circuit 18 of the line interface 5A.
The parity calculation result information p3 of the data of the time slots 10 and 12 in (downlink) and the information q indicating whether or not the parity information p2 and the parity calculation result information p3 match are shown.

The time slots 1, 2 of the line interface 5A,
Parity monitoring information of 3 and 10, parity information of time slots 7 and 8 of the line interface 5B, and line interface 5C.
The parity information of the time slots 4, 5, and 12 is transmitted from each line circuit unit to the highway 4A (upstream).

These pieces of parity information are checked by the highway parity monitoring storage unit 29a, and the parity information shown in FIG.
Are stored in the memory 42a as described above.

From this result, the data from the time slots 1, 2, 3, 10 of the line interface 5A and the time slots 4, 5, 12 of the line interface 5C have been transmitted on the highway 4A without error. Is determined.

On the other hand, although the parity information of the time slots 7 and 8 added by the line corresponding unit 5B matches the parity information on the highway bus by the highway parity monitoring storage unit 29a, the parity calculation monitoring circuit (upstream) 41.
It does not match the data parity recalculation result by a.

From this, it can be determined that the line interface 5B is abnormal. Next, the data of the time slots 1, 2, 3, 4, 5, 7, 8 on the highway bus 4A are sent to the demultiplexing unit 3A. The parity information of the data of each time slot and the recalculation result of the parity in the unit parity monitoring storage unit (not particularly shown) of the demultiplexing unit 3A match the information on the highway bus shown in FIG. 4D. Therefore, the data of the time slots 1, 2, 3, 4, 5, 7, and 8 on the highway bus 4A are demultiplexed by the demultiplexer 3
It can be determined that A has been transmitted without error.

Furthermore, the parity information p4 on the highway 4A (upstream) and the parity information p2 of the data in the internal highway (downstream) time slots 10 and 12 of the line interface 5A shown in FIG. However, the parity re-calculation result information p3 for the data of the time slots 10 and 12 does not match with the parity monitoring circuit 18 of the line interface 5A.

From this result, it can be determined that a failure has occurred in the line interface 5A. In this way, when a failure occurs when data is transmitted / received to / from the highway bus 4a from a plurality of line corresponding parts at specific time slots, which line corresponding part on the data transmission side has a failure occurrence place? It is possible to identify at an early stage whether it is between the highway bus 4a and the demultiplexing unit 3A or which line corresponding unit on the receiving side.

The result of fault isolation by the fault isolation unit 10 of FIG. 1 is notified to the supervisory control unit 1 through the control bus 2 and further to the network management device.

In the multiplexer of the embodiment of the present invention, the parity check is used as the data error checking method, but other data error detecting methods can be applied.

[0049]

As is apparent from the above description, the multiplexing apparatus of the present invention has such a configuration that each circuit portion in the apparatus can detect the data error monitoring information for each time slot on the highway. It is possible to identify the fault location by mutually comparing and collating the data error monitoring information for each circuit part, and at the same time, the content of the fault condition can be grasped, so that measures for fault recovery can be taken early. It has the effect of being able to.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration in an embodiment of a multiplexing device of the present invention.

FIG. 2 is a configuration block diagram of a line interface unit in the embodiment.

FIG. 3 is a block diagram showing in detail the configuration of a highway parity monitoring storage unit in the embodiment.

FIG. 4 is a unit parity monitoring storage unit in the embodiment,
Explanatory diagram showing parity information stored in each parity storage unit of the highway parity monitoring storage unit and demultiplexing unit

FIG. 5 is a configuration block diagram of a conventional multiplexing device.

FIG. 6 is a block diagram showing the configuration of a line interface in a conventional multiplexer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 supervisory control part 2 control bus 3A demultiplexing part 4a, 4b highway 5A, 5B, 5C, 6A, 6B, 6C line corresponding part 10 fault isolation part 29a, 29b highway parity monitoring storage part 30, 31 parity storage means (upstream) And parity storage means (downstream) 32 unit parity monitoring storage unit 33a, 33b line corresponding unit control signal line 34a, 34b demultiplexing unit control signal line 35 fault interrupt signal line 41a, 41b parity calculation monitoring circuit (upstream) and parity calculation monitoring Circuit (down) 42a, 42b Memory

Claims (1)

[Claims] 1. A multiplexing device comprising a plurality of line corresponding parts accommodating a plurality of communication lines, wherein the plurality of line corresponding parts are connected by a highway that is time slot exchange controlled by demultiplexing means. Control means for allocating channel data of transmission frames on the plurality of communication lines to time slots on a highway, and data error verification information when allocating channel data to time slots on the highway are added to the line interface. On the contrary, at the time of data distribution from the highway to the time slot of each line corresponding part, the data error verification information added to the data of each time slot and the data error verification information recalculated from the data are compared and collated. And a data error monitoring storage means for storing the time slot in the demultiplexing means. A data error monitoring storage means for each time slot before and after the switching is provided, and a highway data error monitoring information storage means is provided for each time slot input to and output from the highway. The data demultiplexing unit of the demultiplexing unit and the highway data error monitoring information storage unit are provided with a failure determination unit for temporarily stopping the update of the data error monitoring information and determining the cause of the failure based on the stored contents. Multiplexer.