JPH05160364A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate a stress which is created in a trench by oxidation by a method wherein a polycrystalline silicon film is built up on a polycrystalline silicon film remaining in the trench selectively in a self-alignment manner and oxidized after the trench is completely filled. CONSTITUTION:A trench is formed selectively in a semiconductor substrate 1 and an insulating film 3 is formed on the substrate 1 surface including the inner wall of the trench 2. Then a polycrystalline silicon film 4 is deposited and the polycrystalline silicon film 4 is made to remain in the trench 2. After that, a polycrystalline silicon film 5 is selectively built up on the polycrystalline silicon film 4 remaining in the trench 2 so as to have its surface higher than the substrate 1 surface. Then the built up polycrystalline silicon film 5 is oxidized to form an oxide film 6. With this constitution, a stress created in the trench 2 by oxidation can be eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a highly integrated semiconductor memory.

[0002]

2. Description of the Related Art A method of manufacturing a DRAM cell having a trench capacitor, which is a first conventional technology, will be described in detail with reference to FIG. A field oxide film 102 for element isolation is formed on a P-type silicon substrate 101, and then the silicon substrate is selectively etched to form a groove 103. Only the inner wall of the trench, by introducing P, and n-type impurity such as As, n ^- Forming layer 104, n ⁻ Layer is SiO ₂ / SiN / SiO ₂
An insulating film 105 such as a (ONO) composite film is coated, and an n-type polysilicon film 106 is further deposited to form the polysilicon film 106, the ONO film 105, n ^−. A capacitor consisting of layer 104 is formed.

Next, as shown in FIG. 5, a photoresist 107 is applied, exposed and developed to form a desired resist pattern, and then the polysilicon film 106 is etched by isotropic etching. , Its end is groove 103
Try to fall inside. By doing so, the gap between the gate electrode of the transfer transistor to be formed later and the groove 103 can be narrowed, and a highly integrated DRAM cell can be manufactured. This is disclosed in JP-A-62-1714.
60 and JP-A-63-23351.

Next, as shown in FIG. 6, the formed plate electrode is oxidized to form an oxide film 108 on the plate in a self-aligned manner. At this time, since the surface of the silicon substrate is covered with the ONO film 105, the oxide film does not grow, and the oxide film can be formed only on the plate.

Next, as shown in FIG. 7, on the silicon substrate
The ONO film is removed, and the gate insulating film 1 of the transfer transistor is formed.
09, the gate electrode 110 is sequentially formed, and the source / drain is formed.
Forming a diffusion layer 111, and forming a storage electrode of the capacitor.
(N^- The layer 104) is connected to the transfer transistor. Furthermore
Then, an interlayer insulating film 112 is formed on the entire surface, and the source / drain is formed.
A contact hole 113 is formed on the diffusion layer 111,
And deposit a polycide film 114 that will be
Then, the bit line is formed. Next, as the second prior art
A method of manufacturing a bit line embedded DRAM cell will now be described with reference to FIG.
Will be explained.

An element isolation field oxide film 202 is formed on a P-type silicon substrate 201, and then the silicon substrate is selectively etched to form a groove 203. Further, a first insulating film 204 is formed along the inner wall of the groove. (Fig. 8
(A), FIG. 9 (a)). 8 (a) and 9 (a) respectively show orthogonal cross sections, and FIG. 8 (a) shows FIG.
9A is a cross section perpendicular to the paper surface of the arrow part shown in FIG. 9A, and FIG. 9A shows a cross section perpendicular to the paper surface of the arrow part shown in FIG.

Next, a photoresist 205 is applied, exposed and developed to form a resist pattern so that a part of the side surface of the groove is exposed. The first insulating film 204 formed on the side surface of the groove is removed by etching, and the contact hole 20 is formed on the side surface of the groove.
6 is opened (FIGS. 8 (b) and 9 (b)).

Next, after removing the resist, for example, an n-type polysilicon film 207 is deposited and etched back to remain inside the trench. The sidewall contact portion 206 has n
N ⁻ by introducing a type impurity Forming layer 208,
A contact between the silicon substrate and the polysilicon film 207 is made possible (FIG. 8C).

Here, the polysilicon film remaining inside the trench forms a bit line. Next, by oxidizing the polysilicon film, the oxide film 209 is self-aligned on the bit line.
Are grown and the bit lines are separated (FIG. 8D).

Next, a gate insulating film 210 and a gate electrode 211 of the transfer transistor are sequentially formed on a silicon substrate, a source / drain diffusion layer 212 is formed, and n ⁻ Layer 2
08 and the transfer transistor are connected. Next, the interlayer insulating film 213 is formed on the entire surface, and the contact hole 21 is formed on the source / drain diffusion layer 212 provided via the transfer transistor.
4, a polysilicon film 21 which is to be a storage electrode
5 is deposited and patterned. The storage electrode preferably has a cylindrical shape as shown in FIG. 9C in order to increase the cell capacity. Further, the capacitor gate insulating film 216
And a plate electrode 217 are deposited to form a capacitor. (FIG.8 (e), FIG.9 (c)).

[0011]

In the above-mentioned prior art, the oxide film 108 shown in FIG. 6 and the oxide film 209 shown in FIG. 8D are the plate electrode and the gate electrode of the transfer transistor in the former, and the bit in the latter. It is for separating the line and the gate electrode of the transfer transistor, and plays a very important role in the DRAM configuration. If this separation is not done properly, a malfunction will occur.
A thick oxide film of 0 to 2000 angstrom is required. Further, in order to realize a highly integrated DRAM, it is necessary to form it in a self-aligned manner. Oxidation of the polysilicon film is an effective means for forming an oxide film in a self-aligned manner, but the following problems have occurred.

It is known that a large stress is generated in the portion shown by the circle in FIGS. 6 and 8D, and this stress leads to the generation of crystal defects and deteriorates the breakdown voltage of the capacitor. As described above, the generation of strong stress due to oxidation significantly reduces the reliability of DRAM.

The method of manufacturing a semiconductor device according to the present invention has been made in view of such a problem, and an object thereof is to relieve a strong stress due to the oxidation of polysilicon, to achieve high reliability and high integration. Another object of the present invention is to provide a method for manufacturing a DRAM cell semiconductor device.

[0014]

To achieve the above object, a step of selectively forming a groove in a semiconductor substrate, a step of forming an insulating film on the substrate surface including the inner wall of the groove, and a polysilicon film Is deposited and left at least in the trench, a step of selectively growing a polysilicon film on the remaining polysilicon film and forming the surface of the polysilicon film above the substrate surface, and oxidation of the grown polysilicon film. And a step of performing.

[0015]

That is, in the present invention, a groove is selectively formed in the semiconductor substrate, an insulating film is formed on the substrate surface including the inner wall of the groove, and a polysilicon film is deposited and left at least in the groove. A polysilicon film is selectively grown on the polysilicon film, its surface is formed above the substrate surface, and the grown polysilicon film is oxidized.

[0016]

First, the outline of the present invention will be described with reference to FIGS. 1 (a) and 1 (b). First, the groove 2 is selectively formed on the semiconductor substrate 1.
To form. Next, the insulating film 3 is formed on the substrate surface 1 including the inner wall of the groove 2. Next, a polysilicon film 4 is deposited and left at least in the trench 2. A polysilicon film 5 is selectively grown on the remaining polysilicon film 4 and its surface is formed above the substrate surface 1 (FIG. 1A). next,
The grown polysilicon film 5 is oxidized to form an oxide film 6 (FIG. 1 (b)). The method of manufacturing the DRAM cell having the trench capacitor according to the first embodiment will be described below with reference to FIG. The process up to the formation of the capacitor is the same as that of the conventional technique and will not be described. Therefore, the continuation of FIG. 5 will be described below.

Patterned polysilicon film 106
A polysilicon film 115 is selectively grown only on the top using the SEG technique (FIG. 2A). At this time, since the polysilicon film does not grow on the oxide film on the surface of the substrate, it becomes self-aligned with the groove. Also, note that the polysilicon film overflows from the surface or inside the groove and continues to grow until it is located above the substrate surface. After completely filling the groove, the polysilicon film is oxidized to form an oxide insulating film 116 (FIG. 2B). By doing so, oxidation occurs only outside the groove and no stress is generated. Moreover, the oxide film 116 is also self-aligned with the groove. Since the method of forming the next transfer transistor and bit line is exactly the same as that of the conventional technique, it will be omitted only by referring to FIG.

Bit line embedded type DR according to the second embodiment
A method of manufacturing the AM cell will be described with reference to FIG. The embedding of the bit line is the same as the conventional technique. The description will be continued from the continuation of FIG. A polysilicon film 218 is selectively deposited on the bit line 207 by SEG. (Fig. 3 (a))

At this time, the groove is made to overflow.
Then, this is oxidized to form an oxide film 219 only on the bit line in a self-aligned manner (FIG. 3B). The subsequent steps are the same as in the conventional technique and will not be described.

As described above, in the present invention, polysilicon is selectively deposited on the polysilicon buried in the groove and grown until the surface overflows from the groove and is located above the substrate surface. After that, oxidation is performed so that stress is not applied to the groove and an oxide film is formed in a self-aligned manner with the groove.

[0021]

EFFECTS OF THE INVENTION By growing a polysilicon film in a self-aligning and selective manner on the polysilicon film remaining in the groove, completely filling the groove, and then oxidizing the polysilicon film, stress acting in the groove due to oxidation is eliminated. be able to. As a result, a highly reliable and highly integrated semiconductor device without crystal defects can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process showing the outline of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process showing a first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process showing a second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a part of a conventional manufacturing process of a semiconductor device.

FIG. 5 is a cross-sectional view showing a part of the conventional manufacturing process of a semiconductor device.

FIG. 6 is a cross-sectional view showing a part of the conventional manufacturing process of a semiconductor device.

FIG. 7 is a cross-sectional view showing a part of the conventional manufacturing process of a semiconductor device.

FIG. 8 is a cross-sectional view showing another manufacturing process of the conventional semiconductor device.

FIG. 9 is a cross-sectional view showing a part of another manufacturing process of the conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Trench, 3 ... Insulating film, 4, 5 ... Polysilicon film, 6 ... Oxide film, 101, 201 ... P-type silicon substrate, 102, 202 ... Field oxide film, 103, 2
03 ... groove, 104,208 ... n ^- Layer, 105 ... ONO
Film, 106, 207 ... Polysilicon film, 107, 205
... resist, 108,209 ... oxide film, 109,210
... Gate insulating film, 110, 211 ... Gate electrode, 11
1,212 ... n ^- Layers, 112, 213 ... interlayer insulating film, 1
13, 214 ... Contact hole, 114 ... Polycide film,
204 ... Insulating film, 206 ... Side wall contact hole, 215 ...
Storage electrodes, 216 ... Capacitor insulating film, 217 ...
Plate electrodes, 115, 218 ... Polysilicon film, 11
6, 219 ... Oxide film.

Claims (1)

[Claims] 1. A step of selectively forming a groove in a semiconductor substrate, a step of forming an insulating film on a substrate surface including an inner wall of the groove, a step of depositing a polysilicon film and leaving the polysilicon film at least in the groove, A semiconductor device comprising: a step of selectively growing a polysilicon film on the remaining polysilicon film and forming a surface of the polysilicon film above the surface of the substrate; and a step of oxidizing the grown polysilicon film. Production method.