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JPH05160288A - Manufacture of semiconductor device mounting substrate - Google Patents

Manufacture of semiconductor device mounting substrate

Info

Publication number
JPH05160288A
JPH05160288A JP34916291A JP34916291A JPH05160288A JP H05160288 A JPH05160288 A JP H05160288A JP 34916291 A JP34916291 A JP 34916291A JP 34916291 A JP34916291 A JP 34916291A JP H05160288 A JPH05160288 A JP H05160288A
Authority
JP
Japan
Prior art keywords
semiconductor device
thin plate
aluminum
mounting substrate
device mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP34916291A
Other languages
Japanese (ja)
Other versions
JP2953163B2 (en
Inventor
Makoto Chokai
誠 鳥海
Hirokazu Tanaka
宏和 田中
Hideaki Yoshida
秀昭 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP34916291A priority Critical patent/JP2953163B2/en
Publication of JPH05160288A publication Critical patent/JPH05160288A/en
Application granted granted Critical
Publication of JP2953163B2 publication Critical patent/JP2953163B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
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    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To prevent nickel plating from peeling off by removing a deformed part in a thin plate surface of aluminum or aluminum alloy and by performing nickel plating for the part. CONSTITUTION:An aluminum or aluminum alloy layer is formed on the surface of a ceramic substrate 11 whereon a semiconductor device is mounted and the entire surface of the layer is mechanically polished. Resist of a specified pattern is applied to the mechanically polished surface and a specified part of the mechanically polished surface whereto the resist is not applied is chemically polished. A nickel plating layer 14 is formed in the specified part. Therefore, the deformed part is removed by chemical polishing and nickel plating is performed for the surface which is not deformed. The nickel plating layer 14 is thereby completely prevented from peeling off an aluminum or aluminum alloy layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置実装用基板
の製造方法に関し、詳しくはセラミックス基板表面に被
着したアルミニウム等の薄板を化学的に研磨したセラミ
ックス基板を製造する場合、この薄板の表面が変質しな
いようにした半導体装置実装用基板の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a substrate for mounting a semiconductor device, and more specifically, in the case of manufacturing a ceramic substrate by chemically polishing a thin plate of aluminum or the like adhered to the surface of the ceramic substrate, The present invention relates to a method for manufacturing a semiconductor device mounting substrate, the surface of which is not altered.

【０００２】[0002]

【従来の技術】従来、例えばＩＣチップ等の半導体装置
を搭載する半導体装置実装用基板は、セラミックス基板
にアルミニウムまたはアルミニウム合金の薄板が被着さ
れ、この薄板の所定部分にニッケルがメッキされてい
た。2. Description of the Related Art Conventionally, in a semiconductor device mounting substrate for mounting a semiconductor device such as an IC chip, a ceramic substrate is covered with a thin plate of aluminum or aluminum alloy, and nickel is plated on a predetermined portion of the thin plate. ..

【０００３】この従来の半導体装置実装用基板の製造方
法を図１１〜図１７を用いて説明する。まず、アルミナ
等のセラミックス基板２１を準備し（図１１）、このセ
ラミックス基板２１の両面に回路パターン形成用、ヒー
トシンク接合用のアルミニウムまたはアルミニウム合金
の薄板２２をそれぞれ被着していた（図１２）。次に、
この薄板２２に機械的研磨（図１３）および化学的研磨
（図１４）を順番に施していた。なお、機械的研磨は、
上記薄板２２の表面の酸化層を除去するために行ってい
る。そして、化学的研磨は、上記薄板２２とニッケルと
の接合強度を上げるために行っている。次に、この薄板
２２の一部分に所定パターンのレジスト２３を塗布して
いた（図１５）。次に、レジスト２３が塗布されてない
薄板２２の表面にニッケル２４をメッキしていた（図１
６）。次に、このレジスト２４を除去することにより、
上記薄板２２の他の一部分にニッケル２４がメッキされ
るものである（図１７）。A conventional method of manufacturing a semiconductor device mounting substrate will be described with reference to FIGS. First, a ceramic substrate 21 made of alumina or the like was prepared (FIG. 11), and aluminum or aluminum alloy thin plates 22 for forming a circuit pattern and for heat sink bonding were respectively attached to both surfaces of the ceramic substrate 21 (FIG. 12). .. next,
The thin plate 22 was mechanically polished (FIG. 13) and chemically polished (FIG. 14) in this order. In addition, mechanical polishing is
This is done to remove the oxide layer on the surface of the thin plate 22. Then, chemical polishing is performed to increase the bonding strength between the thin plate 22 and nickel. Next, a resist 23 having a predetermined pattern was applied to a part of the thin plate 22 (FIG. 15). Next, the surface of the thin plate 22 on which the resist 23 was not applied was plated with nickel 24 (see FIG. 1).
6). Next, by removing the resist 24,
The other part of the thin plate 22 is plated with nickel 24 (FIG. 17).

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の半導体装置実装用基板の製造方法にあって
は、化学的研磨の後、レジスト工程でアルミニウムまた
はアルミニウム合金の薄板表面が変質してしまう。その
結果、ニッケルメッキが剥げてしまう。従って、半導体
装置実装用基板の信頼性が低下してしまうという課題が
あった。However, in such a conventional method for manufacturing a semiconductor device mounting substrate, the surface of the aluminum or aluminum alloy thin plate is altered in the resist step after chemical polishing. .. As a result, the nickel plating comes off. Therefore, there is a problem in that the reliability of the semiconductor device mounting substrate decreases.

【０００５】[0005]

【発明の目的】そこで、本発明は、アルミニウムまたは
アルミニウム合金の薄板表面からのニッケルメッキの剥
離を防止し、半導体装置実装用基板の信頼性を向上させ
た半導体装置実装用基板の製造方法を提供することを、
その目的としている。SUMMARY OF THE INVENTION Therefore, the present invention provides a method for manufacturing a semiconductor device mounting substrate, which prevents the nickel plating from peeling off from the surface of a thin plate of aluminum or aluminum alloy and improves the reliability of the semiconductor device mounting substrate. To do
That is the purpose.

【０００６】[0006]

【課題を解決するための手段】本発明は、半導体装置が
実装されるセラミックス基板面にアルミニウムまたはア
ルミニウム合金の層を形成する工程と、この層の全面に
機械的研磨を施す工程と、この機械的研磨された面に所
定パターンのレジストを被着する工程と、このレジスト
が被着されていない機械研磨面の所定部分に化学的研磨
を施す工程と、この所定部分にニッケルメッキ層を形成
する工程と、を備えた半導体装置実装用基板の製造方法
である。According to the present invention, there is provided a step of forming a layer of aluminum or an aluminum alloy on a surface of a ceramic substrate on which a semiconductor device is mounted, a step of mechanically polishing the entire surface of the layer, and a step of performing the mechanical polishing. A step of depositing a resist having a predetermined pattern on the mechanically polished surface, a step of chemically polishing a predetermined portion of the mechanically polished surface on which the resist is not deposited, and a nickel plating layer formed on the predetermined portion A method of manufacturing a semiconductor device mounting substrate, comprising:

【０００７】[0007]

【作用】本発明に係る半導体装置実装用基板の製造方法
にあっては、アルミニウムまたはアルミニウム合金の薄
板の面の所定部分についてはレジストプロセスにより変
質するが、この変質した面に化学的研磨を施し、この所
定部分にニッケルメッキ層を形成している。このため、
変質した部分が化学的研磨により除去され、変質のない
状態の面にニッケルメッキが施されることとなる。よっ
て、アルミニウムまたはアルミニウム合金層に対するニ
ッケルメッキ層の剥離は完全に防止されることとなる。In the method for manufacturing a semiconductor device mounting substrate according to the present invention, a predetermined portion of the surface of the aluminum or aluminum alloy thin plate is altered by the resist process, and the altered surface is chemically polished. A nickel plating layer is formed on this predetermined portion. For this reason,
The altered portion is removed by chemical polishing, and the surface in the unaltered state is nickel-plated. Therefore, peeling of the nickel plating layer from the aluminum or aluminum alloy layer can be completely prevented.

【０００８】[0008]

【実施例】以下、本発明に係る半導体実装用基板の製造
方法を実施例に基づいて説明する。図１〜図１０は、本
発明の一実施例を説明するためのものである。EXAMPLES A method for manufacturing a semiconductor mounting substrate according to the present invention will be described below based on examples. 1 to 10 are for explaining one embodiment of the present invention.

【０００９】まず、絶縁性のセラミックス基板として、
例えば所定の厚さの純度９６％のＡｌ2Ｏ3焼結体である
アルミナ基板１１を使用するものとする（図１）。そし
て、このアルミナ基板１１の上面には、例えば純度が９
９.９９％のアルミニウム製の回路形成用薄板１２が、
例えばＡｌ−Ｓｉ合金およびＡｌ−Ｇｅ合金からなるろ
う材により接着されている。さらに、アルミナ基板１１
の下面には、例えば同じく純度９９.９９％のアルミニ
ウム製のヒートシンク接合用薄板１８がろう材により接
着されている（図２）。First, as an insulating ceramic substrate,
For example, an alumina substrate 11 which is an Al 2 O 3 sintered body having a predetermined thickness and a purity of 96% is used (FIG. 1). And, on the upper surface of the alumina substrate 11, for example, a purity of 9
The circuit forming thin plate 12 made of 9.99% aluminum is
For example, they are bonded by a brazing material made of an Al-Si alloy and an Al-Ge alloy. Further, the alumina substrate 11
A heat sink joining thin plate 18, which is also made of aluminum and has a purity of 99.99%, is adhered to the lower surface of the sheet by a brazing material (FIG. 2).

【００１０】これらの接着は、ろう材を薄板１２と薄板
１８との圧延加工時に３０μｍの厚さにクラッドしてろ
う付け板材（ブレージングシート）とし、これらの材料
を積み重ねた状態で、ろう材に適合した４３０〜６１０
℃の温度範囲内に真空中で１０分間保持した条件でろう
付けして積層接合体とし、３５０℃で３０分間の熱処理
後室温まで徐冷することによって行っている。なお、薄
板材１２の回路形成は、接合前の形成回路の打ち抜き、
または、接合後のエッチング加工等により行っている。These are adhered to each other by brazing the brazing material to a thickness of 30 μm when the thin plate 12 and the thin plate 18 are rolled to form a brazing plate material (brazing sheet), and stacking these materials on the brazing material. 430-610 matched
It is carried out by brazing under a condition of being kept in a vacuum temperature range of 10 ° C. for 10 minutes to form a laminated joined body, followed by heat treatment at 350 ° C. for 30 minutes and then gradually cooling to room temperature. In addition, the circuit formation of the thin plate material 12 is performed by punching out the forming circuit before joining,
Alternatively, etching is performed after joining, or the like.

【００１１】上記薄板１２および薄板１８としては、純
アルミニウムの他にも、例えばＡｌ−２.５％（重量
％、以下同じ）Ｍｇ−０.２％Ｃｒ合金、Ａｌ−１％Ｍ
ｎ合金、Ａｌ−０.０２％Ｎｉ合金、Ａｌ−０.００５％
Ｂ合金等を用いることができる。As the thin plate 12 and the thin plate 18, in addition to pure aluminum, for example, Al-2.5% (weight%, hereinafter the same) Mg-0.2% Cr alloy, Al-1% M.
n alloy, Al-0.02% Ni alloy, Al-0.005%
B alloy or the like can be used.

【００１２】次に、薄板１２の上面およびに薄板１８の
下面に、例えばポリシング等の機械的研磨を施す（図
３）ことにより、これらの表面上の酸化膜を除去する。
次に、この薄板１２上面にフォトレジスト膜１３を被
着、露光等することにより所定のパターンのフォトレジ
スト膜１３を形成する（図４）。このとき、薄板１２上
面でこのレジストプロセスによってレジストが除去され
て露出した部分は変質している可能性がある。Next, the upper surface of the thin plate 12 and the lower surface of the thin plate 18 are subjected to mechanical polishing such as polishing (FIG. 3) to remove the oxide film on these surfaces.
Next, a photoresist film 13 is deposited on the upper surface of the thin plate 12 and exposed to light to form a photoresist film 13 having a predetermined pattern (FIG. 4). At this time, there is a possibility that the exposed portion of the upper surface of the thin plate 12 where the resist is removed by this resist process is deteriorated.

【００１３】次に、薄板１２の上面でフォトレジスト膜
１３が形成されていない部分および薄板１８の下面に化
学的研磨を施す（図５）。例えば５０〜９０℃の温度範
囲で、リン酸２０〜６０％、硝酸２〜４０％に硫酸２０
〜６０％を添加した液中に、数秒〜数分間浸漬させて行
う。この化学的研磨により、機械的研磨により生じた凸
部を化学的に溶解させ平滑にするものである。Next, the upper surface of the thin plate 12 where the photoresist film 13 is not formed and the lower surface of the thin plate 18 are chemically polished (FIG. 5). For example, in the temperature range of 50 to 90 ° C., phosphoric acid 20 to 60%, nitric acid 2 to 40%, and sulfuric acid 20
It is performed by immersing it in a liquid added with -60% for several seconds to several minutes. By this chemical polishing, the convex portions generated by the mechanical polishing are chemically dissolved and smoothed.

【００１４】次に、化学研磨されている面、すなわちフ
ォトレジスト膜１３が形成されていない薄板１２の上面
および薄板１８の下面全面に厚さ５μｍのニッケルメッ
キ層１４を通常の無電解メッキ法により被着する（図
６）。そして、フォトレジスト膜１３を除去することに
より、ニッケルメッキ層１４は、薄板１２の所定面と薄
板１８の下面に形成されるものである（図７）。Next, a nickel-plated layer 14 having a thickness of 5 μm is formed on the chemically polished surface, that is, the upper surface of the thin plate 12 on which the photoresist film 13 is not formed and the entire lower surface of the thin plate 18 by a normal electroless plating method. It is applied (Fig. 6). Then, by removing the photoresist film 13, the nickel plating layer 14 is formed on the predetermined surface of the thin plate 12 and the lower surface of the thin plate 18 (FIG. 7).

【００１５】そして、この半導体装置実装用基板に半導
体装置を実装する場合は、例えばダイボンディングとワ
イヤボンディングとを施す。つまり、まずニッケルメッ
キ層１４にＰｂ−Ｓｎ製のはんだ１５を被着する（図
８）。このはんだ１５を介して、ＩＣチップ１６等を実
装し固定する（図９）。そして、超音波エネルギーを用
いて、ＩＣチップ１６等のパッドと上記薄板２２の回路
パターンの所定部分とを直径２５〜３００μｍの純度９
９.９９％のアルミニウム線１７で接続する。さらに、
薄板１２、１８と同じ材料のヒートシンク１９をはんだ
１５を介して基板に接合するものである。When mounting a semiconductor device on this semiconductor device mounting substrate, for example, die bonding and wire bonding are performed. That is, first, the Pb—Sn solder 15 is applied to the nickel plating layer 14 (FIG. 8). The IC chip 16 and the like are mounted and fixed via the solder 15 (FIG. 9). Then, using ultrasonic energy, the pad such as the IC chip 16 and a predetermined portion of the circuit pattern of the thin plate 22 having a diameter of 25 to 300 μm and a purity of 9 are used.
Connect with 9.99% aluminum wire 17. further,
A heat sink 19 made of the same material as the thin plates 12 and 18 is joined to the substrate via the solder 15.

【００１６】このように化学的研磨してニッケルメッキ
を施した結果、このニッケルメッキ層１４のアルミニウ
ム薄板１２、１８に対する密着不良は生じることなく、
ニッケルメッキ１４がもろくなったり、これにピットや
シミ等が発生するこもない。これにより、はんだ１５の
ニッケルメッキ層１４へののりが良くなり、ＩＣチップ
１６やヒートシンク１９の接合強度が向上する。したが
って、半導体実装装置用基板の品質が向上する。As a result of the chemical polishing and nickel plating in this way, the nickel plating layer 14 does not adhere to the aluminum thin plates 12 and 18 poorly, and
The nickel plating 14 does not become brittle, and pits and stains do not occur on it. This improves the adhesion of the solder 15 to the nickel plating layer 14 and improves the bonding strength of the IC chip 16 and the heat sink 19. Therefore, the quality of the semiconductor mounting device substrate is improved.

【００１７】なお、上記実施例にあっては、アルミナ基
板１１に薄板１８とニッケルメッキ層１５とを介しない
で、ヒートシンク１９をアルミナ基板１１に直接ろう材
を介して接着してもよい。In the above embodiment, the heat sink 19 may be directly adhered to the alumina substrate 11 via the brazing material instead of the thin plate 18 and the nickel plating layer 15 on the alumina substrate 11.

【００１８】[0018]

【発明の効果】本発明によれば、アルミニウムまたはア
ルミニウム合金の薄板表面において変質した部分を除去
することができ、この部分にニッケルメッキを施してい
る。この結果、ニッケルメッキの剥離を防止することが
できる。したがって、半導体装置実装用基板の信頼性を
向上させることができる。According to the present invention, the altered portion of the surface of a thin plate of aluminum or aluminum alloy can be removed, and this portion is nickel-plated. As a result, peeling of the nickel plating can be prevented. Therefore, the reliability of the semiconductor device mounting substrate can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例に係る半導体装置実装用基板
の製造方法の一工程を示す断面図である。FIG. 1 is a cross-sectional view showing a step of a method of manufacturing a semiconductor device mounting substrate according to an embodiment of the present invention.

【図２】本発明の一実施例に係る半導体装置実装用基板
の製造方法の一工程を示す断面図である。FIG. 2 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

【図３】本発明の一実施例に係る半導体装置実装用基板
の製造方法の一工程を示す断面図である。FIG. 3 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

【図４】本発明の一実施例に係る半導体装置実装用基板
の製造方法の一工程を示す断面図である。FIG. 4 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

【図５】本発明の一実施例に係る半導体装置実装用基板
の製造方法の一工程を示す断面図である。FIG. 5 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

【図６】本発明の一実施例に係る半導体装置実装用基板
の製造方法の一工程を示す断面図である。FIG. 6 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

【図７】本発明の一実施例に係る半導体装置実装用基板
の製造方法の一工程を示す断面図である。FIG. 7 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

【図８】本発明の一実施例に係る半導体装置実装用基板
の製造方法の一工程を示す断面図である。FIG. 8 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

【図９】本発明の一実施例に係る半導体装置実装用基板
の製造方法の一工程を示す断面図である。FIG. 9 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

【図１０】本発明の一実施例に係る半導体装置実装用基
板の製造方法の一工程を示す断面図である。FIG. 10 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

【図１１】従来の半導体装置実装用基板の製造方法の一
工程を示す断面図である。FIG. 11 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device mounting substrate.

【図１２】従来の半導体装置実装用基板の製造方法の一
工程を示す断面図である。FIG. 12 is a cross-sectional view showing a step of the method of manufacturing the conventional semiconductor device mounting substrate.

【図１３】従来の半導体装置実装用基板の製造方法の一
工程を示す断面図である。FIG. 13 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device mounting substrate.

【図１４】従来の半導体装置実装用基板の製造方法の一
工程を示す断面図である。FIG. 14 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device mounting substrate.

【図１５】従来の半導体装置実装用基板の製造方法の一
工程を示す断面図である。FIG. 15 is a cross-sectional view showing a step of the method of manufacturing the conventional semiconductor device mounting substrate.

【図１６】従来の半導体装置実装用基板の製造方法の一
工程を示す断面図である。FIG. 16 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device mounting substrate.

【図１７】従来の半導体装置実装用基板の製造方法の一
工程を示す断面図である。FIG. 17 is a cross-sectional view showing a step of the method of manufacturing the conventional semiconductor device mounting substrate.

【符号の説明】[Explanation of symbols]

１１ アルミナ基板 １２ 回路形成用薄板 １４ ニッケルメッキ層 １６ ＩＣチップ １８ ヒートシンク接合用薄板 11 Alumina Substrate 12 Circuit Forming Thin Plate 14 Nickel Plating Layer 16 IC Chip 18 Heat Sink Bonding Thin Plate

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体装置が実装されるセラミックス基
板面にアルミニウムまたはアルミニウム合金の層を形成
する工程と、 この層の全面に機械的研磨を施す工程と、 この機械的研磨された面に所定パターンのレジストを被
着する工程と、 このレジストが被着されていない機械研磨面の所定部分
に化学的研磨を施す工程と、 この所定部分にニッケルメッキ層を形成する工程と、を
備えたことを特徴とする半導体装置実装用基板の製造方
法。1. A step of forming an aluminum or aluminum alloy layer on a surface of a ceramic substrate on which a semiconductor device is mounted, a step of mechanically polishing the entire surface of this layer, and a predetermined pattern on the mechanically polished surface. And a step of chemically polishing a predetermined portion of the mechanically polished surface on which the resist is not deposited, and a step of forming a nickel plating layer on the predetermined portion. A method for manufacturing a substrate for mounting a semiconductor device, which is characterized.
JP34916291A 1991-12-06 1991-12-06 Method for manufacturing substrate for mounting semiconductor device Expired - Lifetime JP2953163B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34916291A JP2953163B2 (en) 1991-12-06 1991-12-06 Method for manufacturing substrate for mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34916291A JP2953163B2 (en) 1991-12-06 1991-12-06 Method for manufacturing substrate for mounting semiconductor device

Publications (2)

Publication Number Publication Date
JPH05160288A true JPH05160288A (en) 1993-06-25
JP2953163B2 JP2953163B2 (en) 1999-09-27

Family

ID=18401892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34916291A Expired - Lifetime JP2953163B2 (en) 1991-12-06 1991-12-06 Method for manufacturing substrate for mounting semiconductor device

Country Status (1)

Country Link
JP (1) JP2953163B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006524583A (en) * 2003-04-25 2006-11-02 サン−ゴバン セラミックス アンド プラスティクス，インコーポレイティド Method for machining ceramics
JP2013214541A (en) * 2012-03-30 2013-10-17 Mitsubishi Materials Corp Method for manufacturing power module substrate and power module substrate

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006019099A1 (en) 2004-08-17 2006-02-23 Mitsubishi Materials Corporation Insulation substrate, power module substrate, manufacturing method thereof, and power module using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006524583A (en) * 2003-04-25 2006-11-02 サン−ゴバン セラミックス アンド プラスティクス，インコーポレイティド Method for machining ceramics
JP2013214541A (en) * 2012-03-30 2013-10-17 Mitsubishi Materials Corp Method for manufacturing power module substrate and power module substrate

Also Published As

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JP2953163B2 (en) 1999-09-27

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