JPH05158841A - Communication controller - Google Patents

Abstract

PURPOSE:To improve evaluating efficiency by tracing the generation interval of host interface control information and transferred data at the time of tracing the host interface control information and the transferred data for a line in communication control. CONSTITUTION:At the time when trace information is stored in a memory 104, the output count value of a counter control part 103 too is stored in the memory 104, and the count value of the counter control part 103 is reset. The count value of the counter control part 103 is counted up at definite intervals, and is stopped at a maximum value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device.

[0002]

2. Description of the Related Art Conventionally, a communication control apparatus of this type has a dedicated external interface control section or a dedicated display control section for storing control information and outputting it to the outside.

[0003]

In this conventional communication control device, especially in a high-speed line, the control timing is often important for the operation analysis, so that the operation analysis is often difficult only with the control information. Further, there is a dedicated external interface control unit and a connector for outputting the failure log information, which requires a mounting area. Furthermore, there is a problem that an external maintenance device is always required to output the fault log information, and the fault log information cannot be collected unless the external maintenance device is present at the site when the fault occurs.

[0004]

A communication control apparatus according to the present invention comprises a host interface control section for transferring data to and from an information processing apparatus, and a transmission / reception control section connected to a line for controlling transmission / reception such as serial / parallel conversion. In a communication control device having a processor, and a storage unit for sequentially storing control response information from the information processing device and transmission / reception data to / from the transmission / reception control unit, the memory is reset / started for each writing to the storage unit. A counting unit for monitoring the information writing interval to the unit and a count value storing unit for writing the count value of the counter unit at the same time as writing to the storage unit are provided.

Then, when a failure occurrence is detected, the contents of the storage unit and the count value storage unit are read out and displayed as serial data via the transmission / reception control unit, and the serial data output from the line to the display unit. And a first switching means for switching. Further, it is provided with a second switching unit which is connected to the transmission / reception control unit and switches the serial data transfer rate, and a switching instruction unit which instructs this switching by an external operation.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the communication control device of the present invention.

Referring to FIG. 1, the processor 101 in the present embodiment controls the entire communication control apparatus, and a high-order interface control unit 102, a transmission / reception control unit 100, a memory 104 via an address bus 201 and a data bus 202. And the counter control unit 103.
The upper interface control unit 102 controls data transfer with a higher-order information processing device, and uses the address bus 20.
3 and the data bus 204 are connected to the upper information processing device. The transmission / reception control unit 100 performs transmission / reception of serial data to / from a line and parallel / serial conversion, and is connected to the line by a serial data signal line 200.
The memory 104 stores control information, transfer data, and the like under the control of the processor 101. Counter control unit 103
Is reset by the processor 104 every time the debug information is written to the memory 104, and outputs the value of the counter that counts up to the maximum count value.

FIG. 2 is a block diagram showing an example of the configuration of the counter control unit shown in FIG. 1. The counter 300 has a data bus 20 shown in FIG. 1 via an initial value setting data signal line 400.
2 and is connected to the decoder 301 and the data bus 202 shown in FIG. 1 via the count value output signal line 401. The decoder 301 includes a signal line 402 and an inverter 3
02 and the signal line 403, and is connected to the AND gate 303. AND gate 303 counts up signal line 40
4 is connected, and is connected to the counter 300 via the signal line 405.

FIG. 3 is a diagram showing an example of use of the debug information storage area on the memory in FIG. As debug information in the memory 104 shown in FIG. 1, command / response information between the host interface control unit 102 and the host information processing device, control information 1, 2, ... 1, 2,
By writing the count value of the counter control unit 103 every time the writing is performed, it is possible to record the generation interval of the debug information. After writing the count value to the memory 104, the counter 300 is reset. The counter 300 shown in FIG. 2 counts up at regular intervals and stops at the maximum value.

Next, FIG. 4 shows a second embodiment of the communication control device of the present invention.
In the block diagram showing the embodiment, a signal line 600 for supplying a transmission / reception clock to the transmission / reception control unit 100 is connected to the LED 505 in addition to the communication control device of the first embodiment. In the transmission / reception control unit 100, the serial transmission data signal line 602 of the serial transmission / reception data signal line 200 shown in FIG. 1 is connected to the AND gate 501 and the LED 504, and the serial reception data signal line 601 is connected to the line. Fault detection flag register 5 that sets logic "1" when a fault is detected
The setting instruction signal line 605 is connected to the output signal line 06.
06 is ANDed through the inverter 503 and the signal line 608.
It is connected to the gate 501. The output of the switch circuit 500 is output via the interrupt signal line 603 to the processor 1 shown in FIG.
01 is connected. The output of the AND gate 501 is connected to the line via the transmission serial data signal line 604.

When the processor 101 detects a fault or the switch circuit 500 gives an instruction, the processor 101
Sets the failure detection flag register 506 and outputs debug information to the transmission / reception control unit 100. As a result, line output is stopped (space state), and the LED 504 is turned on by the output of debug information. At this time, if a light receiving element is used in the external maintenance device, this debug information can be read.

Next, FIG. 5 shows a third embodiment of the communication control device of the present invention.
In the block diagram showing the embodiment of FIG. 5, in addition to the communication control device of the second embodiment, the output of the clock oscillation circuit 700 is the signal line 8
00, and the output of the clock oscillation circuit 701 is connected to the selector 702 via the signal line 801 and the switch circuit 703 via the signal line 802, and the output is transmitted / received via the signal line 600. 100 and LED 505.

The output of the clock oscillation circuit 700 is usually the clock supplied to the transmission / reception control unit 100, and the output of the clock oscillation circuit 701 is 1 hertz. When the clock from the clock oscillation circuit 701 is selected by the instruction of the switch circuit 703 when outputting the debug information, the debug data output by the LED 504 and the LED 505 can be visually read.

In the block diagrams shown in FIGS. 1, 2, 4 and 5, only the features of the present invention are shown, and circuits and wirings not shown are present. To do.

[0015]

As described above, the communication control device of the present invention stores the control information and the transmission / reception data as well as the occurrence interval thereof, thereby facilitating the analysis of the operation timing and improving the evaluation efficiency. it can. Moreover, since a dedicated external interface control unit, a connector, and the like are not required to output the failure log information, the mounting area can be reduced. Further, by visually reading the failure log information, there is an effect that the failure log information can be collected without an external maintenance device in case of emergency.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a communication control device of the present invention.

FIG. 2 is a block diagram showing a configuration example of a counter control unit in FIG.

FIG. 3 is a diagram showing a usage example of a debug information storage area on the memory in FIG.

FIG. 4 is a block diagram showing a second embodiment of the communication control device of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the communication control device of the present invention.

[Explanation of symbols]

 100 transmission / reception control unit 101 processor 102 upper interface control unit 103 counter control unit 104 memory 300 counter 301 decoder 302, 503 inverter 303, 501 AND gate 500 switch circuit 504, 505 LED (light emitting device) 506 fault detection flag register 700, 701 clock Oscillation circuit 702 Selector 703 Switch circuit

Claims (3)

[Claims] 1. A host interface control section for transferring data to and from an information processing apparatus, a transmission / reception control section connected to a line for controlling transmission / reception such as serial / parallel conversion, and the like.
In a communication control device having a processor and a storage unit that sequentially stores control response information from the information processing device and transmission / reception data to / from the transmission / reception control unit, reset / start to write to the storage unit to the storage unit And a count value storage unit for writing the count value of the counter unit at the same time as writing to the storage unit. 2. A display unit for reading the contents of the storage unit and the count value storage unit and displaying them as serial data via the transmission / reception control unit when a failure is detected, and the serial data output from the line to the display unit. The communication control apparatus according to claim 1, further comprising a first switching unit that switches. 3. The second switching means connected to the transmission / reception control section for switching the serial data transfer rate, and the switching instruction means for instructing the switching by an external operation. Communication control device.