JPH05158734A - Microprocessor - Google Patents

Abstract

PURPOSE:To reduce the quantity of information necessary for tracing an instruction or to prevent the deterioration of performance of a microprocessor by providing a bus control part to input a branch signal and to output the contents of the 1st and 2nd registers to the terminals respectively. CONSTITUTION:An instruction prefetch pert 10 is provided together with an instruction cache part 20, an instruction decoder 30, an address calculation part 40, an instruction executing part 50, a bus interface control pert 60, a branch address register 70, an execution instruction counter 80, a branch address 41, a branch signal 51, an instruction end signal 52, an address bus 61, the bus access information 62, and the instruction execution information 63. The counter 80 inputs both signals 51 and 52 and counts the number of instructions carried out among the branch instructions. Meanwhile, the instruction address of a branch destination is stored in the register 70, and the contents of the counter 80 are outputted to the information 63. Then, the contents of the register 70 are outputted to the bus 61.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for outputting the execution state of a microprocessor to the outside of the microprocessor, and more particularly to a microprocessor incorporating an instruction cache memory device which is one of the techniques for speeding up computer processing. It is about.

[0002]

2. Description of the Related Art In recent years, microprocessors have introduced technologies such as pipeline processing and cache memory devices in order to speed up the processing speed, and increase the development efficiency when developing circuits and programs using the microprocessor. A mechanism for outputting information indicating the execution state of the microprocessor, which is necessary for this purpose, to the outside of the microprocessor is used. When the instruction cache is built-in, if the built-in cache is hit, the instruction execution status is not output to the outside of the microprocessor, and if the microprocessor's address bus and data bus information are only recorded, It is not possible to trace the instruction to be executed.

An example of the conventional microprocessor described above will be described below with reference to the drawings.

FIG. 3 shows the structure of a device for outputting information indicating the execution state of a conventional microprocessor to the outside of the microprocessor. In FIG. 3, 10
Reference numeral 1 is a fetch address register, and 102 is an execution address register, which holds an instruction fetch address and an address of an instruction being executed by the microprocessor. 1
Reference numeral 03 is a bus control unit, 104 is an output bus, 106 is a latch, 107 is a buffer, 125 is an address bus, 127
Is a fetch address strobe signal, and 128 is an execution address strobe signal.

The operation of the microprocessor configured as described above will be described below. First, the microprocessor stores the addresses corresponding to the instruction fetch address register 101 and the execution address register 102 in the fetch cycle and the execution cycle, respectively. When the address is stored in the fetch address register 101, the bus control unit 103 controls to output the content of the fetch address register 101 to the output bus 104, and stores it in the latch 106 and outputs it to the address bus 125 by the buffer 107. .. The bus control unit 103 further indicates that the fetch address strobe signal 127 outputs the fetch address on the address bus 125.

When an address is stored in the execution address register 102, the bus control unit next time when an address is not stored in the fetch address register 101 in that cycle, and when the fetch address is stored in the same cycle in the following cycle. Output the contents of the execution address register 102 in the cycle
4 and outputs it to the latch 106 and outputs it to the address bus 125 by the buffer 107. Further, the execution address strobe 128 indicates that the execution address is output on the address bus 125.
(For example, JP-A-1-154255).

[0007]

However, in the above configuration, when tracing the execution instructions of the microprocessor based on the information output by the microprocessor, the addresses of all the instructions executed by the microprocessor are recorded. However, there is a problem in that a storage device having a large capacity is required. Further, as the microprocessor speeds up, the execution information of the microprocessor is always output to the outside of the processor, which causes bus contention and reduces the performance of the microprocessor. Furthermore, there is a method of outputting the execution information of the microprocessor only when tracing the instructions executed by the microprocessor, but the execution environment when tracing is different from that when it is not, and accurate information can be obtained. Have difficulty.

In view of the above problems, the present invention provides an execution trace of a microprocessor which does not require a large storage device and which suppresses deterioration of the performance of the microprocessor when tracing an instruction executed by the microprocessor. It is an object to provide a microprocessor that can perform.

[0009]

In order to solve the above problems, a microprocessor according to the present invention uses an instruction end signal indicating the end of instruction execution and a branch condition is satisfied when a branch instruction is executed, or unconditionally. A branch signal indicating that a branch is to be performed, an instruction execution counter that inputs the instruction end signal, counts the number of executed instructions, and resets the contents by inputting the branch signal, and an instruction execution number from the instruction execution counter. A first register for inputting and holding, an address calculating unit for calculating and outputting an address of a branch destination instruction, a second register for inputting and holding a branch destination address output by the address calculating unit, and the branch signal And a bus controller for inputting the contents of the first and second registers to the respective terminals.

Further, the address of the branch destination instruction to be calculated is provided with an indirect branch signal which is output only when referring to the contents of the memory or the register.

[0011]

With the above-described structure, the present invention outputs the number of executed instructions and the address of the branch destination instruction each time the microprocessor executes a branch instruction while using the cache. Since the start address of the instruction trace is known, the execution trace of the microprocessor can be performed from the instruction string on the memory when the branch instruction is not executed. When the microprocessor executes the branch instruction, the branch destination is indicated by the microprocessor. Therefore, in order to execute the execution trace of the instruction, the instruction that has branched can be determined by the start address of the trace or the address of the branch destination of the branch instruction and the number of instructions that have finished executing. Therefore, the instruction tracing device provided outside the microprocessor determines the address of the instruction at the branch destination and the number of instructions executed until branching to the address when the microprocessor performs a branch. You can keep it as.
Therefore, the trace can be efficiently performed using the storage device having a small capacity. Further, since the execution information of the microprocessor is output using the address bus only when branching by the branch instruction, the deterioration of the performance of the microprocessor is reduced.

Further, by providing an indirect branch signal for outputting the address of the branch destination instruction only when referring to the contents of the memory or the register, only when the address of the branch destination instruction cannot be determined from the instruction on the memory. It becomes possible to output the address of the branch destination instruction. That is, when the branch destination branched by the branch instruction is indicated by absolute addressing or the like, the execution trace can be performed from the instruction sequence on the memory, and the instruction of the branch destination can be executed only when the branch destination is indicated by the register or the data on the memory. Address and the number of instructions executed up to the execution of that branch instruction are output as execution information. If the branch destination instruction address is determined in another addressing mode, the number of instructions executed up to that branch instruction. By outputting only, the influence on the execution environment of the microprocessor is suppressed, the deterioration in performance is reduced, and further, the information required for instruction tracing is further reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A microprocessor according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the configuration of a microprocessor according to an embodiment of the present invention. In FIG. 1, 1
0 is an instruction prefetch unit, 20 is an instruction cache, 30
Is an instruction decoder, 40 is an address calculation unit, 50 is an instruction execution unit, 60 is a bus interface control unit, 70 is a branch address register, 80 is an execution instruction counter, 41 is a branch address, 51 is a branch signal, and 52 is an instruction end. Signal, 6
Reference numeral 1 is an address bus, 62 is bus access information, and 63 is instruction execution information.

The operation of the microprocessor configured as described above will be described below with reference to FIG.
Instruction cache 2 by cache enable signal 12
If the use of 0 is permitted, the instruction prefetch unit 1
At 0, the address of the instruction to be executed in the next cycle is calculated (when no branch occurs), the instruction in the instruction cache 10 is read, and the read instruction is decoded by the instruction decoder 30. The instruction executing section 50 executes the instruction based on the decoding result of the instruction decoder 30. The instruction execution unit 50 outputs the instruction execution end signal 52 in the cycle in which the execution of the instruction instructed by the instruction decoder 30 ends. Furthermore, the instruction execution counter 80 increments the content by one each time the instruction execution end signal 52 is output, and counts the number of instructions that have been executed in the instruction execution unit 50. Although not shown in FIG. 1, the instruction execution counter 80 is reset to 0 at the same time when the microprocessor is reset.

When the instruction decoded by the instruction decoder 30 matches a branch instruction, the instruction executing section 50 obtains the address of the branch destination instruction in the address calculating section 40, outputs the result to the branch address bus 41, and branches. A branch instruction signal 51 is output to indicate that the condition is satisfied or the branch is unconditionally performed. Bus control unit 6
0 captures and stores the branch address each time the branch address is output to the branch destination address bus 41 to the branch address register 70 in the unit. Further, the instruction prefetch unit 10 fetches the branch destination address from the branch address bus 41 and searches whether or not the branch destination instruction is stored in the instruction cache 20. Further, when the branch signal 51 is output, the instruction execution counter 80 outputs the content held in the counter to the latch 85 and clears the content of the counter to zero. When the cache enable signal 12 is output, the bus control unit 60 outputs the branch address register 7 every time the branch instruction signal 51 is output.
The content of 0 is selected by the selector 65 and the address bus 61 is selected.
And the branch address is output on the address bus 61 by the bus access information 62. Further, the bus control unit simultaneously outputs the contents of the latch 85 to the instruction execution information 63.

Although not shown in the figure, the address bus 61, the bus access information 62, and the instruction execution information 63 are traced by a device for tracing the execution status connected to the present microprocessor. Depending on the information, the information about the branch instruction is sent to the address bus 61.
And only when the output is confirmed in the instruction execution information 63, the trace device stores those contents. Address bus 6
From 1 and the instruction execution information 63, the address of the branch destination instruction can be obtained, and the number of executed instructions can be confirmed from the address of the previous branch instruction. Therefore, the instruction trace is the instruction execution information 6 that continues from the previous branch instruction on the memory.
The number of instructions indicated by 3 can be obtained by a disassembler or the like.

As described above, according to the present embodiment, the instruction end signal 52 for indicating the end of the execution of the instruction, the branch signal 51 for performing the branch when the branch instruction is executed, and the instruction end signal are input. The instruction execution counter 80 that counts the number of executed instructions and resets the contents by inputting the branch signal, the latch 85 that is input and held by the instruction execution counter, and the branch destination address output by the address calculator 40 By providing a register 70 for inputting and holding 41 and an address bus 61, bus access information 62 and instruction execution information 63 as terminals, a lot of information can be stored outside the processor even when the instruction trace is used in the instruction cache. The trace of the instruction executed by the microprocessor can be performed without holding.

A second embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a microprocessor showing a second embodiment of the present invention. 10 is an instruction prefetch unit, 20 is an instruction cache, 30 is an instruction decoder, 40 is an address calculation unit, 50 is an instruction execution unit, 60
Is a bus interface control unit, and 70 is a branch address register. The above is the same as the configuration of FIG. The difference from FIG. 1 is that an indirect branch signal 53 is provided.

The operation of the microprocessor configured as described above will be described below. Instruction execution unit 5
The indirect branch signal 53 is output when the address of the instruction to branch to in the branch instruction executed at 0 is determined by using the value in the register or the memory. The indirect branch signal 53 is not output when it is specified by the address of the branch instruction and the displacement information, that is, the deviation in the branch instruction. The bus control unit 60 outputs the address of the branch destination instruction to the address bus 61 only when the branch instruction signal 51 and the indirect branch signal 53 are output, and further, the bus access information 62 and the instruction execution information 6
3 is output. When the indirect branch signal 53 is not output and only the branch instruction signal 51 is output, the bus control unit 60
Only the instruction execution information 63 is output. That is, when an indirect branch instruction is executed, the address and the bus access information branching by the execution of the instruction are output together with the instruction execution information, that is, the number of instructions executed from the previous branch to the current branch,
When the branch destination is determined by another method and the branch is executed, only the instruction execution information is output.

As described above, by providing the indirect branch signal 53 output when the indirect branch instruction is executed, the information recorded when tracing the instruction executed by the microprocessor can be reduced and the branch address can be reduced. Can be output to the address bus less frequently, and the influence on the execution environment and performance of the microprocessor can be reduced.

[0022]

As described above, according to the present invention, the cache valid signal for validating the use of the cache, the instruction end signal for indicating the end of the execution of the instruction, and the branch signal for indicating the branch at the execution of the branch instruction are provided. And an instruction execution counter that counts the number of executed instructions by counting up the contents held each time the instruction end signal is input and resets the contents by inputting the branch signal. A first register for inputting and holding the number of execution instructions from the instruction execution counter; an address calculation unit for calculating and outputting the address of the branch destination instruction; and a branch destination address output by the address calculation unit. A second register that holds the bus, and a bus control unit that inputs the cache valid signal and the branch signal and outputs the contents of the first and second registers, respectively. By kicking it, it is possible to trace instructions executed in the microprocessor by a storage device smaller volume without providing a large tracing device external to the microprocessor.

By providing an indirect branch signal that is output when an indirect branch instruction is executed, the number of times the branch destination address is output can be reduced, which further affects the execution environment of the microprocessor and lowers the performance. The instruction executed by the microprocessor can be traced without incurring.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a microprocessor according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a microprocessor according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a device that outputs information indicating the execution state of a conventional microprocessor to the outside of the microprocessor.

[Explanation of symbols]

 10 instruction prefetch unit 20 instruction cache 30 instruction recorder 40 address calculation unit 50 instruction execution unit 60 bus control unit 70 branch address register 80 instruction execution counter

Claims (2)

[Claims] 1. A cache for instructions, a cache valid signal for validating the use of the cache, and an instruction end signal for indicating the end of an instruction in a cycle in which the instruction is input, decoded and executed, and the execution of the instruction ends. And an execution unit that outputs a branch signal indicating that a branch is to be executed when the branch instruction is executed, and the number of executed instructions is counted by counting up the content held each time the instruction end signal is input. An instruction execution counter that resets the contents by inputting a branch signal, a first register that inputs and holds the number of executed instructions from the instruction execution counter, and an address calculation unit that calculates and outputs the address of the branch destination instruction A second register for inputting and holding a branch destination address output from the address calculator, the cache valid signal, and A microprocessor comprising a bus control unit which inputs a branch signal and outputs the contents of the first and second registers to terminals. 2. A cache for instructions, a cache valid signal that enables the use of the cache, and an instruction end signal that indicates the end of the instruction in the cycle in which the instruction is input, decoded and executed, and the execution of the instruction ends. And a branch signal indicating that a branch is to be executed when the branch instruction is executed, and an instruction that outputs an indirect branch signal only when the address of the branch destination instruction calculated by the address calculator is determined based on the contents of the memory or register. An execution unit; an instruction execution counter for counting the number of executed instructions by counting up the content held each time the instruction end signal is input and resetting the content by inputting the branch signal; Calculates the first register that holds the number of executed instructions from the instruction execution counter and the address of the branch destination instruction An address calculator that outputs, a second register that inputs and holds a branch destination address that the address calculator outputs, and a case where the indirect branch signal is input and the indirect branch signal and the branch signal are input. A bus controller that outputs the contents of the first and second registers and outputs only the contents of the first register when only the branch signal is input.