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JPH0515453U - SOI substrate - Google Patents

SOI substrate

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Publication number
JPH0515453U
JPH0515453U JP6158791U JP6158791U JPH0515453U JP H0515453 U JPH0515453 U JP H0515453U JP 6158791 U JP6158791 U JP 6158791U JP 6158791 U JP6158791 U JP 6158791U JP H0515453 U JPH0515453 U JP H0515453U
Authority
JP
Japan
Prior art keywords
bonding
soi substrate
refractory metal
wafer
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6158791U
Other languages
Japanese (ja)
Inventor
秀俊 上原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP6158791U priority Critical patent/JPH0515453U/en
Publication of JPH0515453U publication Critical patent/JPH0515453U/en
Withdrawn legal-status Critical Current

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Abstract

(57)【要約】 【目的】 接合により発生する応力緩和および素子特性
を向上できるSOI基板を実現する。 【構成】 2枚のSiウェハを直接接合して形成される
SOI基板において、接合面となる一方の面に高融点金
属または高融点金属シリサイトが形成された前記第1の
Siウエハと、接合面となる一方の面にSiO2 を形成
後、このSiO2の上層に前記高融点金属が形成された
前記第2のSiウェハとを、前記接合面同志を800℃
以上の熱処理により一体化接合して形成したことを特徴
とする。
(57) [Abstract] [Purpose] To realize an SOI substrate capable of improving stress relaxation and device characteristics caused by bonding. In an SOI substrate formed by directly joining two Si wafers, the first Si wafer having a refractory metal or refractory metal silisite formed on one surface serving as a bonding surface is bonded to the first Si wafer. After forming SiO2 on one of the surfaces, the second Si wafer having the refractory metal formed on the upper layer of SiO2 and the bonding surface at 800.degree.
It is characterized by being integrally joined by the above heat treatment.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、2枚のSiウェハを直接接合して形成されるSOI(Silicon On I nsulator)基板に関し、特に接合時に発生する応力を緩和させるものである。 The present invention relates to an SOI (Silicon On Insulator) substrate formed by directly bonding two Si wafers, and in particular, relaxes stress generated during bonding.

【0002】[0002]

【従来の技術】[Prior Art]

2枚のSiウェハを直接接合して形成されるSOI基板として、従来、2枚の SiウェハをSiO2 を介して直接接合することにより行われており、例えば、 接合時の条件として、1000℃,30分のアニ−ルにより接合が行われる。 As an SOI substrate formed by directly bonding two Si wafers, conventionally, two Si wafers are directly bonded via SiO2. For example, as a bonding condition, 1000 ° C, Joining is performed by annealing for 30 minutes.

【0003】 しかし、このような接合では、高温での熱処理を施す際、SiとSiO2 の熱 膨脹の差により、応力が発生するため、Siウェハの反りを招いたり、素子の特 性に悪影響をもたらすなどの課題があった。However, in such bonding, stress is generated due to the difference in thermal expansion between Si and SiO 2 when heat treatment is performed at a high temperature, which causes warpage of the Si wafer and adversely affects the characteristics of the element. There were issues such as bringing.

【0004】[0004]

【考案が解決しようとする課題】[Problems to be solved by the device]

本考案は、上記従来技術の課題を踏まえてなされたものであり、直接接合SO I基板に関し、SiとSiO2 の界面にシリサイトの中間層を形成することによ り、SiとSiO2 の熱膨脹の差により発生する応力を緩和し、素子の特性を向 上できるSOI基板を提供することを目的としたものである。 The present invention has been made in view of the above problems of the prior art, and relates to a direct-bonded SOI substrate, by forming an intermediate layer of silisite at the interface between Si and SiO2, the thermal expansion of Si and SiO2 is prevented. The purpose of the present invention is to provide an SOI substrate capable of relaxing the stress generated by the difference and improving the characteristics of the device.

【0005】[0005]

【課題を解決するための手段】[Means for Solving the Problems]

上記課題を解決するための本考案の構成は、2枚のSiウェハを直接接合して 形成されるSOI基板において、 接合面となる一方の面に高融点金属または高融点金属シリサイトが形成された 前記第1のSiウエハと、 接合面となる一方の面にSiO2 を形成後、このSiO2 の上層に前記高融点 金属が形成された前記第2のSiウェハとを、 前記接合面同志を800℃以上の熱処理により一体化接合して形成したことを 特徴とするものである。 In the structure of the present invention for solving the above-mentioned problems, in an SOI substrate formed by directly bonding two Si wafers, a refractory metal or refractory metal silicite is formed on one surface to be a bonding surface. The first Si wafer and the second Si wafer having the refractory metal formed on the upper surface of the SiO2 after forming SiO2 on one surface to be the bonding surface, It is characterized by being integrally joined by heat treatment at a temperature of ℃ or more.

【0006】[0006]

【作用】[Action]

本考案によれば、SiとSiO2 の界面にシリサイトの中間層を形成したSO I基板の構造としている。したがって、このシリサイトの中間層により、Siと SiO2 の熱膨脹の差により発生する応力を緩和できると共に、バルクSiと同 程度の接合力を有する。 According to the present invention, the structure of the SOI substrate has an intermediate layer of silicite formed at the interface between Si and SiO2. Therefore, the intermediate layer of silisite can alleviate the stress generated by the difference in thermal expansion between Si and SiO2, and has a bonding force similar to that of bulk Si.

【0007】[0007]

【実施例】【Example】

以下、本考案を図面に基づいて説明する。 図1(イ)〜(ニ)は本考案のSOI基板の製作工程および断面構造を示す図 である。図1において、(イ)図に示すように、第1のSi基板は、Siウェハ 1aの接合面となる片側面に、Ta(タンタル)やMo(モリブデン)やW(タ ングステン)などの高融点金属2aが、例えば、厚さが0.1μm程度に形成さ れている。この第1のSi基板をシリサイト化のために、800℃〜1000℃ 程度の温度で、N2 雰囲気中でアニ−ルを行い、Siウェハ1a表面に高融点金 属シリサイト3を形成する。また、(ロ)図に示すように、第2のSi基板は、 Siウェハ1bの接合面となる片側面に、素子を誘電体分離し絶縁するためのS iO2 4を厚さ約1〜数μm程度に形成した後、そのSiO2 4上に、第1のS i基板の高融点金属2aと同種のTa(タンタル)やMo(モリブデン)やW( タングステン)などの高融点金属2bが、例えば厚さが0.1μm程度に形成さ れている。この(イ)図および(ロ)図に示す第1,第2のSi基板を、(ハ) 図に示すように、高融点金属シリサイト3側(第1のSi基板)と高融点金属2 b側(第2のSi基板)とを接触させて、重ね合わせ、約800〜1000℃で 、数十秒から数十分間、熱処理して接合する。 Hereinafter, the present invention will be described with reference to the drawings. 1A to 1D are views showing a manufacturing process and a sectional structure of an SOI substrate of the present invention. In FIG. 1, as shown in FIG. 1A, the first Si substrate has a high surface such as Ta (tantalum), Mo (molybdenum), or W (tungsten) on one side that is a bonding surface of the Si wafer 1a. The melting point metal 2a is formed to have a thickness of, for example, about 0.1 μm. The first Si substrate is annealed in a N2 atmosphere at a temperature of about 800 DEG C. to 1000 DEG C. to form silicite to form a high melting point metal silicite 3 on the surface of the Si wafer 1a. Further, as shown in (b), the second Si substrate has a thickness of about 1 to several layers of SiO 2 4 for dielectric isolation and insulation of the element on one side surface which is a bonding surface of the Si wafer 1b. After being formed to a thickness of about μm, a refractory metal 2b such as Ta (tantalum), Mo (molybdenum) or W (tungsten) similar to the refractory metal 2a of the first Si substrate is formed on the SiO2 4, for example. The thickness is about 0.1 μm. As shown in (c), the refractory metal silicite 3 side (first Si substrate) and the refractory metal 2 are replaced by the refractory metal 2 and the first and second Si substrates shown in (a) and (b). The b-side (second Si substrate) is brought into contact with each other, and they are superposed and heat-treated at about 800 to 1000 ° C. for several tens of seconds to several tens of minutes to bond them.

【0008】 ここで、(ニ)図に示すように、熱処理接合後のSiウェハ1a,1bの界面 は、SiO2 4とSiウェハ1aの間に高融点金属シリサイト層3とSi−M( 高融点金属)−Oによる中間層5を形成している。したがって、Siウェハ1a からSiウェハ1bまで、接合界面では、連続的に成分が分布された中間層とな っている。Here, as shown in FIG. 2D, the interface between the Si wafers 1 a and 1 b after the heat treatment bonding has a high melting point metal silicite layer 3 and a Si-M (high The intermediate layer 5 made of (melting point metal) -O is formed. Therefore, from the Si wafer 1a to the Si wafer 1b, the bonding interface forms an intermediate layer in which components are continuously distributed.

【0009】 このように、図1(ニ)に示す中間層3,5により、バルクSiと同程度の接 着力を有し、熱膨脹の違いにより発生する応力を緩和することができると共に、 高融点金属シリサイト層3を有し、この高融点金属シリサイト層3の抵抗率は1 0-4Ωcm以下であり、寄生容量低下、デバイス高速化が可能となる埋め込み層を 有するSOI基板の構造を形成できる。As described above, the intermediate layers 3 and 5 shown in FIG. 1D have the same adhesive force as that of bulk Si, can alleviate the stress generated by the difference in thermal expansion, and have a high melting point. The structure of the SOI substrate having the metal silicite layer 3 and the resistivity of the refractory metal silicite layer 3 is 10 −4 Ωcm or less, and having the buried layer capable of reducing the parasitic capacitance and speeding up the device. Can be formed.

【0010】[0010]

【考案の効果】[Effect of the device]

以上、実施例と共に具体的に説明したように、本考案によれば、SiとSiO 2 の界面にシリサイトの中間層を形成したSOI基板の構造としている。したが って、このシリサイトの中間層により、SiとSiO2 の熱膨脹の差により発生 する応力を緩和できると共に、寄生容量低下やデバイス高速化などの素子特性も 向上できるSOI基板を実現できる。 As described above in detail with the embodiments, the present invention has the structure of the SOI substrate in which the intermediate layer of silicite is formed at the interface between Si and SiO 2. Therefore, the intermediate layer of silicite can realize the SOI substrate which can alleviate the stress generated by the difference in thermal expansion between Si and SiO2 and improve the element characteristics such as the parasitic capacitance reduction and the device speedup.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案のSOI基板の製作工程及び断面構造を
示す図である。
FIG. 1 is a view showing a manufacturing process and a sectional structure of an SOI substrate of the present invention.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 2枚のSiウェハを直接接合して形成さ
れるSOI基板において、 接合面となる一方の面に高融点金属または高融点金属シ
リサイトが形成された前記第1のSiウエハと、 接合面となる一方の面にSiO2 を形成後、このSiO
2 の上層に前記高融点金属が形成された前記第2のSi
ウェハとを、 前記接合面同志を800℃以上の熱処理により一体化接
合して形成したことを特徴とするSOI基板。
1. An SOI substrate formed by directly bonding two Si wafers together with the first Si wafer having a refractory metal or refractory metal silicite formed on one surface to be a bonding surface. , SiO2 is formed on one surface to be the bonding surface,
2 above the second Si having the refractory metal formed on it.
An SOI substrate, which is formed by integrally bonding a wafer and the bonding surface by heat treatment at 800 ° C. or higher.
JP6158791U 1991-08-05 1991-08-05 SOI substrate Withdrawn JPH0515453U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6158791U JPH0515453U (en) 1991-08-05 1991-08-05 SOI substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6158791U JPH0515453U (en) 1991-08-05 1991-08-05 SOI substrate

Publications (1)

Publication Number Publication Date
JPH0515453U true JPH0515453U (en) 1993-02-26

Family

ID=13175432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6158791U Withdrawn JPH0515453U (en) 1991-08-05 1991-08-05 SOI substrate

Country Status (1)

Country Link
JP (1) JPH0515453U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52163746U (en) * 1976-06-04 1977-12-12
JPS5412498A (en) * 1977-06-16 1979-01-30 Sloan Valve Co Adaptor for circuit breaker
JP2004512683A (en) * 2000-10-19 2004-04-22 インターナショナル・ビジネス・マシーンズ・コーポレーション Layer migration of low defect SiGe using etch back method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52163746U (en) * 1976-06-04 1977-12-12
JPS5412498A (en) * 1977-06-16 1979-01-30 Sloan Valve Co Adaptor for circuit breaker
JP2004512683A (en) * 2000-10-19 2004-04-22 インターナショナル・ビジネス・マシーンズ・コーポレーション Layer migration of low defect SiGe using etch back method

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19951102