JPH05153633A - A/d converter - Google Patents

Abstract

PURPOSE:To output a digital composite signal in compliance with the D-2 format at all times even when the valve of an electric component is subject to change due to the change of temperature or a power supply or the like. CONSTITUTION:A VCO 11 generates a sampling clock having a frequency being a multiple of (m) of a frequency of a subcarrier. An A/D converter 3 uses the sampling clock to convert an analog composite signal into a digital composite signal. A BPF 13 extracts an input subcarrier from the digital composite signal. A local oscillator 12 generates a local subcarrier. A multiplier 14 multiplies the two subcarriers. An averaging (I) circuit 15 averages consecutive mn-sets of the products, and an averaging (II) circuit 16 averages further the averaged values by plural lines. A pulse generator 17 generates a pulse signal whose width is corresponding to the averaged value. An integration device 18 integrates the pulse signal to control a VCO 11 based on the integration value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter for converting an analog composite video signal into a digital composite video signal.

[0002]

2. Description of the Related Art A conventional analog / digital converter (hereinafter referred to as A /) which converts a so-called analog composite video signal (hereinafter referred to as composite signal) into a digital composite signal.
As shown in FIG. 6, the D converter is based on an amplifier 31 that amplifies the composite signal, and a subcarrier (hereinafter referred to as a subcarrier) superimposed on the composite signal from the amplifier 31 as a color burst signal. ,
For example, a clock generation circuit 32 that generates a sampling clock having a frequency four times that of the subcarrier (hereinafter referred to as 4f _SC ), and an A / D conversion that converts the composite signal into a digital composite signal by the sampling clock from the clock generation circuit 32 And the container 33.

By the way, as the format of the digital composite signal, for example, in the case of the so-called NTSC system, the so-called D-2 format is known. Here, the D-2 format will be briefly described.

The D-2 format is the so-called ANSI S
MPTE (American Standard / Movie Television Technology Association Standard) 244
The sampling frequency is 4f _SC and the quantization is linear 8-bit quantization (10-bit for the color burst part).
The sampling phase is the IQ axis in order to correctly limit the band of the color signal (so-called IQ signal).

Therefore, the clock generating circuit 32 is
Is composed of, for example, a so-called PLL (Phase Locked Loop), and is adapted to generate a sampling clock based on a subcarrier superimposed as a color burst signal on a supplied composite signal. Specifically, the frequency is 4f _SC and the phase is 123 degrees with respect to the subcarriers. That is, the clock generating circuit 32 configured by the PLL is adjusted sufficiently at the time of manufacture so as to generate the sampling clock which meets the above conditions, and is shipped.

[0006]

By the way, even if the adjustment is sufficiently made at the time of manufacturing as described above, the set phase is changed due to, for example, the temperature characteristics of the electric components constituting the PLL, aging, or fluctuations in the power supply voltage. Fluctuates and this A /
There is a problem that the digital composite signal output from the D converter does not conform to the standard. In addition, the above adjustment required man-hours.

The present invention has been made in view of the above circumstances, and provides an analog / digital conversion device which can be stably operated with respect to fluctuations in temperature, power supply voltage and the like and can be adjusted. With the goal.

[0008]

In order to solve the above-mentioned problems, the present invention provides a voltage-controlled oscillation means for generating a sampling clock m times the sub-carrier frequency, and an analog by means of the sampling clock from the voltage-controlled oscillation means. An analog / digital converting means for converting the composite video signal into a digital composite video signal and outputting the composite video signal, an extracting means for extracting a color burst signal from the digital composite video signal from the analog / digital converting means, and the voltage control oscillating means. Local oscillation means for generating a subcarrier on the basis of the sampling clock, multiplication means for multiplying the subcarrier from the local oscillation means by the color burst signal from the extraction means, and the multiplication values from the multiplication means are continuous. averaging means for averaging mn pieces, and an average value from the averaging means into an analog signal And conversion, characterized in that it comprises a digital / analog converting means for controlling the oscillation frequency and phase of the voltage controlled oscillation means on the basis of the average value is converted into the analog signal.

Further, the digital / analog converting means integrates the pulse signal generating means for generating a pulse signal having a width corresponding to the average value from the averaging means, and the pulse signal from the pulse signal generating means, And an integrating means for supplying the integrated value to the voltage controlled oscillating means.

Further, the local oscillating means counts the sampling clock from the voltage controlled oscillating means, and the multiplying means uses the level value of a predetermined phase of the subcarrier based on the count value from the counting means. It is characterized by comprising a storage means for supplying.

Further, the average value from the averaging means is averaged over at least two lines to obtain the digital / digital value.
A line averaging means for supplying to the analog converting means is provided.

[0012]

In the analog / digital converter according to the present invention, the voltage-controlled oscillator means generates a sampling clock m times the subcarrier frequency, and the analog / digital converter means converts the analog composite video signal into a digital composite video signal. Convert to a signal and output. Then, at this time, the extracting means extracts the color burst signal from the digital composite video signal, the local oscillating means generates a subcarrier based on the sampling clock, and the multiplying means multiplies the subcarrier and the color burst signal to obtain an average. The averaging means averages consecutive mn multiplication values, and the digital / analog converting means converts the average value into an analog signal.
The oscillation frequency and the phase of the voltage controlled oscillation means are controlled based on the average value converted into the analog signal.

Further, the pulse signal generating means generates a pulse signal having a width corresponding to the average value from the averaging means, the integrating means integrates the pulse signal, and the oscillation of the voltage controlled oscillating means based on the integrated value. Control frequency and phase.

Further, the counting means counts the sampling clock from the voltage controlled oscillating means, and based on this count value, the level value of the predetermined phase of the subcarrier is calculated.
It is read from the storage means and supplied to the multiplication means.

The line averaging means averages the average value from the averaging means over at least two lines and supplies the averaged value to the digital / analog converting means.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an analog / digital converter according to the present invention will be described below with reference to the drawings.

In this embodiment, the present invention is applied to an analog / digital conversion device for converting a so-called analog composite video signal into a digital composite video signal conforming to a predetermined standard, for example, the so-called NTSC system D-2 format. This analog / digital conversion device (hereinafter referred to as A / D conversion device) is, for example, as shown in FIG. 1, an amplifier 2 for amplifying an analog composite video signal (hereinafter referred to as composite signal), and an amplifier 2 from the amplifier 2. A / to convert composite signal to digital composite signal
The D converter 3 and a clock generation circuit 10 which forms a sampling clock based on the digital composite signal from the A / D converter 3 and supplies the sampling clock to the A / D converter 3.
It consists of and.

The A / D converter converts the composite signal supplied through the terminal 1 into a digital composite signal conforming to the D-2 format, and outputs the digital composite signal through the terminal 4. ..

The clock generation circuit 10 is the same as that shown in FIG.
As shown in FIG. 2, a voltage controlled oscillator (hereinafter, VCO: Voltage Controlled Osc) that generates a sampling clock having a frequency m times that of a so-called subcarrier (hereinafter, referred to as subcarrier).
illator) 11, a local oscillator 12 that generates a subcarrier (hereinafter referred to as a local subcarrier) based on a sampling clock from the VCO 11, and the above A /
A bandpass filter (hereinafter referred to as BPF) 13 that extracts a subcarrier (hereinafter referred to as an input subcarrier) superimposed as a so-called color burst signal from the digital composite signal from the D converter 3, and an input subcarrier from the BPF 13. A multiplier 14 for multiplying the local subcarriers from the VCO 11 and an averaging (I) circuit 1 for averaging consecutive mn multiplication values from the multiplier 14.
5 and an averaging (II) circuit 16 for averaging the average value from the averaging (I) circuit 15 over at least two lines,
A pulse generator 17 for generating a pulse signal having a width corresponding to an average value of a plurality of lines from the averaging (II) circuit 16 and a pulse signal from the pulse generator 17 are integrated, and based on the integrated value And an integrator 18 for controlling the oscillation frequency and phase of the VCO 11.

That is, the clock generation circuit 10
It has a kind of PLL (Phase Locked Loop) structure, and the frequency is m times, for example, 4 times (hereinafter 4f) with respect to the input subcarrier superimposed on the digital composite signal converted into the digital signal as the color burst signal. _{(Referred to as SC} ) so that the phase is locked to 123 degrees, and a sampling clock having a frequency of 4f _SC and a phase of 123 degrees is generated for the input subcarrier.

Specifically, the BPF 13 gates the color burst signal of the digital composite signal from the A / D converter 3 to extract an input subcarrier,
This input subcarrier is supplied to the multiplier 14.

The multiplier 14 multiplies this input subcarrier by the local subcarrier from the local oscillator 12, and supplies the obtained multiplication value to the averaging (I) circuit 15.

The averaging (I) circuit 15 has mn consecutive multiplication values, that is, 4 (m = 4, n = 1) and 8 (m = 4, n) that are consecutive within one color burst period. =
2) Average the ... For example, when the phase difference between the input subcarrier and the local subcarrier is 0 degree, the output of the averaging (I) circuit 15 is 0. Specifically, when averaging, for example, four consecutive multiplication values, the value obtained by adding the remaining two is subtracted from the value obtained by adding the two consecutive values, and the values are averaged.

The averaging (II) circuit 16 is the averaging (I) circuit 1
The average value from 5 is further at least 2 so that the response speed of this PLL does not become too fast and operates stably.
Average over lines, ie multiple lines.

The pulse generator 17 includes an averaging (II) circuit 16
The pulse signal having a width corresponding to the average value of a plurality of lines from is generated and supplied to the integrator 18.

The integrator 18 integrates this pulse signal,
The oscillation frequency and phase of the VCO 11 are controlled based on the integrated value.

Specifically, the integrator 18 includes, as shown in FIG. 2, for example, a resistor 18a and a capacitor 18b which form an integrator circuit, and a switch 18c which connects the resistor 18a to a power source having a positive voltage. , A switch 18d for connecting the resistor 18a to a power supply having a negative voltage,
The pulse generator 17 generates a pulse signal having a width proportional to the average value of a plurality of lines from the averaging (II) circuit 16, and switches the switch 18c with a pulse signal corresponding to the positive polarity depending on the polarity of the average value. Control is performed by turning on the switch 18c with a pulse signal corresponding to the negative polarity. As a result, the capacitor 18c is positively charged for a time corresponding to the pulse width of the pulse signal corresponding to the positive polarity or the pulse signal corresponding to the negative polarity with a time constant determined by the capacitance value and the resistance value of the resistor 18a. It is charged negatively for a time corresponding to the pulse width. Therefore, the output of the integrator 18 becomes 0 when the phase difference between the input subcarrier and the local subcarrier is 0 degree, and when the phase difference is other than 0 degree, a value corresponding to the phase difference is output. That is, the pulse generator 17 and the integrator 18 operate as a D / A converter that converts the average value of a plurality of lines from the averaging (II) circuit 16 into an analog signal, and obtain it as described above. The oscillation frequency and phase of the VCO 11 are controlled by the integrated value obtained.

The VCO 11 supplies a sampling clock whose frequency and phase are controlled to the A / D converter 3 and the local oscillator 12 to the pulse generator 17.

The local oscillator 12 divides this sampling clock into 1/4 and delays the signal obtained by the division by, for example, 327 (= 360-33) degrees, that is, a phase of 33 degrees with respect to the sampling clock. Generate local subcarriers. Specifically, "sin33
° "," sin123 ° "," sin213 ° "," s
In 213 ° ”and“ sin 303 ° ”cyclically output sample values in synchronization with the sampling clock.

Thus, in the clock generating circuit 10 having the PLL structure, the sampling clock from the VCO 11 is applied to the input subcarrier superimposed on the digital composite signal converted into the digital signal by the A / D converter 3. The frequency is 4f _SC and the phase is 123
It is locked when it is delayed once, and the sampling clock in this locked state is supplied to the A / D converter 3.

On the other hand, the A / D converter 3 converts the composite signal supplied through the terminal 1 into a digital composite signal based on the sampling clock, and outputs the digital composite signal through the terminal 4.

That is, the A / D configured as described above
The converter converts the composite signal from the terminal 1 into a digital composite signal based on a sampling clock having a frequency four times that of the input subcarrier superimposed as a color burst signal and having a phase delayed by 123 degrees, and outputs the digital composite signal. To do. In other words, the A / D converter is D
Output a digital composite signal conforming to the -2 format.

At this time, in this A / D converter, since the frequency and phase of the sampling clock are obtained from the digital composite signal converted by the A / D converter 3, for example, the clock generation circuit 10 is used. Even if the values of the constituent electrical components change due to temperature characteristics, aging, etc., or if the power supply voltage changes, a field back is applied so that these changes do not appear in the frequency and phase of the sampling clock. A / D
It is possible to always generate and output a digital composite signal conforming to the D-2 format without the phase fluctuation of the sampling clock caused by the fluctuation of the temperature and the power supply voltage as in the converter. Further, by performing the field back control in this way, the A / D conversion device can be adjusted. Also, averaging as described above
(II) By averaging the average value AV in a plurality of lines in the circuit 16, so-called jitter of the sampling clock formed can be suppressed.

Further, since the phase of the sampling clock can be easily changed by changing the delay amount in the local oscillator 12, for example, the so-called SCH (Sub Carrie) is used.
r toHorizontal sync) Even when an analog composite signal whose phase is not 0 degrees is input, a digital composite signal conforming to the D-2 format can be output.

Furthermore, since the sampling clock is obtained by digital signal processing, this A /
The D conversion device can be a so-called 1-chip IC, and the power consumption can be reduced as compared with the conventional device.

By the way, in the above-mentioned embodiment, since the local subcarrier whose phase matches the input subcarrier is generated and the input subcarrier is multiplied by this local subcarrier by the multiplier 4, the averaging (I In the circuit 15, it is necessary to perform addition and subtraction based on the polarity of the input subcarrier, as described above, in order to obtain the mn average value of consecutive multiplication values. Therefore, the local subcarrier from the local oscillator 12 may have its phase advanced by 33 degrees with respect to the sampling clock so that the averaging (I) circuit 15 can be configured by a simple adding circuit.

Specifically, as shown in FIG. 3, for example, the local oscillator 12 stores a counter 12a for counting the sampling clock from the VCO 11, a level value of a predetermined phase of the local subcarrier, and the counter. And a memory 12b for outputting the level value based on the count value from 12a.

The counter 12a is composed of, for example, a 2-bit (quaternary) counter, counts a sampling clock (shown in FIG. 4d), for example, as shown in FIGS. 4e and 4f, and outputs 2 bits b ₁ and b ₀ ( The count value composed of b ₁ is the upper bit) is supplied to the memory 12b as a read address. Specifically, the bits b _1, b ₀ are (0, 0),
Four kinds of read addresses of (0,1), (1,0), and (1,1) are cyclically supplied to the memory 12b.

In the memory 12b, the level value of a predetermined phase of the local subcarrier, for example, "sin-57 °", "si".
n33 ° "," sin123 ° "," sin213 ° "
Are stored in the memory 12b, and the memory 12b repeatedly reads these based on the read address and supplies them to the multiplier 14. That is, the multiplier 14 has, for example, as shown in FIG. 4C, “sin −57 °” and “sin 33” which are level values of a predetermined phase of a local subcarrier (shown by a broken line).
The sample values Q _i (i = 1, 2, 3, ...) In which “°”, “sin123 °”, and “sin213 °” circulate are supplied in synchronization with the sampling clock.

On the other hand, the multiplier 14 has, for example, the circuit shown in FIG.
And as shown in FIG. 4b, sample values P _i (i = 1, 2 ,, _i ) obtained by sampling an input subcarrier (shown by a broken line) supplied as a color burst signal with a sampling clock (shown in FIG. 4d). 3 ...) are discretely supplied.

Then, the multiplier 14 multiplies the corresponding sample value P _i by the sample value Q _i , and the averaging (I) circuit 15
Averages mn, for example, four of these multiplication values. As a result, the averaging (I) circuit 15 outputs the average value AV calculated by the following equation 1.

AV = (P ₁ × Q ₁ + P ₂ × Q ₂ + P ₃ × Q ₃ + P ₄ × Q ₄ ) / 4 Equation 1

Therefore, the averaging (I) circuit 15 uses the equation 1
Thus, 0 is output when the phase difference θ between the input subcarrier and the local subcarrier is 90 degrees, and when the phase difference θ deviates from 90 degrees, the average value AV corresponding to the deviation is output.

The averaging (II) circuit 16 averages the average value AV from the averaging (I) circuit 15 over a plurality of lines, as in the above embodiment.

The pulse generator 17 and the integrator 18 convert the average value of a plurality of lines from the averaging (II) circuit 16 into an analog signal, as in the above embodiment. Therefore,
The integrator 18 outputs 0 when the phase difference θ between the input subcarrier and the local subcarrier is 90 degrees as shown in FIGS. 4b and 4c described above, and the phase difference θ is 90 degrees as shown in FIG.
When it is other than 90 degrees, an analog value corresponding to the deviation from 90 degrees is output to control the oscillation frequency and phase of the VCO 11.

Thus, also in the clock generation circuit 10 of this embodiment, the sampling clock from the VCO 11 is applied to the input subcarrier superimposed on the digital composite signal converted into the digital signal by the A / D converter 3. When the frequency is 4f _SC and the phase is delayed by 123 degrees, the signal is locked and the sampling clock in this locked state is supplied to the A / D converter 3. As a result,
From the A / D converter 3, as in the above-described embodiment, the terminal 1
The composite signal from is converted into a digital composite signal based on a sampling clock having a frequency four times that of the input subcarrier superimposed as a color burst signal and having a phase delayed by 123 degrees, and a digital composite signal is output. In other words, it is possible to obtain the same effect as that of the above-described embodiment and to make the averaging (I) circuit 15 have a simple circuit configuration.

Further, since it is possible to easily change the phase of the sampling clock by changing the sample value Q _i in the local oscillator 12, that is, the predetermined phase, the SCH phase is not 0 degrees as in the above-mentioned embodiment. The analog composite signal can be converted into a digital composite signal conforming to the D-2 format and output.

The present invention is not limited to the above-mentioned embodiment, and for example, in the above-mentioned embodiment, the pulse generator 17 generates the pulse signal having the width corresponding to the average value. However, the number of pulse signals may be generated according to the average value.

It goes without saying that the present invention can also be applied to the case where a digital composite signal is obtained in, for example, the so-called PAL system or SECAM system.

[0050]

As is apparent from the above description, the analog-to-digital converter according to the present invention has a voltage-controlled oscillating means for generating a sampling clock m times the subcarrier frequency and a sampling from the voltage-controlled oscillating means. An analog / digital converting means for converting an analog composite video signal into a digital composite video signal by a clock and outputting the same, an extracting means for extracting a color burst signal from the digital composite video signal from the analog / digital converting means, and a voltage control oscillating means. Local oscillating means for generating a subcarrier based on the sampling clock from, the multiplying means for multiplying the subcarrier from the local oscillating means by the color burst signal from the extracting means, and mn consecutive multiplication values from the multiplying means. The average value from the averaging means for averaging And a digital / analog conversion means for controlling the oscillation frequency and phase of the voltage controlled oscillation means based on the average value converted into the analog signal, and converting the frequency and phase of the sampling clock from the converted digital composite video signal. I'm trying to get
For example, even if the values of the electrical components that make up the device change due to temperature characteristics, changes over time, or the power supply voltage changes, a field back is applied so that these changes do not affect the sampling clock. It is possible to always generate and output a digital composite video signal complying with a predetermined system without the phase fluctuation of the sampling clock caused by the fluctuation of temperature and power supply voltage as in the analog / digital converter of FIG. In other words, the analog / digital converter can be adjusted.

Further, the sampling clock can be obtained by digital signal processing, and this analog / digital conversion device can be made into a one-chip IC.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an analog / digital conversion device to which the present invention is applied.

FIG. 2 is a diagram showing a specific circuit configuration of an integrator that constitutes the analog / digital conversion apparatus.

FIG. 3 is a diagram showing a specific circuit configuration of a local oscillator that constitutes the analog / digital conversion apparatus.

FIG. 4 is a waveform diagram for explaining the operation of the analog / digital converter.

FIG. 5 is a waveform diagram for explaining the operation of the analog / digital converter.

FIG. 6 is a block diagram showing a configuration of a conventional analog / digital conversion device.

[Explanation of symbols]

 3 ... A / D converter 10 ... Clock generation circuit 11 ... VCO 12 ... Local oscillator 13 ... BPF 14 ... Multiplier 15 ... Averaging (I) circuit 16. ..Averaging (II) circuit 17 ... Pulse generator 18 ... Integrator

Claims (4)

[Claims] 1. A voltage-controlled oscillating means for generating a sampling clock of m times the sub-carrier frequency, and an analog / analog output for converting an analog composite video signal into a digital composite video signal by the sampling clock from the voltage-controlled oscillating means. Digital converting means, extracting means for extracting a color burst signal from the digital composite video signal from the analog / digital converting means, local oscillating means for generating a subcarrier based on the sampling clock from the voltage controlled oscillating means, Multiplying means for multiplying the sub-carrier from the local oscillating means by the color burst signal from the extracting means, averaging means for averaging consecutive mn multiplication values from the multiplying means, and averaging means Is converted into an analog signal, and based on the average value converted into the analog signal An analog / digital conversion device comprising: a digital / analog conversion means for controlling the oscillation frequency and phase of the voltage controlled oscillation means. 2. The digital / analog conversion means, a pulse signal generating means for generating a pulse signal having a width corresponding to an average value from the averaging means, and integrating the pulse signal from the pulse signal generating means, 2. An analog / digital converter according to claim 1, further comprising an integrating means for supplying the integrated value to the voltage controlled oscillating means. 3. The local oscillating means counts the sampling clock from the voltage controlled oscillating means, and the multiplying means receives a level value of a predetermined phase of a subcarrier based on the count value from the counting means. Analogue according to claim 1, characterized in that it comprises storage means for supplying.
Digital converter. 4. The analog according to claim 1, further comprising line averaging means for averaging the average value from the averaging means over at least two lines and supplying the averaged value to the digital / analog converting means. / Digital converter.