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JPH05152611A - Manufacture of led semiconductor chip for led array print head - Google Patents

Manufacture of led semiconductor chip for led array print head

Info

Publication number
JPH05152611A
JPH05152611A JP31266391A JP31266391A JPH05152611A JP H05152611 A JPH05152611 A JP H05152611A JP 31266391 A JP31266391 A JP 31266391A JP 31266391 A JP31266391 A JP 31266391A JP H05152611 A JPH05152611 A JP H05152611A
Authority
JP
Japan
Prior art keywords
wafer
semiconductor chip
led semiconductor
led
dividing lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31266391A
Other languages
Japanese (ja)
Inventor
Yutaka Tatsumi
豊 巽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP31266391A priority Critical patent/JPH05152611A/en
Publication of JPH05152611A publication Critical patent/JPH05152611A/en
Pending legal-status Critical Current

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  • Dot-Matrix Printers And Others (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To reduce the fraction defective at the time of manufacturing an LED semiconductor chip provided with a plurality of light emitting element sections by cutting a wafer along longitudinal and transversal parting lines drawn on the wafer. CONSTITUTION:After forming indentation grooves 7 along at least transversal parting lines parallel to both the left and right end faces of LED semiconductor chips 2 of the longitudinal parting lines Al and transversal parting lines which are drawn on a wafer A for dividing the wafer A into each chip 2, the wafer A is divided into the chips 2 by cutting the wafer A in the grooves 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子写真式プリンタ等
における光源として使用されるLEDアレイプリントヘ
ッドにおいて、発光素子部を備えたLED半導体チップ
を製造する方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an LED semiconductor chip having a light emitting element portion in an LED array print head used as a light source in an electrophotographic printer or the like.

【0002】[0002]

【従来の技術】一般に、この種のLEDアレイプリント
ヘッドは、特開平2−184466号公報等に記載さ
れ、且つ、図1〜図3に示すように、基板1の上面に、
上面に複数個の発光素子部3を一定ピッチPの間隔で一
列状に形成した長さLのLED半導体チップ2の複数個
を、当該各LED半導体チップ2の各々における発光素
子部3が一直線に沿って並ぶようにして搭載する構成に
している。
2. Description of the Related Art Generally, an LED array printhead of this type is described in JP-A-2-184466, and as shown in FIGS. 1 to 3, on an upper surface of a substrate 1,
A plurality of LED semiconductor chips 2 each having a length L in which a plurality of light emitting element portions 3 are formed in a line on the upper surface at a constant pitch P are arranged so that the light emitting element portions 3 in each LED semiconductor chip 2 are aligned. It is configured to be mounted side by side.

【0003】なお、前記各LED半導体チップ2におい
て、符号4は、前記発光素子部3を形成するためのGa
- As- P系拡散層、符号5は拡散バリヤー層(絶縁
層)、符号6は前記発光素子部3に接続した電極導体を
各々示す。また、前記LED半導体チップ2の製造に際
して、従来は、図4に示すように、Ga- As系シリン
コン製のウエハーAを使用し、このウエハーAの表面
に、前記Ga- As- P系拡散層4を形成し、次で、複
数本の縦分割線A1 及び複数本の横分割線A2 によって
区画された各LED半導体チップ2の箇所に、拡散バリ
ヤー層5、発光素子部3及び電極導体6を各々形成した
のち、前記ウエハーAを、ダイヤモンド砥石B又はダイ
シングソー等の切削工具にて前記各縦分割線A 1 及び各
横分割線A2 に沿って切断することによって、各LED
半導体チップ2ごとに分割すると言う方法を採用してい
る。
In each of the LED semiconductor chips 2
Reference numeral 4 denotes Ga for forming the light emitting element section 3.
-As-P type diffusion layer, reference numeral 5 is a diffusion barrier layer (insulation
Layer), reference numeral 6 is an electrode conductor connected to the light emitting element section 3.
Each is shown. Further, in manufacturing the LED semiconductor chip 2,
Then, conventionally, as shown in FIG.
The surface of this wafer A is made by using wafer A made by CON
Then, the Ga-As-P-based diffusion layer 4 is formed on the
Several vertical dividing lines A1And a plurality of horizontal dividing lines A2By
Diffusion burrs are placed on each partitioned LED semiconductor chip 2.
The layer 5, the light emitting element portion 3 and the electrode conductor 6 are formed respectively.
After that, the wafer A is replaced with a diamond grindstone B or a die.
With a cutting tool such as a sing saw, each vertical dividing line A 1And each
Horizontal dividing line A2Each LED by cutting along
The method of dividing each semiconductor chip 2 is adopted.
It

【0004】そして、ウエハーAを、前記のように、ダ
イヤモンド砥石B又はダイシングソー等の切削工具にて
前記各縦分割線A1 及び各横分割線A2 に沿って切断す
る場合、その切断部には、マイクロクラック及びチッピ
ングが必然的に発生すると共に、拡散バリヤー層6に剥
離が必然的に発生するものである。
When the wafer A is cut along the vertical dividing lines A 1 and the horizontal dividing lines A 2 with the cutting tool such as the diamond grindstone B or the dicing saw as described above, the cutting portion Inevitably, microcracks and chipping occur, and peeling of the diffusion barrier layer 6 also occurs.

【0005】[0005]

【発明が解決しようとする課題】ところで、前記LED
アレイプリントヘッドにおいて、基板1の上面に、複数
個のLED半導体チップ2を一列状に並べて搭載するに
際して、各発光素子部3におけるピッチ間隔Pを、各L
ED半導体チップ2の継ぎ目箇所においても一定のピッ
チ間隔Pにしなければならないことに加えて、各LED
半導体チップ2の継ぎ目箇所に隙間をあけるようにしな
ければならないから、前記各LED半導体チップ2にお
ける各発光素子部3のうち当該LED半導体チップ2の
左右両端面2aに隣接する発光素子部3は、前記左右両
端面2aにきわめて接近した部位に位置する形態にな
る。
By the way, the above-mentioned LED
In the array print head, when a plurality of LED semiconductor chips 2 are mounted in a line on the upper surface of the substrate 1, the pitch interval P in each light emitting element section 3 is set to L
In addition to having to have a constant pitch interval P also at the joint portion of the ED semiconductor chip 2, each LED
Since it is necessary to make a gap at the joint portion of the semiconductor chip 2, the light emitting element portion 3 adjacent to the left and right end surfaces 2a of the LED semiconductor chip 2 among the light emitting element portions 3 of each LED semiconductor chip 2 is The shape is such that it is located in a region extremely close to the left and right end faces 2a.

【0006】一方、前記LED半導体チップ2における
左右両端面2aは、前記ウエハーAを、ダイヤモンド砥
石B又はダイシングソー等の切削工具にて前記各横分割
線A 2 に沿って切断することによって形成されるもので
あって、前記各LED半導体チップ2における各発光素
子部3のうち当該LED半導体チップ2の左右両端面2
aに隣接する発光素子部3は、前記両端面2aにきわめ
て接近した部位に位置していることにより、ウエハーA
の切断に際して必然的に発生するマイクロクラック及び
チッピング、並びに拡散バリヤー層6の剥離の影響を受
けて、その輝度が他の発光素子部における輝度よりも低
下することになるから、LED半導体チップを、ウエハ
ーを使用して製造する場合に、不良品の発生率が高いと
言う問題があった。
On the other hand, in the LED semiconductor chip 2
The left and right end surfaces 2a are formed by diamond-grinding the wafer A.
Each horizontal division with a cutting tool such as stone B or a dicing saw
Line A 2Formed by cutting along
Therefore, each luminescent element in each LED semiconductor chip 2
Left and right end faces 2 of the LED semiconductor chip 2 of the child portion 3
The light-emitting element portion 3 adjacent to a has a sharp edge on both end faces 2a.
Wafer A
Micro cracks that are inevitably generated when cutting
It is affected by chipping and peeling of the diffusion barrier layer 6.
However, the brightness is lower than the brightness of other light emitting elements.
LED semiconductor chips are mounted on the wafer
If the production rate of defective products is high when using
There was a problem to say.

【0007】特に、この問題、つまり不良率の発生が高
くなる傾向は、前記各発光素子部3のピッチ間隔Pが狭
いほど、換言すると単位長さ当たりにおける発光素子部
3の数、つまり、ドット数に比例して増大するのであ
る。本発明は、LED半導体チップを、ウエハーを使用
して製造する場合において、不良品の発生率を確実に低
減できるようにした製造方法を提供することを技術的課
題とするものである。
In particular, this problem, that is, the tendency of occurrence of defective rate is high, is that the narrower the pitch interval P of the light emitting element portions 3 is, that is, the number of the light emitting element portions 3 per unit length, that is, the dot. It increases in proportion to the number. SUMMARY OF THE INVENTION It is a technical object of the present invention to provide a manufacturing method capable of reliably reducing the incidence of defective products when manufacturing LED semiconductor chips using a wafer.

【0008】[0008]

【課題を解決するための手段】この技術的課題を達成す
るため本発明は、ウエハーの表面に、拡散層を形成し、
次いで、複数本の縦分割線及び複数本の横分割線によっ
て区画された各LED半導体チップの箇所に、拡散バリ
ヤー層、発光素子部及び電極導体を各々形成したのち、
前記ウエハーを、切削工具にて前記各縦分割線及び各横
分割線に沿って切断することによって、各LED半導体
チップごとに切断・分割するようにしたLED半導体チ
ップの製造方法において、前記各LED半導体チップご
とに区画する各縦分割線及び各横分割線のうち少なくと
も前記LED半導体チップにおける左右両端面と平行な
横分割線の部分に、凹み溝を、前記各横分割線に沿って
延びるように形成し、この凹み溝内で前記ウエハーに対
する切断・分割を行うことにした。
In order to achieve this technical object, the present invention provides a diffusion layer on the surface of a wafer,
Then, after forming a diffusion barrier layer, a light emitting element section and an electrode conductor at the location of each LED semiconductor chip partitioned by a plurality of vertical division lines and a plurality of horizontal division lines,
In the method for manufacturing an LED semiconductor chip, the wafer is cut and divided for each LED semiconductor chip by cutting the wafer along each of the vertical dividing lines and each of the horizontal dividing lines with a cutting tool. A recessed groove is formed along each of the horizontal dividing lines at least in a portion of each of the vertical dividing lines and each of the horizontal dividing lines that are divided for each semiconductor chip, the horizontal dividing line being parallel to the left and right end surfaces of the LED semiconductor chip. Then, the wafer is cut and divided in the groove.

【0009】[0009]

【作 用】このように、前記ウエハーを各LED半導
体チップごとに区画する各縦分割線及び各横分割線のう
ち少なくとも前記LED半導体チップにおける左右両端
面と平行な横分割線の部分に、凹み溝を、前記各横分割
線に沿って延びるように形成し、この凹み溝内で前記ウ
エハーに対する切断・分割を行うことにより、ウエハー
を切断工具にて各LED半導体チップごとに切断・分割
にする場合に、各LED半導体チップの左右両端面のう
ち拡散層及び拡散バリヤー層の部分に及ぼすダメージ
を、前記凹み溝の存在によって少なくすることができる
から、前記各LED半導体チップの左右両端面のうち拡
散層及び拡散バリヤー層の部分に、マイクロクラック及
びチッピング並びに剥離が発生することを大幅に低減で
きるのである。
[Operation] As described above, among the vertical dividing lines and the horizontal dividing lines that divide the wafer into the LED semiconductor chips, at least the horizontal dividing lines parallel to the left and right end surfaces of the LED semiconductor chip are recessed. Grooves are formed so as to extend along each of the horizontal dividing lines, and the wafer is cut / divided in the recessed grooves by cutting tools so that each LED semiconductor chip is cut / divided by a cutting tool. In this case, since damage to the diffusion layer and the diffusion barrier layer of the left and right end faces of each LED semiconductor chip can be reduced by the presence of the recessed groove, the left and right end faces of each LED semiconductor chip can be reduced. It is possible to significantly reduce the occurrence of microcracks, chipping and peeling in the diffusion layer and the diffusion barrier layer.

【0010】[0010]

【発明の効果】従って、本発明によると、LED半導体
チップを、ウエハーを使用して製造する場合に際して、
当該LED半導体チップにおける各発光素子部のうちL
ED半導体チップの左右両端面の隣接する発光素子部の
輝度が低下して不良品になると言う不良品の発生率を、
確実に低減できる効果を有する。
Therefore, according to the present invention, when an LED semiconductor chip is manufactured using a wafer,
L of each light emitting element portion in the LED semiconductor chip
The occurrence rate of defective products in which the brightness of the adjacent light emitting element portions on the left and right end surfaces of the ED semiconductor chip decreases and the defective products are
It has an effect that can be surely reduced.

【0011】[0011]

【実施例】以下、本発明の実施例を図面(図5〜図1
3)について説明する。この図において符号Aは、複数
本の縦分割線A1 と、同じく複数本の横分割線A2 に沿
って複数個のLED半導体チップ2ごとに分割するよう
にしたGa- As系シリンコン製のウエハーを示し、こ
のウエハーAの上面に、図6及び図7に示すように、G
a- As- P系の拡散層4を形成したのち、この拡散層
4の上面に、前記各LED半導体チップ2の部分に複数
個の抜き窓5aを備えた拡散バリヤー層5を形成する。
Embodiments of the present invention will now be described with reference to the drawings (FIGS. 5 to 1).
3) will be described. In this figure, reference numeral A is a Ga-As type sircon made by dividing into a plurality of LED semiconductor chips 2 along a plurality of vertical dividing lines A 1 and a plurality of horizontal dividing lines A 2 . A wafer is shown, and on the upper surface of the wafer A, as shown in FIGS.
After the diffusion layer 4 of a-As-P type is formed, a diffusion barrier layer 5 having a plurality of cut-out windows 5a is formed on the upper surface of the diffusion layer 4 in the portion of each LED semiconductor chip 2.

【0012】次いで、前記ウエハーAにおける上面のう
ち前記各横分割線A2 の部分に、図8及び図9に示すよ
うに、凹み溝7を、前記各横分割線A2 に沿って延びる
ように形成する。なお、この各凹み溝7は、従来から良
く知られているように、ウエハーAの上面にホォトレジ
スト膜を形成し、このホォトレジスト膜に、前記凹み溝
7の形状通りのパターンをマスク露光したのち現像する
ことによって、前記凹み溝7と同じ形状の開口部を形成
し、次いで、エッチング液にてエッチングしたのち、前
記ホォトレジスト膜を除去すると言ういわゆるホォトエ
ッチング法にて形成する。
[0012] Then, the a portion of the wafer each transverse dividing line of the top surface of A A 2, as shown in FIGS. 8 and 9, the recessed groove 7, extending along the each lateral division line A 2 To form. As is well known in the art, each of the recessed grooves 7 is formed with a photoresist film on the upper surface of the wafer A, and the photoresist film is mask-exposed with a pattern having the same shape as the recessed grooves 7. After that, by developing, an opening having the same shape as that of the recessed groove 7 is formed. Then, after etching with an etching solution, the photoresist film is removed by a so-called photoetching method.

【0013】次に、図10及び図11に示すように、前
記ウエハーAの上面に拡散処理を施すことによって、前
記拡散層4のうち前記拡散バリヤー層5における各抜き
窓5a内の部分に発光素子部3を各々形成し、次いで、
前記各発光素子部3の箇所に、電極導体6を各々形成
し、更に、ウエハーAの下面に、裏メタル層8を形成す
る。
Next, as shown in FIGS. 10 and 11, by diffusing the upper surface of the wafer A, light is emitted to a portion of the diffusion layer 4 in each of the vent windows 5a in the diffusion barrier layer 5. Each of the element parts 3 is formed, and then
Electrode conductors 6 are formed on the respective light emitting element portions 3, and a back metal layer 8 is formed on the lower surface of the wafer A.

【0014】そして、前記ウエハーAを、図12及び図
13に示すように、ダイヤモンド砥石B又はダイシング
ソー等の切削工具にて前記各縦分割線A1 及び各横分割
線A 2 に沿って切断することによって、各LED半導体
チップ2ごとに分割するに際して、前記各横分割線A2
に沿っての切断を、前記各凹み溝7内において行うよう
にするのである。
Then, the wafer A is shown in FIGS.
As shown in 13, diamond grinding stone B or dicing
Each vertical dividing line A with a cutting tool such as a saw1And each horizontal division
Line A 2Each LED semiconductor by cutting along
When dividing into chips 2, each of the horizontal dividing lines A2
Cutting along the inside of each groove 7
To do.

【0015】すると、前記ウエハーAを、ダイヤモンド
砥石B又はダイシングソー等の切断工具にて各LED半
導体チップ2ごとに切断・分割にする場合に、各LED
半導体チップ2の左右両端面2aのうち拡散層4及び拡
散バリヤー層5の部分に及ぼすダメージを、前記凹み溝
7の存在によって少なくすることができるから、前記各
LED半導体チップ2の左右両端面2aのうち拡散層4
及び拡散バリヤー層5の部分に、マイクロクラック及び
チッピング並びに剥離が発生することを大幅に低減でき
るのである。
Then, when the wafer A is cut and divided for each LED semiconductor chip 2 by a cutting tool such as a diamond grindstone B or a dicing saw, each LED is cut.
Since the damage to the diffusion layer 4 and the diffusion barrier layer 5 of the left and right end surfaces 2a of the semiconductor chip 2 can be reduced by the presence of the recessed groove 7, the left and right end surfaces 2a of each LED semiconductor chip 2 can be reduced. Out of diffusion layer 4
It is possible to significantly reduce the occurrence of microcracks, chipping and peeling in the diffusion barrier layer 5 and the diffusion barrier layer 5.

【0016】この場合おいて、前記各凹み溝7の深さ
は、前記拡散層4に形成する発光素子部3の厚さと等し
くするか、発光素子部3の厚さよりも大きくすることが
好ましく、また、前記各凹み溝7の幅寸法は、前記ダイ
ヤモンド砥石B又はダイシングソー等の切断工具におけ
る切削幅と等しくするか、切削幅よりも大きくすること
が好ましい。
In this case, the depth of each of the recessed grooves 7 is preferably equal to the thickness of the light emitting element portion 3 formed in the diffusion layer 4 or larger than the thickness of the light emitting element portion 3. Further, the width dimension of each recessed groove 7 is preferably equal to or larger than the cutting width in the cutting tool such as the diamond grindstone B or the dicing saw.

【0017】なお、前記実施例は、各横分割線A2 の箇
所における凹み溝7を、拡散バリヤー層5を形成したあ
との時点で形成する場合を示したが、本発明は、これに
限らず、前記凹み溝7を、発光素子部3を形成したあと
の時点で形成するようにしたり、或いは、電極導体6を
形成したあとの時点で形成するようにしたりしても良い
のである。
Although the above-mentioned embodiment shows the case where the recessed groove 7 at each horizontal dividing line A 2 is formed at the time after the diffusion barrier layer 5 is formed, the present invention is not limited to this. Instead, the recessed groove 7 may be formed after the light emitting element portion 3 is formed, or may be formed after the electrode conductor 6 is formed.

【0018】また、凹み溝を、前記実施例のように、各
横分割線A2 の箇所に形成することに加えて、前記各縦
分割線A1 の箇所に、当該縦分割線A1 に沿って延びる
ように形成するようにしても良いのである。
Further, in addition to forming the recessed groove at the position of each horizontal dividing line A 2 as in the above-described embodiment, at the position of each vertical dividing line A 1 , the vertical dividing line A 1 is formed. It may be formed so as to extend along it.

【図面の簡単な説明】[Brief description of drawings]

【図1】LEDアレイプリントヘッドの要部を示す拡大
斜視図である。
FIG. 1 is an enlarged perspective view showing a main part of an LED array printhead.

【図2】図1のII−II視断面図である。FIG. 2 is a sectional view taken along line II-II of FIG.

【図3】図1のIII −III 視断面図である。FIG. 3 is a sectional view taken along line III-III in FIG.

【図4】従来の製造方法を示す斜視図である。FIG. 4 is a perspective view showing a conventional manufacturing method.

【図5】本発明の方法に使用するウエハーの斜視図であ
る。
FIG. 5 is a perspective view of a wafer used in the method of the present invention.

【図6】図5のVI−VI視拡大断面図である。6 is an enlarged sectional view taken along line VI-VI of FIG.

【図7】図5のVII −VII 視拡大断面図である。FIG. 7 is an enlarged sectional view taken along line VII-VII of FIG.

【図8】図5におけるウエハーの上面に凹み溝を形成し
た状態の斜視図である。
8 is a perspective view showing a state in which a recessed groove is formed on the upper surface of the wafer in FIG.

【図9】図8のIX−IX視拡大断面図である。9 is an enlarged sectional view taken along line IX-IX of FIG.

【図10】図5におけるウエハーに発光素子部を形成し
た状態の拡大断面図である。
10 is an enlarged cross-sectional view of a state in which a light emitting element portion is formed on the wafer in FIG.

【図11】図10のXI−XI視断面図である。11 is a sectional view taken along line XI-XI of FIG.

【図12】図5のウエハーを各LED半導体チップに切
断・分割する状態を示す斜視図である。
12 is a perspective view showing a state in which the wafer of FIG. 5 is cut and divided into LED semiconductor chips.

【図13】図12のXIII−XIII視拡大断面図である。13 is an enlarged sectional view taken along line XIII-XIII in FIG.

【符号の説明】[Explanation of symbols]

A ウエハー A1 縦分割線 A2 横分割線 B ダイヤモンド砥石 2 LED半導体チップ 2a LED半導体チップにおける左右両端
面 3 発光素子部 4 拡散層 5 拡散バリヤー層 6 電極導体 7 凹み溝
A Wafer A 1 Vertical dividing line A 2 Horizontal dividing line B Diamond grindstone 2 LED semiconductor chip 2a Left and right end surfaces of LED semiconductor chip 3 Light emitting element section 4 Diffusion layer 5 Diffusion barrier layer 6 Electrode conductor 7 Recessed groove

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】ウエハーの表面に、拡散層を形成し、次い
で、複数本の縦分割線及び複数本の横分割線によって区
画された各LED半導体チップの箇所に、拡散バリヤー
層、発光素子部及び電極導体を各々形成したのち、前記
ウエハーを、切削工具にて前記各縦分割線及び各横分割
線に沿って切断することによって、各LED半導体チッ
プごとに切断・分割するようにしたLED半導体チップ
の製造方法において、前記各LED半導体チップごとに
区画する各縦分割線及び各横分割線のうち少なくとも前
記LED半導体チップにおける左右両端面と平行な横分
割線の部分に、凹み溝を、前記各横分割線に沿って延び
るように形成し、この凹み溝内で前記ウエハーに対する
切断・分割を行うことを特徴とするLEDアレイプリン
トヘッドにおけるLED半導体チップの製造方法。
1. A diffusion layer is formed on the surface of a wafer, and then, a diffusion barrier layer and a light emitting element section are provided at the positions of each LED semiconductor chip partitioned by a plurality of vertical dividing lines and a plurality of horizontal dividing lines. After forming the electrode conductors and the electrode conductors respectively, the wafer is cut along the vertical dividing lines and the horizontal dividing lines with a cutting tool to cut and divide each LED semiconductor chip. In the method of manufacturing a chip, a recessed groove is formed in at least a portion of each vertical division line and each horizontal division line that is divided for each of the LED semiconductor chips, the horizontal division line being parallel to the left and right end surfaces of the LED semiconductor chip. In an LED array print head, which is formed so as to extend along each horizontal division line, and cuts and divides the wafer in the concave groove. Manufacturing method of ED semiconductor chip.
JP31266391A 1991-11-27 1991-11-27 Manufacture of led semiconductor chip for led array print head Pending JPH05152611A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31266391A JPH05152611A (en) 1991-11-27 1991-11-27 Manufacture of led semiconductor chip for led array print head

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31266391A JPH05152611A (en) 1991-11-27 1991-11-27 Manufacture of led semiconductor chip for led array print head

Publications (1)

Publication Number Publication Date
JPH05152611A true JPH05152611A (en) 1993-06-18

Family

ID=18031929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31266391A Pending JPH05152611A (en) 1991-11-27 1991-11-27 Manufacture of led semiconductor chip for led array print head

Country Status (1)

Country Link
JP (1) JPH05152611A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996005617A1 (en) * 1994-08-12 1996-02-22 The Charles Stark Draper Laboratory, Inc. Improved wafer and method of making same
US6560871B1 (en) * 2000-03-21 2003-05-13 Hewlett-Packard Development Company, L.P. Semiconductor substrate having increased facture strength and method of forming the same
KR100804362B1 (en) * 2002-02-21 2008-02-15 주식회사 엘지이아이 Cutting method of semiconductor wafer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996005617A1 (en) * 1994-08-12 1996-02-22 The Charles Stark Draper Laboratory, Inc. Improved wafer and method of making same
US5596222A (en) * 1994-08-12 1997-01-21 The Charles Stark Draper Laboratory, Inc. Wafer of transducer chips
US6560871B1 (en) * 2000-03-21 2003-05-13 Hewlett-Packard Development Company, L.P. Semiconductor substrate having increased facture strength and method of forming the same
US7055242B2 (en) 2000-03-21 2006-06-06 Hewlett-Packard Development Company, L.P. Semiconductor substrate having increased fracture strength
KR100804362B1 (en) * 2002-02-21 2008-02-15 주식회사 엘지이아이 Cutting method of semiconductor wafer

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