JPH05152473A - Mounting and cooling methods for intergrated circuit - Google Patents
Mounting and cooling methods for intergrated circuitInfo
- Publication number
- JPH05152473A JPH05152473A JP34008991A JP34008991A JPH05152473A JP H05152473 A JPH05152473 A JP H05152473A JP 34008991 A JP34008991 A JP 34008991A JP 34008991 A JP34008991 A JP 34008991A JP H05152473 A JPH05152473 A JP H05152473A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- multilayer wiring
- ceramic substrate
- wiring ceramic
- heat conduction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001816 cooling Methods 0.000 title claims abstract description 32
- 239000000919 ceramic Substances 0.000 claims abstract description 31
- 229910000679 solder Inorganic materials 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 20
- 150000001875 compounds Chemical class 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims description 5
- 239000003507 refrigerant Substances 0.000 claims description 4
- GLGNXYJARSMNGJ-VKTIVEEGSA-N (1s,2s,3r,4r)-3-[[5-chloro-2-[(1-ethyl-6-methoxy-2-oxo-4,5-dihydro-3h-1-benzazepin-7-yl)amino]pyrimidin-4-yl]amino]bicyclo[2.2.1]hept-5-ene-2-carboxamide Chemical compound CCN1C(=O)CCCC2=C(OC)C(NC=3N=C(C(=CN=3)Cl)N[C@H]3[C@H]([C@@]4([H])C[C@@]3(C=C4)[H])C(N)=O)=CC=C21 GLGNXYJARSMNGJ-VKTIVEEGSA-N 0.000 abstract description 3
- 229940125758 compound 15 Drugs 0.000 abstract description 3
- 239000002826 coolant Substances 0.000 abstract description 2
- AFYPFACVUDMOHA-UHFFFAOYSA-N chlorotrifluoromethane Chemical compound FC(F)(F)Cl AFYPFACVUDMOHA-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は集積回路の取付方法およ
び冷却方法に関し、特に、集積回路の取付け時間の短縮
化および冷却性能の向上を図ることのできる集積回路の
取付方法および冷却方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit mounting method and a cooling method, and more particularly to an integrated circuit mounting method and a cooling method capable of shortening the mounting time of the integrated circuit and improving the cooling performance.
【０００２】[0002]
【従来の技術】従来、多層配線セラミック基板１への集
積回路（パッケージ）３の半田付けは、マウンターを用
いて行なっていた。例えば、図２に示すように枠４を取
付けた多層配線セラミック基板１を搭載テーブル１８上
に載置し、確実に固定する。設備付属の画像認識装置で
位置決めを行ない、吸着機構１７を有するハンド１６で
集積回路３を吸着し、多層配線セラミック基板１の指定
された位置（ロケーション）に集積回路３を搭載する。
搭載が完了したパッケージは、ベーパーリフローやＮ2
リフロ炉などにより半田をリフローして半田付けすると
いう取付方法であった。2. Description of the Related Art Conventionally, soldering of an integrated circuit (package) 3 to a multilayer wiring ceramic substrate 1 has been performed using a mounter. For example, as shown in FIG. 2, the multilayer wiring ceramic substrate 1 to which the frame 4 is attached is placed on the mounting table 18 and securely fixed. Positioning is performed by the image recognition device attached to the equipment, the integrated circuit 3 is sucked by the hand 16 having the suction mechanism 17, and the integrated circuit 3 is mounted at the designated position on the multilayer wiring ceramic substrate 1.
The package that has been installed is vapor reflow or N 2
The mounting method was to reflow the solder by using a reflow oven or the like and solder the solder.
【０００３】また、このような方法で取り付けられた集
積回路３の冷却構造は、従来、図３に示すようになって
いた。すなわち、集積回路３から発せられた熱は、熱伝
導性コンパウンド１５を介し、冷却部材１９に伝導す
る。冷却部材１９は、ねじ２０を締つけることにより外
側に開く構造となっており、高さの違う個々の集積回路
３と一定の微少間隔１４を保つ位置に配設されるととも
に、冷却部材１９の胴部で熱伝導ブロック１０と密着す
るようになっている。したがって、集積回路３から発せ
られる熱は、冷却部材１９から熱伝導ブロック１０に伝
導される。さらに、冷媒１３が流れる流路１２を有する
コールドプレート１１に熱伝導ブロック１０の熱が伝導
されることにより、集積回路３を冷却する構造となって
いた。Further, the cooling structure of the integrated circuit 3 mounted by such a method has hitherto been as shown in FIG. That is, the heat generated from the integrated circuit 3 is conducted to the cooling member 19 via the heat conductive compound 15. The cooling member 19 has a structure that opens to the outside by tightening the screw 20, is arranged at a position where a constant minute gap 14 is maintained between the integrated circuits 3 having different heights, and The body is in close contact with the heat conduction block 10. Therefore, the heat generated from the integrated circuit 3 is conducted from the cooling member 19 to the heat conduction block 10. Further, the heat of the heat conduction block 10 is conducted to the cold plate 11 having the flow path 12 through which the refrigerant 13 flows, so that the integrated circuit 3 is cooled.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上述し
た従来の集積回路の取付方法にあっては、多層配線セラ
ミック基板１へ一個ずつ集積回路の搭載を行なっている
ため、集積回路の部品や組立時の組立誤差などにより、
取付け後の集積回路の高さにばらつきが生じる。このた
め、冷却モジュール組立時に熱抵抗のため、集積回路と
冷却部材との微少間隔を個々の集積回路ごとに設定しな
ければならない。したがって、組立に時間を要してしま
うい、集積回路の数が多くなるほど組立時間が増加する
という問題があった。However, in the above-mentioned conventional method of mounting an integrated circuit, since the integrated circuits are mounted on the multilayer wiring ceramic substrate 1 one by one, the parts of the integrated circuit and the assembly process are not performed. Due to the assembly error of
The height of the integrated circuit after mounting varies. Therefore, due to thermal resistance when assembling the cooling module, it is necessary to set a minute gap between the integrated circuit and the cooling member for each integrated circuit. Therefore, there is a problem that it takes time to assemble, and the assembly time increases as the number of integrated circuits increases.
【０００５】また、従来の集積回路の冷却方法にあって
は、集積回路と冷媒の流れるコールドプレートとの間に
は金属間の接触による熱伝導箇所があるため、熱抵抗の
低減図りづらいという問題があった。Further, in the conventional integrated circuit cooling method, there is a heat conduction portion due to metal contact between the integrated circuit and the cold plate through which the coolant flows, so that it is difficult to reduce the thermal resistance. was there.
【０００６】本発明は上述した事情にかんがみてなされ
たものであり、集積回路の取付け時間の短縮化および冷
却性能の向上を図ることのできる集積回路の取付方法お
よび冷却方法の提供を目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an integrated circuit mounting method and a cooling method capable of shortening the mounting time of the integrated circuit and improving the cooling performance. ..
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に本発明の集積回路の取付方法は、多層配線セラミック
基板に半田付けされる複数の集積回路パッケージを、そ
れぞれ所定の位置に、すべてのパッケージが同じ高さに
なるように保持し、次いで、多層配線セラミック基板と
各集積回路の半田接合部を位置合わせした後当接させ、
その後、半田をリフローさせて多層配線セラミック基板
に集積回路を実装する構成としてある。上記本発明の集
積回路の取付方法は、外部接続のためのピンを有する多
層配線セラミック基板を固定する枠と、前記多層配線セ
ラミック基板に半田付けされる複数の集積回路パッケー
ジを、それぞれ所定の位置に、すべてのパッケージが同
じ高さになるように保持するための前記パッケージと嵌
合する凹部を有する載置台と、前記多層配線セラミック
基板を固定する枠と係合する前記載置台に設けられた位
置決めピンを具備する集積回路の取付具を用いて実施す
ることが好ましい。In order to achieve the above-mentioned object, an integrated circuit mounting method of the present invention includes a plurality of integrated circuit packages which are soldered to a multilayer wiring ceramic substrate and are all placed at predetermined positions. Hold the packages so that they are at the same height, and then align and contact the multilayer wiring ceramic substrate and the solder joints of each integrated circuit,
After that, the solder is reflowed to mount the integrated circuit on the multilayer wiring ceramic substrate. The integrated circuit mounting method of the present invention comprises a frame for fixing a multilayer wiring ceramic substrate having pins for external connection, and a plurality of integrated circuit packages soldered to the multilayer wiring ceramic substrate at predetermined positions. A mounting table having a recess for fitting all the packages to be at the same height, and a mounting table for engaging the package, and the mounting table provided for engaging with a frame for fixing the multilayer wiring ceramic substrate. It is preferably carried out using an integrated circuit fixture with locating pins.
【０００８】また、本発明の集積回路の冷却方法は、多
層配線セラミック基板上に集積回路をすべて同じ高さで
半田付けし、該半田付けされた集積回路の半田付け面と
反対側の面に対し、一定の微少間隔をあけて熱伝導ブロ
ックを配設するとともに、集積回路と熱伝導ブロックと
の間の微少間隙にコンパウンドを介在させ、熱伝導ブロ
ックに冷媒が流れる流路を有するコールドプレートを当
接させて、集積回路の冷却を行なうようにしてある。上
記本発明の集積回路の冷却方法は、多層配線セラミック
基板上にすべて同じ高さで半田付けされた集積回路の半
田付け面と反対側の面に対し、一定の微少間隔をあけて
配設された平面部を有する熱伝導ブロックと、前記集積
回路と熱伝導ブロックとの間の微少間隙に介在させたコ
ンパウンドと、前記熱伝導ブロックと当接するととも
に、冷媒が流れる流路を有するコールドプレートと、を
具備する集積回路の冷却器を用いて実施することが好ま
しい。Further, according to the method for cooling an integrated circuit of the present invention, the integrated circuits are all soldered on the multilayer wiring ceramic substrate at the same height, and the surface of the soldered integrated circuit is opposite to the soldering surface. On the other hand, while arranging the heat conduction block with a certain minute gap, a compound is interposed in the minute gap between the integrated circuit and the heat conduction block, and a cold plate having a flow path of the refrigerant in the heat conduction block is provided. The contact is made so as to cool the integrated circuit. According to the method for cooling an integrated circuit of the present invention, a constant minute interval is provided with respect to the surface opposite to the soldering surface of the integrated circuit which is all soldered on the multilayer wiring ceramic substrate at the same height. A heat conduction block having a flat surface portion, a compound interposed in a minute gap between the integrated circuit and the heat conduction block, and a cold plate that is in contact with the heat conduction block and has a flow path through which a refrigerant flows, Preferably, it is implemented using an integrated circuit cooler comprising
【０００９】[0009]
【実施例】以下、本発明の一実施例について図面を参照
して説明する。図１（ａ）は本発明の集積回路の取付方
法の一実施例を示す断面図である。図１（ａ）に示すよ
うに、外部接続のためのピン２を有する多層配線セラミ
ック基板１に、枠４をエポキシ系接着剤８で接着する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1A is a sectional view showing an embodiment of an integrated circuit mounting method according to the present invention. As shown in FIG. 1A, the frame 4 is bonded to the multilayer wiring ceramic substrate 1 having the pins 2 for external connection with the epoxy adhesive 8.
【００１０】集積回路３の半田接続部７にも、あらかじ
め半田の供給をしておく。この半田供給はダミー基板に
半田接続パターンと同じ半田印刷を行ない、そのダミー
基板上の半田を集積回路３の半田接続部７に供給する転
写方式で行なう。ダミー基板上の半田量を変えることに
より集積回路３への半田供給量をコントロールし半田過
不足によるオープンやショートを防止する。The solder is also supplied in advance to the solder connection portion 7 of the integrated circuit 3. This solder supply is performed by a transfer method in which the same solder printing as the solder connection pattern is performed on the dummy substrate and the solder on the dummy substrate is supplied to the solder connection portion 7 of the integrated circuit 3. By changing the amount of solder on the dummy substrate, the amount of solder supplied to the integrated circuit 3 is controlled to prevent an open or a short circuit due to excess or shortage of solder.
【００１１】半田供給した集積回路３は、取付治具５の
凹部９に接続面を上にして、セットする。取付治具５
は、セラミックに近い熱膨張係数を有する材料で作成し
てあるので、熱容量が少ない構造となっている。取付治
具５に集積回路３をセットしたら、多層配線セラミック
基板１をピン２を上向にして取付治具５にセットする。
このとき、枠４と取付治具５を位置決めピン６で固定す
ることにより、多層配線セラミック基板１と集積回路３
の半田接続部７が正しく位置合わせできる構造になって
いる。The integrated circuit 3 supplied with solder is set in the recess 9 of the mounting jig 5 with the connecting surface facing upward. Mounting jig 5
Is made of a material having a coefficient of thermal expansion close to that of ceramic, so that the structure has a small heat capacity. After the integrated circuit 3 is set on the mounting jig 5, the multilayer wiring ceramic substrate 1 is set on the mounting jig 5 with the pins 2 facing upward.
At this time, by fixing the frame 4 and the mounting jig 5 with the positioning pins 6, the multilayer wiring ceramic substrate 1 and the integrated circuit 3 are
The solder connection portion 7 has a structure capable of being correctly aligned.
【００１２】取付治具５への取付けが完了したら、多層
配線セラミック基板１のピン２を上に向けた状態でベー
パーリフロー槽又はＮ2 リフロ炉などで半田のリフロー
を行なうことにより、すべての集積回路３が同じ高さで
多層配線セラミック基板１に半田付けされる。集積回路
３の高さは、取付治具５の凹部９の深さにより調整でき
る。After the mounting to the mounting jig 5 is completed, the solder is reflowed in a vapor reflow bath or an N 2 reflow furnace with the pins 2 of the multilayer wiring ceramic substrate 1 facing upward, so that all the integrated components are integrated. The circuit 3 is soldered to the multilayer wiring ceramic substrate 1 at the same height. The height of the integrated circuit 3 can be adjusted by the depth of the recess 9 of the mounting jig 5.
【００１３】上記本発明の集積回路の取付方法によれ
ば、一度に均一な高さで集積回路を多層配線セラミック
基板１上に半田付けでき、取付時間を短縮化することが
できる。According to the integrated circuit mounting method of the present invention, the integrated circuit can be soldered onto the multilayer wiring ceramic substrate 1 at a uniform height at one time, and the mounting time can be shortened.
【００１４】次に、本発明の集積回路の冷却方法につい
て説明する。図１（ｂ）は本発明の集積回路の冷却方法
の一実施例を示す断面図である。図１（ｂ）において、
熱伝導ブロック１０は熱伝導性の良いアルミニウムなど
の金属材料で作成されている。熱伝導ブロック１０の表
面には腐食防止のためメッキ処理が施してある。熱伝導
ブロック１０の集積回路３側の面は平面になっており、
集積回路３の間に微少間隔１４が保てるようになってい
る。Next, a method of cooling the integrated circuit of the present invention will be described. FIG. 1B is a cross-sectional view showing an embodiment of the integrated circuit cooling method of the present invention. In FIG. 1 (b),
The heat conduction block 10 is made of a metal material such as aluminum having good heat conductivity. The surface of the heat conduction block 10 is plated to prevent corrosion. The surface of the heat conduction block 10 on the integrated circuit 3 side is a flat surface,
A minute space 14 can be maintained between the integrated circuits 3.
【００１５】コールドプレート１１も熱伝導性の良い金
属材料で製作されている。コールドプレート１１は、冷
媒１３が常に流路１２を循環し集積回路３を冷却する構
造になっている。コールドプレート１１と熱伝導ブロッ
ク１０は、面粗度０．６ｓ程度の粗さで密着し、熱伝導
を良くし冷却性能の向上を図っている。The cold plate 11 is also made of a metal material having good thermal conductivity. The cold plate 11 has a structure in which the refrigerant 13 constantly circulates in the flow path 12 to cool the integrated circuit 3. The cold plate 11 and the heat conduction block 10 are in close contact with each other with a surface roughness of about 0.6 s to improve heat conduction and improve cooling performance.
【００１６】集積回路３上には、適量の熱伝導性コパウ
ンド１５が塗布してある。これにより、微小間隔１４は
埋められ、集積回路３の熱が熱伝導ブロック１０へと伝
導していくようになっている。熱伝導ブロック１０と枠
４、および、コールドプレート１１と熱伝導１０を、各
々ねじにより組立て冷却モジュールが完成する。On the integrated circuit 3, a proper amount of the heat conductive compound 15 is applied. As a result, the minute gap 14 is filled, and the heat of the integrated circuit 3 is conducted to the heat conduction block 10. The heat conduction block 10 and the frame 4, and the cold plate 11 and the heat conduction 10 are respectively assembled by screws to complete the cooling module.
【００１７】上記本発明の集積回路の冷却方法によれ
ば、多層配線セラミック基板上に同じ高さで集積回路が
半田付けされているため、従来のように各集積回路ごと
に微小間隔を調整する必要がなく、したがって、冷却モ
ジュールの作製が容易となる。According to the above-described integrated circuit cooling method of the present invention, since the integrated circuits are soldered on the multilayer wiring ceramic substrate at the same height, a minute interval is adjusted for each integrated circuit as in the conventional case. There is no need, and thus the cooling module is easy to make.
【００１８】また、熱伝導ブロックと冷却部材を一体化
したことにより、金属どうしの接触による熱伝導部分が
減少し冷却性能の向上が図れるとともに、部材費も低減
することができる。Further, by integrating the heat conducting block and the cooling member, the heat conducting portion due to contact between the metals can be reduced, the cooling performance can be improved, and the member cost can be reduced.
【００１９】さらに、上述した本発明の集積回路の取付
方法および冷却方法によれば、基板への集積回路の取付
けおよび冷却モジュールの組立ての一連の工程を自動化
することができる。Further, according to the above-described integrated circuit mounting method and cooling method of the present invention, a series of steps for mounting the integrated circuit on the substrate and assembling the cooling module can be automated.
【００２０】[0020]
【発明の効果】以上説明したように本発明の集積回路の
取付方法および冷却方法によれば、集積回路の取付時間
の短縮化および冷却性能の向上を図ることのできる。As described above, according to the integrated circuit mounting method and cooling method of the present invention, the mounting time of the integrated circuit can be shortened and the cooling performance can be improved.
【図１】本発明の一実施例を示す断面図であり、図１
（ａ）は本発明の集積回路の取付方法の一実施例を示す
断面図、図１（ｂ）は本発明の集積回路の冷却方法の一
実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
1A is a sectional view showing an embodiment of an integrated circuit mounting method according to the present invention, and FIG. 1B is a sectional view showing an embodiment of an integrated circuit cooling method according to the present invention.
【図２】従来の集積回路の取付方法を示す断面図であ
る。FIG. 2 is a cross-sectional view showing a conventional integrated circuit mounting method.
【図３】従来の集積回路の冷却方法を示す断面図であ
る。FIG. 3 is a cross-sectional view showing a conventional integrated circuit cooling method.
１…多層配線セラミック基板上 ２…ピン ３…集積回路 ４…枠 ５…取付治具 ６…位置決めピン ７…半田接続部 ９…凹部 １０…熱伝導ブロック １１…コールドプレート １２…流路 １３…冷媒 １４…微小間隔 １５…熱伝導性コンパウンド DESCRIPTION OF SYMBOLS 1 ... On multilayer wiring ceramic substrate 2 ... Pin 3 ... Integrated circuit 4 ... Frame 5 ... Mounting jig 6 ... Positioning pin 7 ... Solder connection part 9 ... Recess 10 ... Heat conduction block 11 ... Cold plate 12 ... Flow path 13 ... Refrigerant 14 ... Minute gap 15 ... Thermally conductive compound
Claims (4)
セラミック基板を固定する枠と、 前記多層配線セラミック基板に半田付けされる複数の集
積回路パッケージを、それぞれ所定の位置に、すべての
パッケージが同じ高さになるように保持するための前記
パッケージと嵌合する凹部を有する載置台と、 前記多層配線セラミック基板を固定する枠と係合する前
記載置台に設けられた位置決めピンを具備することを特
徴とする集積回路の取付具。1. A frame for fixing a multilayer wiring ceramic substrate having pins for external connection, and a plurality of integrated circuit packages to be soldered to the multilayer wiring ceramic substrate, each package being placed at a predetermined position. A mounting table having a recess for fitting with the package to hold the same level; and a positioning pin provided on the mounting table for engaging with a frame for fixing the multilayer wiring ceramic substrate. An integrated circuit fixture characterized by.
る複数の集積回路パッケージを、それぞれ所定の位置
に、すべてのパッケージが同じ高さになるように保持
し、次いで、多層配線セラミック基板と各集積回路の半
田接合部を位置合わせした後当接させ、その後、半田を
リフローさせて多層配線セラミック基板に集積回路を実
装することを特徴とした集積回路の取付方法。2. A plurality of integrated circuit packages to be soldered to a multilayer wiring ceramic substrate are held at predetermined positions so that all packages have the same height, and then the multilayer wiring ceramic substrate and each integrated circuit package are held. A method for mounting an integrated circuit, characterized in that the solder joints of the circuit are aligned and brought into contact with each other, and then the solder is reflowed to mount the integrated circuit on the multilayer wiring ceramic substrate.
高さで半田付けされた集積回路の半田付け面と反対側の
面に対し、一定の微少間隔をあけて配設された平面部を
有する熱伝導ブロックと、前記集積回路と熱伝導ブロッ
クとの間の微少間隙に介在させたコンパウンドと、前記
熱伝導ブロックと当接するとともに、冷媒が流れる流路
を有するコールドプレートと、を具備することを特徴と
した集積回路の冷却器。3. A heat having flat portions arranged at a certain minute interval with respect to a surface opposite to a soldering surface of an integrated circuit which is all soldered at the same height on a multilayer wiring ceramic substrate. A heat conduction block; a compound interposed in a minute gap between the integrated circuit and the heat conduction block; and a cold plate that is in contact with the heat conduction block and has a flow path through which a refrigerant flows. And the integrated circuit cooler.
すべて同じ高さで半田付けし、該半田付けされた集積回
路の半田付け面と反対側の面に対し、一定の微少間隔を
あけて熱伝導ブロックを配設するとともに、集積回路と
熱伝導ブロックとの間の微少間隙にコンパウンドを介在
させ、熱伝導ブロックに冷媒が流れる流路を有するコー
ルドプレートを当接させて、集積回路の冷却を行なうこ
とを特徴とした集積回路の冷却方法。4. All of the integrated circuits are soldered on the multilayer wiring ceramic substrate at the same height, and heat is applied to the surface of the soldered integrated circuit opposite to the soldering surface at a certain minute interval. A cooling block is installed, a compound is interposed in the minute gap between the integrated circuit and the heat conduction block, and a cold plate having a flow path for the refrigerant is brought into contact with the heat conduction block to cool the integrated circuit. A method of cooling an integrated circuit characterized by carrying out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34008991A JPH05152473A (en) | 1991-11-29 | 1991-11-29 | Mounting and cooling methods for intergrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34008991A JPH05152473A (en) | 1991-11-29 | 1991-11-29 | Mounting and cooling methods for intergrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05152473A true JPH05152473A (en) | 1993-06-18 |
Family
ID=18333612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34008991A Pending JPH05152473A (en) | 1991-11-29 | 1991-11-29 | Mounting and cooling methods for intergrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05152473A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999016128A1 (en) * | 1997-09-19 | 1999-04-01 | Hitachi, Ltd. | Semiconductor module |
| JP2009053082A (en) * | 2007-08-28 | 2009-03-12 | Elpida Memory Inc | Apparatus and method for testing semiconductor |
| JP2015088556A (en) * | 2013-10-29 | 2015-05-07 | 富士電機株式会社 | Electronic module |
-
1991
- 1991-11-29 JP JP34008991A patent/JPH05152473A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999016128A1 (en) * | 1997-09-19 | 1999-04-01 | Hitachi, Ltd. | Semiconductor module |
| JP2009053082A (en) * | 2007-08-28 | 2009-03-12 | Elpida Memory Inc | Apparatus and method for testing semiconductor |
| JP2015088556A (en) * | 2013-10-29 | 2015-05-07 | 富士電機株式会社 | Electronic module |
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