JPH05151304A - Electronic circuit waveform analyzing device - Google Patents

Abstract

PURPOSE:To reduce an analytic manhour of simulation result data. CONSTITUTION:With regard to waveform group data 8 generated by simulation result data 5 and connecting information 6, a waveform analyzing means 1 generates automatically a waveform group data group 11. by a waveform grooping processing part 10 and displays it as a table. Also, by a hierarchization processing part 13, hierarchical waveform group data 14 is generated, and by a waveform selection processing part 16, waveform subgroup data 18 is generated and they are subjected to graph display in a lump, and an analysis is executed. In such a way, from among simulation result data of an electronic circuit being a largescale circuit, a waveform in an arbitrary circuit block is grouped and can be analyzed, and the analytic manhour can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a circuit simulation for simulating electric characteristics of an electronic circuit on a computer, and in particular, an electronic circuit waveform analysis for analyzing the electric characteristics of the simulation result as waveform data. Used for equipment.

[0002]

2. Description of the Related Art In the circuit design of an LSI (Large Scale Integrated Circuit), analyzing the electrical characteristics of a target circuit by electronic circuit simulation is an indispensable technique especially in the circuit design including an analog system.

Conventionally, two typical electronic circuit waveform analyzers for analyzing circuit simulation results are a conventional example (1) shown in FIG. 6 and a conventional example (2) shown in FIG.

FIG. 6 shows the simulation result data 5 obtained by the circuit simulator 22 as waveform analysis means 2.
The waveform display processing unit 24 in 3 simply displays a graph on the screen of the display 4b of the computer, which is simply a bitmap display, and the user uses the graph display command group 17 installed in the system to display the simulation result data 5 You can select the waveform in and change the scale of the graph.

On the other hand, in FIG. 7, the target circuit is graphically displayed by the circuit diagram editor 26 in the waveform analysis means 25, and the output variable designating section 27 designates the output variable on the circuit diagram. Information on nodes and branches corresponding to the specified variables is used as interprocess communication data 28, and the waveform display processing unit 2
4, the waveform display processing unit 24 extracts the waveform information of the output variable designated on the circuit diagram from the simulation result data 5 simulated by the circuit simulator 22 according to the instruction of the graph display command group 17, A graph is displayed on the screen of the display device 4b of the computer including a bitmap display. Compared to the case of the conventional example (1) of FIG. 6, in the case of the conventional example (2) of FIG. 7, output variables can be specified on the circuit diagram, so it is easier to identify the waveform displayed in the graph, but the circuit diagram editor 26 And the graph display command group 17 must operate in synchronization with each other. Also in the case of FIG. 7, it is usual that the scale of the displayed graph can be changed and the command input regarding the simple calculation function for the waveform can be performed by the graph display command group 17.

[0006]

In the above-mentioned conventional electronic circuit waveform analyzer, it is necessary to manually specify all the waveforms to be analyzed, so it is good for a small circuit, but a simulation result for a large circuit. When analyzing, there was a drawback in that much labor was required to display the required waveform. In the past, circuit simulation itself did not handle such a large circuit, but recently, due to advances in computer hardware and advances in simulation algorithms, circuit simulations of tens of thousands of transistors have become possible. .. Normally, the number of nodes of an electronic circuit is 1/2 to 1/3 of the number of transistors, and therefore, for example, a circuit of about 10,000 transistors has 30 nodes.
Since there are about 00 nodes, it is a difficult task to select a necessary waveform from these, and there is a drawback that the number of analysis steps is increased.

The method of selecting output variables on the circuit diagram as shown in FIG. 7 is effective when the circuit diagram does not have a hierarchical structure. However, a large-scale circuit diagram is usually created in a hierarchical manner, and in order to display the internal state of a circuit block in a specific hierarchy, it is necessary to trace the hierarchy in order from the top hierarchy. Therefore, in order to display the waveform across the layers, the work becomes rather complicated as compared with the method of FIG. 6, and there is a drawback that the number of analysis steps is increased.

The object of the present invention is to eliminate the above-mentioned drawbacks so that the waveform data in the required circuit block can be easily selected from the electronic simulation result data of a large-scale circuit and displayed in a graph for analysis. An object of the present invention is to provide an electronic circuit waveform analyzer that can reduce the number of analysis steps.

[0009]

According to the present invention, connection information of an electronic circuit and simulation result data including a group of nodal voltage waveforms and a group of branch current waveforms, which is performed based on this connection information, are inputted and an arbitrary circuit is inputted. In an electronic circuit waveform analysis device provided with a waveform analysis means for selectively displaying and displaying a waveform of a block, the waveform analysis means includes all nodes surrounded by arbitrary nodes on a designated circuit and a power supply and ground. Waveform grouping processing means for automatically grouping voltage waveforms and branch current waveforms to generate a waveform group data group, and the waveform group data group is further divided into subgroup data according to the structure of the circuit diagram to obtain structural waveform group data. Structured processing means to generate, and collectively for the specified waveform group data group or the structural waveform group data Characterized in that it comprises a waveform selection analysis means for performing view and analysis.

[0010]

The waveform grouping processing means automatically designates only major nodes in the circuit diagram, and automatically groups the relevant node voltage waveforms and branch current waveforms surrounded by the power source and ground. Create a waveform group data group and display it in a list. Then, the structuring processing means further subgroups the grouped waveform groups into hierarchical or output variables according to the connection information of the target circuit, and the waveform selection analysis means collectively collects each group waveform data or subgroup waveform data. Then, the data is displayed in groups and analyzed.

Therefore, it is possible to easily select the required waveform data in the circuit block from the electronic simulation result data of the large-scale circuit, display it in the form of a graph, and reduce the number of analysis steps. Become.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the essential parts of a first embodiment of the present invention.

In the first embodiment, the electronic circuit connection information 6
And the simulation result data 5 including the node voltage waveform group and the branch current waveform group, which are performed based on the connection information 6.
And a data input processing unit 7 for generating waveform group data 8 and selecting and displaying a waveform of an arbitrary circuit block for analysis, and an output device unit 4 including display devices 4a and 4b. In an electronic circuit waveform analyzing apparatus having the above, the waveform analyzing means 1 characterized by the present invention is provided.
Generates a waveform group data group 11 by automatically grouping all node voltage waveforms and branch current waveforms surrounded by any node on the circuit designated by the input / output node designating unit 9 and the power supply and the ground. The waveform grouping processing unit 10 as the waveform grouping processing unit, and the waveform group data group 11 are further divided into subgroups according to the hierarchical structure of the circuit diagram to generate the hierarchical waveform group data 14, and the list display instructing unit 12 gives an instruction. Output device section 4
The hierarchical processing unit 13 as a structured processing unit for displaying a list on the display 4a in the inside, and the waveform subgroup data 18 for the waveform group data group 11 or the hierarchical waveform group data 14 designated by the waveform selection unit 15. And a waveform selection processing section 16 as a waveform selection analysis processing means for collectively displaying a graph on the display 4b and performing analysis in accordance with an instruction of the graph display command group 17.

Here, the data input processing section 7, the waveform grouping processing section 10, the hierarchical processing section 13, and the waveform selection processing section 16 constitute the waveform analysis processing section 3, and the input / output node designating section 9, List display instruction unit 12, waveform selection unit 15,
The graph display command group 17 constitutes the user interface unit 2, and the user inputs these data.

Next, an outline of the operation of the first embodiment will be described with reference to the flow chart shown in FIG.

The simulation result data 5 and the connection information 6 obtained from a circuit simulator (not shown) are converted into hierarchically related waveform group data 8 by the data input processing unit 7 (step S1), and input / output is performed. The waveform grouping processing unit 10 groups each arbitrary node designated by the node designation unit 9 into a waveform group in a circuit surrounded by these input / output nodes, a power supply, and a ground, and a waveform group data group 11 is obtained. Created. Then, a list of waveforms included in each waveform group data group 11 is displayed on the display device 4a according to an instruction from the list display instruction unit 12 (step S2). Each waveform group data is processed by the hierarchical processing unit 13
Thus, it is converted into the hierarchical waveform group data 14 according to the hierarchical structure on the circuit connection (step S3). The waveform selection unit 15 selects only the required waveform from the hierarchical waveform group data 14 thus obtained, and the waveform selection processing unit 16 creates the waveform subgroup data 18, while the graph display command group is generated. The graph 17 displays a graph and changes the scale for each arbitrary waveform subgroup data 18 (step S4).

Next, the processing in the waveform grouping processing section 10 will be described in more detail. Now, assuming that a D-type flip-flop circuit as shown in FIG. 3A is present in the circuit diagram, it is considered to group the waveform data in the circuit surrounded by the input node IN and the output node OUT.

In this case, the nodes other than the power supply VDD and the ground GND connected to the adjacent elements are sequentially traced from the node IN, and a node group having the same number of adjacencies as the node OUT is found is one group. Can be defined. Here, the number of neighbors is defined as the minimum number of elements connecting one node to another node.

FIG. 3B is an explanatory diagram showing a correspondence table 30 of the number of adjacencies and the input / output nodes and power supplies of the circuit block of FIG. 3A. Although the example of FIG. 3 is a case where there is no feedback loop in the circuit block, the above-described waveform grouping processing unit 10 can be easily applied even when there is a feedback loop.

FIG. 4A shows a circuit block consisting of a CMOS operational amplifier, and FIG. 4B shows an input / output node and a power supply of a circuit surrounded by its input nodes IN1 and IN2 and an output node OUT. It is explanatory drawing which shows the correspondence table 31 with the adjacent number. In this case, all the nodes from the input node to the output node are covered with the number of adjacencies of 3,
One waveform group data group 11 can be formed by removing the duplicated waveform data from the waveform data group related to these nodes.

The above-mentioned waveform group data can be applied to any partial circuit on the circuit. However, when the partial circuit itself has a hierarchy, waveforms of all the layers below the partial circuit are assigned to one waveform group data, so that the grouping waveform group data group 11 is connected by the hierarchy processing unit 13 in FIG. The hierarchical waveform group data 14 is formed by sub-grouping according to the information hierarchy. Once the waveforms are grouped and hierarchical subgroups are processed in this manner, the waveform selection unit 15 or the graph display command group 17 in FIG. 1 can be processed in units of each group or subgroup. Therefore, the simulation result data of a large-scale circuit can be easily analyzed.

FIG. 5 is a block diagram showing the main part of the second embodiment of the present invention, showing the waveform analysis processing part. In the second embodiment, as shown in the figure, the input connection information 6a has the same partial circuits (X1, X2,
, XN) are connected.

The waveform analysis processing unit 3 of the second embodiment is shown in FIG.
In the waveform analysis processing unit 3 of the first embodiment, instead of the hierarchical processing unit 13 as a structuring processing unit, a waveform group data group 21 for each output variable, which is a feature of the present invention.
Is provided with a waveform sort processing unit 20.

Next, the operation of the second embodiment will be described mainly on the points different from the first embodiment.

After creating the waveform group data group 11 by the waveform grouping processing unit 10 for each partial circuit as in the first embodiment, the waveform sort processing unit 20 assigns the same node or branch to each waveform group. Only the corresponding waveforms are collected to create a new output variable-based waveform group data group 21. Waveform group data group 2 for each output variable
1 can be analyzed collectively by the waveform selection unit 15 and the graph display command group 17, as in the first embodiment.

In the circuit design, it is essential to confirm the circuit performance by repeatedly performing a plurality of simulations in which the element parameters and the circuit configuration are changed for a specific circuit block. According to the above, there is an advantage that the time and effort required for waveform analysis associated with such repeated simulation are almost the same as those required for one simulation.

[0028]

As described above, according to the present invention, by providing the main input / output nodes on the circuit diagram, the circuit simulation waveform in the circuit surrounded by these input / output nodes, the power supply, and the ground is automatically generated. Since it can be grouped into, the simulation result analysis of a large-scale circuit,
This has the effect of reducing the number of man-hours required to analyze a large number of simulation result data obtained by changing circuit parameters.

According to the conventional technique, the labor required for waveform analysis increases substantially in proportion to the circuit scale and the number of times of simulation repetition, but according to the present invention, the number of hierarchical partial circuit blocks included in the entire circuit is increased. , And does not depend much on the number of simulation iterations. For example, in the circuit design of a memory chip of the megabit class, a partial circuit block of about 100 elements is 20 to 200.
The circuit performance is optimized by repeating the circuit simulation of 2000 to 20000 elements made up of a plurality of times. Therefore, according to the present invention, it is estimated that the time and effort required for the waveform analysis can be reduced to about one tenth of the conventional one.
The effect is great.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation.

FIG. 3 is an explanatory diagram showing a circuit diagram showing an application circuit example (1) and a correspondence table thereof.

FIG. 4 is a circuit diagram showing an application circuit example (2) and an explanatory diagram showing a correspondence table thereof.

FIG. 5 is a block diagram showing a main part of a second embodiment of the present invention.

FIG. 6 is a block configuration diagram showing a main part of a conventional example (1).

FIG. 7 is a block configuration diagram showing a main part of a conventional example (2).

[Explanation of symbols]

 1, 23, 25 waveform analysis means 2 user interface section 3, 19 waveform analysis processing section 4 output device section 4a, 4b display 5 simulation result data 6, 6a connection information 7 data input processing section 8 waveform group data 9 input / output node Designating unit 10 Waveform grouping processing unit 11 Waveform group data group 12 List display instructing unit 13 Hierarchical processing unit 14 Hierarchical waveform group data 15 Waveform selecting unit 16 Waveform selecting processing unit 17 Graph display command group 18 Waveform subgroup data 20 Waveform Sort processing unit 21 Waveform group data group for each output variable 22 Circuit simulator 24 Waveform display processing unit 26 Circuit diagram editor 27 Output variable designation unit 28 Interprocess communication data 30, 31 Correspondence table S1 to S4 steps

Claims (1)

[Claims] 1. Input of connection information of an electronic circuit and simulation result data including a group of node voltage waveforms and a group of branch current waveforms, which is performed based on this connection information, and selectively displays and analyzes a waveform of an arbitrary circuit block. In an electronic circuit waveform analysis device having a waveform analysis means for performing the above, the waveform analysis means automatically calculates all node voltage waveforms and branch current waveforms surrounded by any node on the designated circuit and the power supply and ground. Waveform grouping processing means for generating a grouped waveform group data group, and structured processing means for further dividing the waveform group data group into subgroup data according to the structure of the circuit diagram to generate structural waveform group data, Waves that collectively display and analyze the specified waveform group data group or the structural waveform group data Electronic circuit waveform analyzer which comprises a selection analysis means.