JPH05150005A - Lsi tester with timing edge flexibility - Google Patents

Abstract

PURPOSE:To enable not only the execution of an automatically generated pattern but also the use of a complicated pattern outside of automatic generation and a test pattern with waveform by supplying each edge output to an input comparing means and a waveform generating means between adjacent channels. CONSTITUTION:An LSI tester is normally put in action in an ASIC mode. In the ASIC mode, a switch 24 is in the 'on' state, and switches 23, 25-27 are in the 'off' state. As a result, three edges are used for generating the waveform of a driver, and one edge is used for the strobing of data. In the ASIC mode, input-output pins 21, 22 are respectively put in independent action at high speed with a small number of edges. In a general purpose mode with the switch 24 in the 'off' state and the switches 23, 25-27 in the 'on' state, the inputoutput pins 21, 22 are put in action at low speed with a large number of edges compared to the ASIC mode. As a result, five edges can be used for generating the waveform of the driver, and two edges can be used for the strobing of the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an LSI tester, and more particularly to a high speed device test LSI tester in consideration of expanding an applicable range of a test application device.

[0002]

2. Description of the Related Art A conventional LSI tester is an ASIC (Applica
There is a high-speed limited specific application such as an inspection specific integrated circuit. For example, Hewlett
HP82000 from Packard, J95 from Teradyne
3 series etc. These LSI testers have the minimum required waveform generation function and can perform high-speed tests.

[0003]

However, the above-mentioned LSI
The main purpose of the tester is to execute a relatively simple pattern combination automatically generated by CAD (Computer Aided Design) data or a simulator.
Therefore, when an attempt is made to test a combination of patterns other than CAD data or the like, the edges for the format clocks that generate timing become insufficient, and it is necessary to rewrite the combination of patterns. For example, in FIG.
As shown in (A), when the same test cycle input / output is performed with three edges ((b) edge signal 1 to (d) edge signal 3 in FIG. 3 (A)) every test cycle, If one edge ((d) edge signal 3 in FIG. 3 (A)) is used as the strobe edge for detecting the output of the test device, the driver ON / OFF and the output waveform will have two edges (in FIG. 3 (A)). Only (b) edge signal 1 and (c) edge signal 2) can be used. Here, turn on the driver
/ OFF has one edge ((b) edge signal 1 in FIG. 3 (B)), and two edges ((c) edge signal 2 and (d) in FIG. 3 (B) to guarantee the effective range of data. Edge signal 3) If it is desired to use it, the strobe edge must be generated in the next test cycle, as shown in FIG. That is, the combination of patterns is shown in FIG.
It must be rewritten as shown in (B), and if there are many such test cycles in the entire test pattern, rewriting the combination of patterns is not easy. Therefore, an object of the present invention is not only to execute a pattern automatically generated by CAD or the like, but also to use a test pattern involving a complicated pattern or waveform other than automatic generation.
In the realization of the tester.

[0004]

In order to achieve such an object, according to the present invention, in an LSI tester of a per pin structure having a timing edge generator for each channel,
Waveform generating means for generating a waveform by the edge output of the timing edge generator, input comparing means for performing input comparison processing by the edge output of the timing edge generator, and each edge output between the adjacent channels The present invention is characterized by comprising switching means for supplying the input comparing means and the waveform generating means to each other, and storage means for supplying data to the input comparing means and the waveform generating means.

[0005]

By supplying each edge output to the input comparing means and the waveform generating means between channels, the number of usable edges of one supplied channel is increased. This edge enables generation of a complicated pattern or waveform.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram of a main part configuration showing portions of two adjacent channels in an embodiment of an LSI tester according to the present invention. In FIG. 1, 1 to 8 are delay generators, 9, 10
Is a pattern memory, 11 and 14 are waveform formatters, 1
2 and 15 are driver ON / OFF formatters, 1
Reference numerals 3 and 16 are comparator logics, 17 and 19 are drivers, 18 and 20 are comparator sections, 21 and 22 are input / output pins, and 23 to 26 are switches. 100 is a reference test rate signal from a rate generator (not shown), 101
Is a pattern address signal from a pattern address generator (not shown), and 102 and 103 are outputs to the fail memory.

Reference numerals 50 and 52 are waveform formatters 11 and 14, respectively, driver ON / OFF formatters 12 and 15, and waveform generating means comprising drivers 17 and 19, and 51 and 53 are comparator logic 1.
Input comparing means composed of 3 and 16 and comparators 18 and 20, 54 is switches 23, 24, 25, 26, 2
7 is a switching means. Here, the delay generator 1
To 4, the pattern memory 9 as the storage means, the waveform generation means 50, and the input comparison means 51 constitute one channel.

The delay generators 1 to 8 delay the reference test rate signal 100 from the rate generator by the value set by the program to generate the edges required for waveform generation and the like. The output edges of the delay generators 1, 2 and 5, 6 are supplied to the waveform formatters 11 and 14, respectively, as waveform generating edges. The output edge of the delay generator 3 is sent to the driver ON / OFF formatter 12 via the switch 24, and the output edge of the delay generator 7 is sent to the driver ON / O.
The FF formatter 15 includes drivers 17 and 19 respectively.
It is supplied as an ON / OFF edge. The output edges of the delay generators 4 and 8 are supplied to the comparator logics 13 and 16, respectively, as data strobe edges. The output edge of the delay generator 3 is the switch 2
3 to the waveform formatter 11, the output edges of the delay generators 5 and 6 to the driver ON / OFF formatter 12 via the switches 26 and 27, respectively, and the output edge of the delay generator 8 to the comparator via the switch 25. It is connected to the logic 13.

The pattern memories 9 and 10 store pattern data, which is data such as generated waveforms designated by the pattern address signal 101 from the pattern address generator, in the waveform formatters 11 and 14, and driver ON / OFF.
Formatters 12 and 15, comparator logic 1
3 and 16 respectively.

The waveform outputs of the waveform formatters 11 and 14 are input to the drivers 17 and 19, and the driver ON / O
Under the control of the FF formatters 12 and 15, the signals are output from the drivers 17 and 19 to the input / output pins 21 and 22, respectively. The input data from the input / output pins 21 and 22 is taken into the comparator units 18 and 20 by the control of the comparator logics 13 and 16 and compared with the expected value, and if there is an abnormality, it is output to the fail memory.
02 and 103 are output.

The operation of the LSI tester shown in FIG. 1 will be described below. This LSI tester has four timing edges and is usually an ASIC in the table shown in FIGS. 2 (A) and 2 (B).
Operating in mode. Switch 2 in ASIC mode
4 is on and switches 23, 25, 26 and 27 are off. As a result, three edges are used for waveform generation of the driver and one edge is used for data strobe. In the ASIC mode, the input / output pins 21 and 22 operate independently with a high speed and a small number of edges. Here, output (NRZ), output (P, N), input, or input / output is selected for each test cycle. Here, in the tables shown in FIGS. 2A and 2B, NRZ is “Non Return Zero”,
RZ is "Return Zero", P is "Positive Pulse", N is "Ne"
gative Pulse ", STB" Strobe ", DRE" Driver E "
nable ". RZ and DRE endings with" L "and"
"T" indicates "Leading" and "Trailing". For example, RZ
Is "Positive Pulse", it means that the edge signal of RZL becomes high level and the edge signal of RZT becomes low level. The subscripts “# 1” and “# 2” indicate edge signals that can be used by the input / output pins 21 and 22.

As can be seen from the tables shown in FIGS. 2A and 2B, in the ASIC mode, 4 edges are used when the input / output test cycle is selected, and only 1 or 2 edges are used when the input and output test cycles are divided. Can not. For this reason,
For example, a window strobe for confirming that the waveform logic of a certain duration does not change while using two edges as timing edges cannot be performed because the strobe edge is one edge. Further, since the 3 edges are for waveform generation of the driver, the RZ signal cannot be generated for the DRE signal in the same test cycle.

Here, the switch 24 is turned off and the switches 23, 25, 26 and 27 are turned on to set the general mode. The general-purpose mode operates at a low speed and a large number of edges, as compared with the ASIC mode. That is, the output edge of the delay generator 3 is sent to the waveform formatter 11 via the switch 23, and the output edge of the delay generator 5 is sent to the driver O via the switch 26.
The output edge of the delay generator 6 is supplied to the driver ON / OFF formatter 12 via the switch 27, and the output edge of the delay generator 8 is supplied to the comparator logic 13 via the switch 25. It As a result, 5 edges can be used for driver waveform generation, and 2 edges can be used for data strobe. However, since the input / output pin 22 of the input / output pins 21 and 22 supplies the edge signal of the input / output pin 22 for the input / output pin 21, it cannot be used.

In the general mode, seven edges can be used as shown in the tables of FIGS. 2A and 2B. Here, since the strobe edges are 2 edges, the window strobe is enabled, and the driver waveform generation is 5
Since it is an edge, it is possible to generate the RZ signal for the DRE signal in the same test cycle. Further, since the seven edges can be individually selected, it is possible to deal with complicated patterns other than automatic generation and test patterns with waveforms.

The above-mentioned general mode and ASIC mode can be mixed. Therefore, the channel that can be tested with the pattern generated automatically is ASIC mode,
By using the general-purpose mode for a channel that requires a test using a complicated pattern, it is possible to perform an efficient test while avoiding an unnecessary decrease in the channel and a decrease in speed. Further, in the embodiment shown in FIG. 1, the edge signals are exchanged between the two adjacent channels, but the invention is not limited to this.

[0016]

As is clear from the above description,
The present invention has the following effects. That is, by using the edge signal of the adjacent channel, not only is a relatively simple pattern automatically generated by CAD or the like executed,
Test patterns with complicated patterns or waveforms other than automatically generated can be used without modification. In addition, since the target device is not always a high-speed multi-pin, the LSI tester can be easily diverted due to production reasons, and the expensive assets can be effectively used.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part configuration showing portions of two adjacent channels in an embodiment of an LSI tester according to the present invention.

FIG. 2 is a table showing an example of distribution of edge signals of two adjacent channels in FIG.

FIG. 3 is a timing chart showing an operation example of a conventional LSI tester.

[Explanation of symbols]

 1, 2, 3, 4, 5, 6, 7, 8 Delay generator 9, 10 Pattern memory 11, 14 Waveform formatter 12, 15 Driver ON / OFF formatter 13, 16 Comparator logic 17, 19 Driver 18, 20 Comparator Parts 21, 22 Input / output pins 23, 24, 25, 26, 27 Switches 50, 52 Waveform generating means 51, 53 Input comparing means 54 Switching means 100 Reference test rate signal 101 Pattern address signal 102, 103 Output

Claims (1)

[Claims] 1. A per-pin structure LSI tester having a timing edge generator for each channel, wherein waveform generating means for generating a waveform by an edge output of the timing edge generator, and input by an edge output of the timing edge generator Input comparing means for performing the comparison processing of 1., switching means for supplying each edge output between the adjacent channels to the input comparing means and the waveform generating means, and data for the input comparing means and the waveform generating means. An LSI tester comprising a storage means for supplying.