JPH05145376A - Digital filter - Google Patents

Abstract

PURPOSE:To reduce missing of small signal information due to a limited word length by adding a dither signal to an input signal in the case of quantization processing so as to round up low-order prescribed bits. CONSTITUTION:A digital filter 51 is formed by sequentially connecting a filter processing circuit 52, an internal processing circuit 543 and an output processing circuit in cascade. The circuit 52 adds dither data DZ1 to audio input data. The circuit 53 (54) is provided with a dither adder circuit 71(72) simultaneously to add dither data DZ2 and DZ3 to the input data. The data DZ1, DZ2, DZ3 are compared with input data to dither adder circuits 61-68, 71 and 72, and the result has a prescribed amplitude and a frequency within a prescribed frequency range and consists of noise whose amplitude and frequency change at random. The filter 51 implements quantization attended with 4-bit round-off processing to the result of dither addition by the circuits 52, 63, 64. Thus, the digital filter whose reproducibility is excellent is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter, and more particularly to a digital filter for minimizing the loss of information of a minute signal.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 7, a digital filter 1, a filter processing circuit 2 and an internal processing circuit 3 are used.
And the output processing circuit 4 is, for example, an LSI (Large Scale Integrated Circuit)
It is proposed that it is configured in the chip. The filter processing circuit 2 includes a shift register 11 having a plurality of stages, for example, eight stages.
Data input signal S obtained by sampling, for example, an analog audio signal at a predetermined sampling frequency through the input terminal 20 to the first stage shift register 11
IN is input.

The shift registers 11 to 18 perform a shift operation by a clock signal having a frequency equal to the sampling frequency of the data input signal SIN, and thus the delay outputs S1 to S1 obtained at the output ends of the shift registers 11 to 18 of each stage. S8 is multiplied by the filter coefficients h1 to h8 in the filter coefficient multiplication circuits 21 to 28.

The multiplication outputs S11 to S18 of the filter coefficient multiplication circuits 21 to 28 are quantized by the quantization circuits 31 to 38, and then supplied to the accumulator 39. The accumulator 39 adds the quantized data S21 to S28 of the quantizers 31 to 38 to the adder circuit 41 of the accumulator 39.
.. to 47, the addition output S41 of the addition circuit 47 is sent to the internal processing circuit 3 as the filter output of the filter processing circuit 2.

Thus, the filter processing circuit 2 forms an FIR digital filter,

[Equation 1] Input time series data Xi-j
The output time series data Yi is obtained by convoluting the impulse response with. Here, hj (j = 0 to 7) is a filter coefficient, and N is the tap number (N = 8 in the case of FIG. 7).

[0006]

However, when the conventional digital filter 1 shown in FIG. 7 is actually constructed in a chip of an LSI (Large Scale Integrated Circuit), it has a functional configuration as shown in FIG. Then, the word length of the quantized data obtained at the time of performing the quantization processing is limited as necessary.

That is, in the filter processing circuit 2,
In the filter coefficient multiplier MLT (21 to 28), the input data D (S1 to S8) and the coefficient data D (h1 to h) are input.
8) Multiplication result data D obtained by multiplying by
(S11 to S18) are quantization circuits QNT1 (31 to 3).
8) after being quantized in Acumulator ACM
Cumulative addition is performed at (41 to 47).

The cumulative addition result data D (S31) is quantized in the quantizing circuit QNT2 of the internal processing circuit 3 and then sent to the internal bus INB, and output data D (OUT) obtained via the internal bus INB. Is the output processing circuit 4
After being quantized in the quantizing circuit QNT3, it is sent to the external hardware OHW.

Here, each quantization circuit QNT1 (31 to 3)
8), QNT2 and QNT3 are multiplication result data D (S11 to S18) and cumulative addition result data D (S3, respectively).
1) and word length limiting processing is performed in order to match the number of bits of the output data D (OUT) with the number of allowable bits of the processing circuit in the subsequent stage.

For example, the first quantization circuit QNT1 (31-31)
38), multiplication result data D (S11 to S18)
In order to obtain highly accurate data, the calculation is performed so as to obtain a result of a bit number larger than the allowable input bit number of the accumulator ACM (41 to 47), and the quantization circuit QNT1 rounds off a predetermined lower bit number or By performing the truncation process, the accumulator A
The word length is limited so as to match the number of input allowable bits of CM (41 to 47).

This accumulator ACM (41-47)
By performing the cumulative addition operation on a large number of input signals, the number of bits of the operation result data D (S31) becomes larger than the number of allowable inputs of the internal bus INB. The second quantization circuit QNT2 limits the word length to the number of allowable input bits of the internal bus INB by rounding or truncating the predetermined lower bit number of the operation result data D (S31).

Thus, when the number of bits of the output data D (OUT) obtained through the internal bus INB becomes larger than the allowable number of bits of the external hardware OHW, the third quantizing circuit QNT3 determines the predetermined value of the output data D (OUT). By rounding or truncating the data with respect to the lower order bit number of, the word length is limited to the allowable number of bits of the external hardware OHW.

Thus, the conventional digital filter is L
When configured in SI, each quantization circuit QN may be used as necessary.
It is necessary to round the quantized data by rounding or truncating the data in T1, QNT2 and QNT3, and the information of the minute signal is quantized in the quantizing circuit QNT1, QNT2 or QNT3 for the rounding process. There is a problem of missing every time.

For example, as shown in FIG. 9, an accumulator A
The calculation result data D (S31) of the CM (41 to 47) is 24
It is a minute sine wave signal having a word length of a bit, and when the sine wave signal is quantized in the quantizer QNT2, it is adapted to the allowable number of bits of the internal bus INB.
When the word length is limited to 20 bits and the quantization levels L1 and L2 are rounded off, the quantized data D (QNT1) 1 is accumulated operation result data D centered on the "0" level as shown by the broken line. In the cycle of (S31), the rectangular wave changes.

On the other hand, when the quantizing circuit QNT2 performs the truncation process, the quantized data D (QNT2) 2 of the quantizing circuit QNT2 has its midpoint offset to a signal level lower than "0" level as shown by the solid line. It exhibits a rectangular waveform change.

As described above, the conventional digital filter is
When limiting the word length by rounding or truncation processing when quantizing data, the information included in the minute signal is compared with the minute signal before quantization having a substantially sine wave shape. Due to the lack, there is a problem that reproducibility is deteriorated such that the waveform becomes a rectangular wave or the level is shifted.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a digital filter capable of further reducing the loss of information of a minute signal caused by word length limitation.

[0018]

In order to solve such a problem, according to the present invention, the delays obtained from the stages of the shift registers 11 to 18 in the multiplication circuits 21 to 28 based on the data input signals D (S1 to S8). After the outputs S1 to S8 are multiplied by the filter coefficients h1 to h8, the quantization circuits 31 to
In the digital filter 51, which is adapted to obtain the filter output S31 by performing quantization and word length limitation in 38 and then performing cumulative addition in the cumulative addition circuit 39, the dither addition circuit 6 is provided after the multiplication circuits 21 to 28.
1 to 68 are provided, the dither signal DZ1 is added to the multiplication outputs of the dither addition circuits 61 to 68, and the addition outputs S41 to S48 are given to the quantization circuits 31 to 38.

[0019]

When the quantizing circuits 31 to 38 perform the quantizing processing, the dither signals DZ1 are added by the dither adding circuits 61 to 68, so that the dither signal D
Even if the predetermined lower number of bits is rounded down or rounded after Z1 is quantized, the information contained in the minute signal of the input signal remains in the quantized data. Thus, a digital filter having excellent reproducibility can be easily realized.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1 in which parts corresponding to those in FIG. 7 are designated by the same reference numerals, a digital filter 51 has a structure in which a filter processing circuit 52, an internal processing circuit 53 and an output processing circuit 54 are sequentially connected in series.

The filter processing circuit 52 has the same structure as the dither adder circuits 61 to 68 are inserted at the output terminals of the filter coefficient multiplication circuits 21 to 28 of the filter processing circuit 2 of FIG. The dither data DZ1 is added to the audio input data of 2.

At the same time, the internal processing circuit 53 and the output processing circuit 54 are provided with dither addition circuits 71 and 72, respectively, whereby the input data of the internal processing circuit 53 and the output processing circuit 54 are dither data DZ2 and DZ.
Z3 is added respectively.

Here, the dither data DZ1, DZ2 and D
Z3 is, as shown in FIG. 2, dither adder circuits 61 to 68,
Compared with the input data 71 and 72, it has a predetermined amplitude, for example, a maximum amplitude corresponding to the lower 4 bits and a frequency within a predetermined frequency range, and is composed of noise whose amplitude and frequency distribution change randomly. .. In the digital filter 51 of FIG. 1, the filter processing circuit 52, the internal processing circuit 53, and the output processing circuit 54 each perform the processing shown in FIG.

In the digital filter processing circuit 52, coefficient data D (h1 to h8) is applied to the 16-bit input data D (S1 to S8) in the multiplier MLT (21 to 28).
Is multiplied by. Thus, the multiplication result data D (S11 to S1
8) is obtained, which is the dither adder circuit ADD1 (61 to 61).
In 68), 4-bit dither data DZ1 is added and supplied to the quantizing circuit QNT1.

Here, the quantizing circuit QNT1 is based on that the accumulator ACM (41 to 47) has a word length of a predetermined number of bits, and the quantized data D (QNT1) obtained by truncating the lower 4 bits is stored in the accumulator ACM ( 41
~ 47).

Since the dither data DZ1 has the maximum amplitude of the lower 4 bits as described above with reference to FIG. 2, when the value of the input data D (S1 to S8) is 0 (that is, when there is no signal), the dither adder circuit ADD1 ( 61 to 68), only the dither data DZ1 is supplied to the quantizing circuit QNT1, so that the quantizing circuit QNT1 generates an offset when the lower 4 bits are truncated as shown in FIG. , The noise of one bit width of the least significant bit is supplied to the accumulator ACM (41 to 47).

However, in this state, the input data D
As (S1 to S8), as described above with reference to FIG.
When a sine wave signal of 100 [Hz] of -115 [dB] is supplied from full scale, the dither adder ADD1 (61 to 6)
At the output end of 8), as shown in FIG. 5, a waveform similar to that obtained by modulating the dither data signal DZ1 with the minute sine wave signal is obtained.

The quantizing circuit QNT1 quantizes such a waveform and discards the lower 4 bits, and as a result, quantized data D (QNT1) as shown in FIG. 6 is obtained. Here, the quantized data D (QNT1) shown in FIG. 6 is different from the case where the lower 4 bits are simply truncated as described above with reference to FIG.
The lowest 1 when the data of 18) is no signal (0 data)
The waveform is such that bit noise (FIG. 4) is modulated by a minute sine wave (FIG. 9).

If this waveform is compared with the waveform of FIG. 9, the addition output data D of the adder adder circuit ADD1 (61 to 68) is added.
When (S41 to S48) crosses the quantization level, since the dither data DZ1 is added, the quantized data based on the dither data that transitions by one bit width has one bit width so as to sandwich the quantization level. The data will change with.

Thus, even when the quantized data for the minute sine wave signal is quantized while the lower 4 bits are truncated, the signal level is set so as to follow the change of the minute sine wave signal based on the dither signal. Due to the superposition of the signal components in which the data level transitions relatively finely, the accumulator ACM (4
1 to 47). According to the above configuration, the audio input signal can be filtered with good reproducibility, whereby a digital filter with much better sound quality can be obtained.

The quantizing operation accompanied by the 4-bit truncation processing for the dither signal addition result as described with reference to FIGS. 3 to 6 is performed on the addition output data of the dither data addition circuits 71 and 72 of the internal processing circuit 53 and the output processing circuit 54. Is also performed in the same manner, and thus, in this case as well, the quantization process for limiting the word length can be performed by performing the truncation process of the lower 4 bits without losing the minute information.

In the above-mentioned embodiment, the embodiment in which the dither data having the maximum amplitude of 4 bits is applied has been described, but the number of bits can be selected as required, and the important point is the dither data. The amplitude of is to be selected as the number of rounded bits at the time of quantization.

Further, in the case of the above-mentioned embodiment, the case where the word length is limited by truncating the quantized data of the predetermined lower bit number in the quantization processing has been described.
Alternatively, the present invention can be widely applied to the case where the quantized data having the predetermined lower number of bits is rounded to limit the word length.

[0035]

As described above, according to the present invention, when the input data is quantized, the dither signal is added in advance, so that the lower predetermined number of bits is rounded during the quantization process. Thus, even when the word length is limited, it is possible to easily realize a digital filter which is further excellent in reproducibility and which does not lose minute information.

[Brief description of drawings]

FIG. 1 is a connection diagram showing a digital filter according to the present invention.

FIG. 2 is a signal waveform diagram showing a dither signal.

FIG. 3 is a system diagram showing processing functions of each unit in FIG.

FIG. 4 is a signal waveform diagram showing a waveform of data obtained as a result of encoding a dither signal and truncating lower bits.

FIG. 5 is a signal waveform diagram showing an addition output obtained by adding a dither signal to a minute sine wave signal.

FIG. 6 is a signal waveform diagram showing a processing result obtained by performing quantization and truncation processing on the signal of FIG.

FIG. 7 is a connection diagram showing a configuration of a conventional digital filter.

8 is a system diagram showing in detail the function of each part of FIG.

FIG. 9 is a signal waveform diagram for explaining a case where a minute sine wave signal is quantized and truncated according to the configuration of FIG.

[Explanation of reference numerals] 11-18 ... Shift register, 21-28 ... Multiplier circuit, 31-38 ... Quantizer circuit, 39 ... Acumulator, 41-47 ... Adder circuit, 51 ... Digital filter, 52 ... filter processing circuit, 53 ... internal processing circuit, 54 ... output processing circuit, 61-68 ... dither data addition circuit.

Claims (3)

[Claims] 1. A multiplier circuit multiplies a delay output obtained from each stage of a shift register based on a data input signal by a filter coefficient, and then a quantizer circuit quantizes and limits a word length, and then a cumulative addition circuit. In a digital filter adapted to obtain a filter output by performing cumulative addition in, a first dither addition circuit is provided at a stage subsequent to the multiplication circuit, and the first dither addition circuit is provided with respect to the multiplication output of the multiplication circuit. A digital filter characterized by adding dither signals and applying the addition output to the quantizing circuit. 2. A second dither addition circuit is provided at a stage subsequent to the cumulative addition circuit, wherein the second dither addition circuit adds a second dither signal to a cumulative addition output of the cumulative addition circuit, and then a second dither signal is added. 2. The digital filter according to claim 1, wherein the quantizing circuit according to claim 1 performs quantization and word length limitation and supplies it to an internal bus. 3. Output data obtained from the internal bus is added to a third dither signal in a third dither adder circuit, and then quantized and word length is limited in the third quantizer circuit. 3. The digital filter according to claim 2, wherein the digital filter is sent as.