JPH05144869A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05144869A JPH05144869A JP3307430A JP30743091A JPH05144869A JP H05144869 A JPH05144869 A JP H05144869A JP 3307430 A JP3307430 A JP 3307430A JP 30743091 A JP30743091 A JP 30743091A JP H05144869 A JPH05144869 A JP H05144869A
- Authority
- JP
- Japan
- Prior art keywords
- gold wire
- semiconductor device
- chip
- die pad
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000011347 resin Substances 0.000 claims abstract description 14
- 229920005989 resin Polymers 0.000 claims abstract description 14
- 239000010931 gold Substances 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 238000000465 moulding Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に係り、特
に薄型パッケージの半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a thin package semiconductor device.
【０００２】[0002]
【従来の技術】図３は従来の薄型パッケージの半導体装
置を示す断面図であり、この図において、１はＩＣリー
ドフレームのダイパッド、２はこのダイパッド１に装着
されたＩＣチップ、３はＩＣリードフレームのリード、
４は前記ＩＣチップ２とリード３を接続する金線、５は
成形されたモールド樹脂である。2. Description of the Related Art FIG. 3 is a sectional view showing a conventional semiconductor device in a thin package, in which 1 is a die pad of an IC lead frame, 2 is an IC chip mounted on the die pad 1, and 3 is an IC lead. Frame leads,
Reference numeral 4 is a gold wire connecting the IC chip 2 and the lead 3, and reference numeral 5 is a molded resin.
【０００３】上記従来の半導体装置は、ＩＣリードフレ
ームのダイパッド１を所定の位置まで沈め、その上にＩ
Ｃチップ２を装着する。次に、ＩＣリードフレームのリ
ード３とＩＣチップ２のボンディングパッド部を金線４
により接続する。次に、前記ダイパッド１，ＩＣチップ
２，リード３，および金線４をモールド樹脂５によりト
ランスファー成形することにより構成される。In the conventional semiconductor device described above, the die pad 1 of the IC lead frame is sunk to a predetermined position, and I is placed thereon.
Attach C-tip 2. Next, the lead 3 of the IC lead frame and the bonding pad portion of the IC chip 2 are connected to the gold wire 4.
To connect. Next, the die pad 1, the IC chip 2, the leads 3, and the gold wire 4 are formed by transfer molding with a molding resin 5.
【０００４】[0004]
【発明が解決しようとする課題】上記のような従来の半
導体装置では、ＩＣチップ２とモールド樹脂５表面の寸
法およびダイパッド１とモールド樹脂５下面の寸法が小
さいため、金線４がモールド樹脂５表面より図示のよう
に露出してしまったり、また、図示はしていないがダイ
パッド１がモールド樹脂５下面より露出するなどの問題
点があった。In the conventional semiconductor device as described above, since the dimensions of the IC chip 2 and the surface of the molding resin 5 and the dimensions of the die pad 1 and the lower surface of the molding resin 5 are small, the gold wire 4 is the molding resin 5. There is a problem that it is exposed from the surface as shown in the figure, and although not shown, the die pad 1 is exposed from the lower surface of the mold resin 5.
【０００５】本発明は、上記のような問題点を解消する
ためになされたもので、金線の露出およびダイパッドの
露出のない半導体装置を提供することを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device in which the gold wire is not exposed and the die pad is not exposed.
【０００６】[0006]
【課題を解決するための手段】本発明に係る半導体装置
は、金線が接続されるＩＣチップのボンディングパッド
部とリードとの段差を小さくして金線を接続し、樹脂モ
ールドしたものである。A semiconductor device according to the present invention is formed by resin-molding by connecting a gold wire while reducing a step between a bonding pad portion of an IC chip to which the gold wire is connected and a lead. .
【０００７】[0007]
【作用】本発明においては、ＩＣチップのボンディング
パッド部とリードとの段差が小さくなることから金線を
接続し、樹脂モールドした場合、金線およびダイパッド
とモールド樹脂の上下面との間にそれぞれ一定の距離が
保たれ、金線の露出やダイパッドの露出が低減できる。In the present invention, since the step between the bonding pad portion of the IC chip and the lead becomes small, when the gold wire is connected and resin-molded, the gold wire and the die pad are respectively interposed between the upper surface and the lower surface of the molding resin. A certain distance is maintained, and the exposure of gold wire and die pad can be reduced.
【０００８】[0008]
【実施例】以下、本発明の一実施例を図について説明す
る。図１は本発明の半導体装置の一実施例を示す断面図
である。図１において、図３と同一符号は同一部分を示
すが、この実施例ではＩＣチップ２のボンディングパッ
ド部に段差部２ａを形成してボンディングパッド部とリ
ード３との段差を従来より小さくしてある。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention. In FIG. 1, the same reference numerals as those in FIG. 3 indicate the same portions, but in this embodiment, a step portion 2a is formed in the bonding pad portion of the IC chip 2 so that the step between the bonding pad portion and the lead 3 is made smaller than before. is there.
【０００９】また、図２に示す実施例は、ＩＣリードフ
レームのダイパッド１のＩＣチップ２が装着される部分
の厚みを薄くして凹部１ａを形成したものであり、その
他は図１と同じものである。In the embodiment shown in FIG. 2, the thickness of the portion of the die pad 1 of the IC lead frame on which the IC chip 2 is mounted is reduced to form the recessed portion 1a. Others are the same as those in FIG. Is.
【００１０】図１の半導体装置は、ＩＣリードフレーム
のダイパッド１上に装着されたＩＣチップ２のボンディ
ングパッド部のウエハ厚を薄くして段差部２ａとし、こ
の段差部２ａとリード３との間を金線４により接続し、
樹脂モールドする。この時、ボンディングパッド部であ
る段差部２ａとリード３との段差は極めて小さくなり、
モールド樹脂５上面と金線４間は一定の距離が保たれて
いる。In the semiconductor device of FIG. 1, the wafer thickness of the bonding pad portion of the IC chip 2 mounted on the die pad 1 of the IC lead frame is reduced to a step portion 2a, and between the step portion 2a and the lead 3. Is connected by a gold wire 4,
Mold with resin. At this time, the step between the step portion 2a which is the bonding pad portion and the lead 3 becomes extremely small,
A constant distance is maintained between the upper surface of the molding resin 5 and the gold wire 4.
【００１１】また、図２の半導体装置は、ダイパッド１
の凹部１ａにＩＣチップ２を装着することにより、ＩＣ
チップ２とリード３との段差が小さくなり、この間に金
線４を接続することにより、図１の実施例と同様に金線
４とモールド樹脂５の上面との間に一定の距離が保たれ
る。したがって、両実施例とも金線４およびダイパッド
１とモールド樹脂５の上面および下面との距離が大きく
とれることから金線４およびダイパッド１の露出を低減
できる。The semiconductor device shown in FIG. 2 has a die pad 1
By mounting the IC chip 2 in the recess 1a of the
The step between the chip 2 and the lead 3 becomes smaller, and by connecting the gold wire 4 between them, a constant distance is maintained between the gold wire 4 and the upper surface of the molding resin 5 as in the embodiment of FIG. Be done. Therefore, in both of the embodiments, the distance between the gold wire 4 and the die pad 1 and the upper surface and the lower surface of the molding resin 5 can be set large, so that the exposure of the gold wire 4 and the die pad 1 can be reduced.
【００１２】[0012]
【発明の効果】以上説明したように、本発明は、金線が
接続されるＩＣチップのボンディングパッド部と、リー
ドとの段差を小さくして金線を接続し、樹脂モールドし
たので、モールド成形されたパッケージからの金線の露
出およびダイパッドの露出が低減できる効果がある。As described above, according to the present invention, the gold wire is connected and resin-molded by reducing the step between the bonding pad portion of the IC chip to which the gold wire is connected and the lead. There is an effect that the exposure of the gold wire and the exposure of the die pad from the formed package can be reduced.
【図１】本発明の半導体装置の一実施例を示す断面図で
ある。FIG. 1 is a sectional view showing an embodiment of a semiconductor device of the present invention.
【図２】本発明の他の実施例を示す断面図である。FIG. 2 is a sectional view showing another embodiment of the present invention.
【図３】従来の半導体装置の一例を示す断面図である。FIG. 3 is a sectional view showing an example of a conventional semiconductor device.
１ ダイパッド １ａ 凹部 ２ ＩＣチップ ２ａ 段差部 ３ リード ４ 金線 ５ モールド樹脂 1 Die Pad 1a Recess 2 IC Chip 2a Step 3 Lead 4 Gold Wire 5 Mold Resin
Claims (1)
着されたＩＣチップのボンディングパッド部と、このボ
ンディングパッド部と前記ＩＣリードフレームのリード
との間を金線により接続して樹脂モールドした半導体装
置において、前記ＩＣチップのボンディングパッド部
と、前記リードとの段差を小さくして前記金線により接
続し、樹脂モールドしたことを特徴とする半導体装置。1. A semiconductor device in which a bonding pad portion of an IC chip mounted on a die pad of an IC lead frame and a resin wire molded between the bonding pad portion and the lead of the IC lead frame are connected by a gold wire. The semiconductor device is characterized in that the bonding pad portion of the IC chip and the lead are reduced in level difference and connected by the gold wire, and resin-molded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3307430A JPH05144869A (en) | 1991-11-22 | 1991-11-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3307430A JPH05144869A (en) | 1991-11-22 | 1991-11-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05144869A true JPH05144869A (en) | 1993-06-11 |
Family
ID=17968973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3307430A Pending JPH05144869A (en) | 1991-11-22 | 1991-11-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05144869A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7012325B2 (en) * | 2001-03-05 | 2006-03-14 | Samsung Electronics Co., Ltd. | Ultra-thin semiconductor package device and method for manufacturing the same |
-
1991
- 1991-11-22 JP JP3307430A patent/JPH05144869A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7012325B2 (en) * | 2001-03-05 | 2006-03-14 | Samsung Electronics Co., Ltd. | Ultra-thin semiconductor package device and method for manufacturing the same |
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