JPH05144843A - Field-effect transistor - Google Patents

Abstract

(57) [Abstract] [Purpose] GaAs MESFET or heterojunction FE
A device structure capable of increasing the drain breakdown voltage by reducing the source parasitic resistance and drain capacitance of T. [Structure] In a field effect transistor in which an ohmic layer 3 is formed by a selective epitaxial growth method, a source-side ohmic layer 3 is provided adjacent to a channel layer, and a drain-side ohmic layer 3 is provided on a channel layer. [Effect] By providing the ohmic layer on the source side adjacent to the channel layer, the parasitic resistance can be reduced, and by providing the ohmic layer on the drain side on the channel layer, the capacitance can be reduced and the drain breakdown voltage can be improved. it can.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a field effect transistor having high performance and high reliability.

[0002]

2. Description of the Related Art When a high-concentration semiconductor conductive layer is formed by an epitaxial growth method, the carrier concentration can be made higher than when it is formed by an ion implantation method, so that the sheet resistance can be reduced. Therefore, when the ohmic layer of the field effect transistor (FET) is formed by the epitaxial growth method, the source parasitic resistance (Rs) can be made smaller than when it is formed by the ion implantation method.
It is possible to increase the conductance (gm).

FIG. 3 shows a conventional example in which an ohmic layer of a Schottky junction gate FET is formed by an epitaxial growth method. FIG. 3A shows a case where an ohmic layer is provided on a channel layer, which is formed by processing a high-concentration conductive layer continuously grown on the channel layer, or an exposed channel surface. It is formed by selectively growing a high-concentration conductive layer.

FIG. 3B shows a case where the ohmic layer is provided adjacent to the channel layer so that the ohmic layer is connected from the side surface of the channel layer. The ohmic layer is formed by etching the side of the channel layer and selectively growing a high-concentration conductive layer on the exposed substrate. To reduce the number of manufacturing processes,
In both cases, the source side and drain side ohmic layers are usually formed at the same time, but it is generally preferable to increase the impurity concentration of the source side ohmic layer in order to reduce parasitic resistance, and to secure the gate breakdown voltage on the drain side. It is preferable to suppress the impurity concentration in order to reduce the parasitic capacitance.

Therefore, it is necessary to determine the optimum value of the impurity concentration of the ohmic layer in consideration of improving the device performance by reducing the parasitic resistance and ensuring the reliability of the device.

[0006]

Normally, the sheet resistance of the channel layer is several kΩ / b, which is about two orders of magnitude higher than that of the ohmic layer, so that the Rs of the FET is controlled by the length of the current path in the channel layer portion. To be done. The structure of FIG. 3 (a) is
Since the length of the current path in the channel layer portion is larger than that in the structure (b) in which the ohmic layer is adjacent to the channel, R
s becomes large. Therefore, the structure of FIG. 3A has a problem that the FET performance is smaller than that of the structure of FIG. On the other hand, in the structure of FIG. 3B, there is a problem that the high-concentration donor impurity in the ohmic layer diffuses laterally, which causes an increase in gate capacitance and a decrease in gate breakdown voltage.

It is an object of the present invention to solve this problem and provide a high performance and highly reliable device structure.

[0008]

In order to achieve high performance of the device, a method of providing the ohmic layer on the source side adjacent to the channel layer is adopted to reduce Rs.

In order to achieve high reliability of the device,
The ohmic layer on the drain side is provided on the channel layer to suppress the lateral diffusion of impurities from the ohmic layer to the channel to reduce the gate capacitance and improve the gate breakdown voltage.

[0010]

Since the ohmic layer on the source side is connected from the side surface of the channel layer, the current path from the end of the gate electrode to the ohmic electrode can be shortened and the parasitic resistance can be reduced to improve gm.

By providing the ohmic layer on the drain side on the channel layer, lateral diffusion of impurities from the ohmic layer to the channel layer can be suppressed, and the gate capacitance can be reduced and the gate breakdown voltage can be improved.

Since the source-side and drain-side ohmic layers are grown in the same manufacturing process, it is not necessary to divide the source-side and drain-side ohmic layers into different manufacturing processes, and an increase in the number of manufacturing processes can be suppressed.

When the parallel ohmic structure is used, the central ohmic layer is provided on the channel layer.
The device area can be made smaller than in the case where all the ohmic layers are adjacent to the channel layer.

[0014]

EXAMPLE 1 An example of a Schottky junction gate FET according to the present invention is shown in FIG. 1 for a GaAs MESFET. FIG. 1A is a cross-sectional view in the case of a normal single gate structure, and FIG. 1B is a cross-sectional view in the case of a parallel gate structure in which a drain electrode is arranged in the center and source electrodes are arranged at both ends. .. FIG. 1 (c) shows a plan view of a parallel gate structure. If the gate width of the FET is Wg and the sheet resistance of the gate metal is ρ, the gate resistance in the case of the single gate structure is (ρ · Wg), but in the parallel gate structure it is ¼ × (ρ · Wg), Since the gate resistance can be reduced, good high frequency characteristics can be obtained. Therefore, a parallel gate structure or a split gate structure is often used in applications such as analog circuits. When the present invention is used in a parallel gate structure, the device structure can be made bilaterally symmetrical with the drain electrode at the center of the device and the source electrodes at both ends.
Further, since the central drain side ohmic layer 3 can be formed without etching the channel layer 2, the area can be reduced.
Therefore, the element area of the FET can be reduced as compared with the case where the entire ohmic layer is formed in the etching region.

FIG. 2 shows the manufacturing process in the case of FIG.

(A) Semi-insulating GaAs substrate 1 with SiO ₂ film 10
Is deposited and ion implantation is performed to form the operating layer 2. When the ion implantation is performed by penetrating the SiO ₂ film 10, the projected range of the ions can be reduced and the operating layer 2 can be thinned. After removing the SiO ₂ film 10 in the portion of the operating layer 2, 300 nm of WSi _X is deposited as a gate metal and processed to form a gate electrode 5. After that, the SiO ₂ film 10 'is coated to 200 nm by plasma CVD (chemical vapor deposition).

(B) The SiO ₂ film 10 'is ground by 170 nm by vertical dry etching to form SiO ₂ sidewalls beside the gate electrode.

(C) A resist film 12 is applied to a region other than the ohmic layer forming region on the source side, and the GaAs substrate 1 is ground by microwave plasma etching using the resist film 12 as a mask, whereby the operating layer 1 on the source side is formed. Expose the sides of.

(D) After removing the resist film 12, 1/1
After removing the SiO ₂ film 10 'with a hydrofluoric acid solution diluted to 00 to expose the ohmic layer formation region on the drain side,
N + -GaAs layer (3 × 1) by CVD (metal organic chemical vapor deposition) method
0 ¹⁸ / cm ³ ) is selectively grown to a thickness of 300 nm to form the ohmic layer 3.

(E) After the interlayer insulating film 11 is covered, the interlayer insulating film 11 is removed in the ohmic electrode forming region, the ohmic electrodes (AuGe / Ni) 6, 7 are formed by the lift-off method, and wiring is performed. This completes the present invention.

In order to reduce the parasitic resistance, it is possible to perform ion implantation using the gate electrode 5 as a mask and to provide another conductive layer having a carrier concentration higher than that of the operating layer 2 between the operating layer 2 and the ohmic layer 3. The conductive layer formed by this ion implantation may be formed by using the SiO ₂ side wall as a mask. The conductive layer formed by this ion implantation can be provided only on one of the source side and the drain side.

In this embodiment, the structure in which the ohmic layer on the drain side is formed on the operating layer is used. However, the structure in which the ohmic layer on the source side is formed on the operating layer is used to diffuse impurities in the substrate direction. It is also possible to suppress the short channel effect.

In this embodiment, the gate electrode 5 is made of WSi _X , but other metal materials such as Ti / Pt / Au can be used. Although the ohmic layer 3 with n + -GaAs _{layer, n + -In X Ga 1-} X As layer and n +-INAS layer or n + -Ge layer and n + -In _X Ga _1- It is also possible to form a non-alloy ohmic layer by using an _X As graded composition layer.

It is also possible to form the ohmic layer 3 using a plurality of semiconductor layers or modulation dope layers having different impurity concentrations, or a plurality of semiconductor layers having different materials or compositions.

Although this embodiment shows the case of a GaAs MESFET, other compound semiconductor materials such as InGaAs can be used, and Si and Ge can also be used.

(Embodiment 2) The present invention is a heterojunction MES.
FIG. 4 shows an embodiment when applied to a FET. n-Ga
The Schottky barrier can be increased by providing a buffer layer made of another semiconductor material having a bandgap larger than that of the operating layer between the As operating layer 2 and the gate electrode 5 to form a heterojunction. If the Schottky barrier is high, the logic amplitude of the device can be increased, the leakage current from the gate electrode can be reduced, and the power consumption can be reduced, so that the device performance is improved.

In FIG. 4, the n-GaAs operating layer (3 × 10 ¹⁸ / cm 3
³ , 15 nm) 2 on top of the un-Al _X Ga _1-X As buffer layer (10n
m) 4 is provided, but the gate electrode 5 has W
The height of the Schottky barrier when Si _X is used can be improved by about 0.3 V by using the buffer layer.

In this embodiment, the ohmic layer on the drain side is grown on the operating layer 2, but it may be grown on the hetero buffer layer 4 to suppress the diffusion of impurities from the ohmic layer. ..

Further, in FIG. 4, the operating layer 2 is made of undoped In.
MODFE having a strained superlattice structure by using a GaAs layer and using an n-type InAlAs layer as the electron supply layer in the buffer layer 4.
It can also be T (Modulation Doped FET).

In this embodiment, the GaAs / Al _x Ga _{1 -x} As system heterojunction FET has been described, but it is possible to use a combination of other compound semiconductor materials for the heterojunction, and Si / The structure of the present invention can be applied to a heterojunction FET such as SiGe or SiC / Si, or amorphous Si / crystal Si.

FIG. 5 shows E / D (Enhancement type / Depletion
An example of forming an inverter circuit having a (type) configuration will be described. For driving, the FET of the present invention shown in FIG. 4 is used,
For loading, an FET having a structure in which a buffer layer 4'of undoped GaAs is provided between the gate electrode 5 and the heterojunction buffer layer 4 and the threshold voltage is shifted to the negative side is used. FET for load
Since the ohmic layer on the source side and the ohmic layer on the drain side of the driving FET are also used, the ohmic layer of the load FET is provided on the operating layer 2 on both the source side and the drain side. It is also possible to reduce the parasitic resistance by using a method in which the ohmic layer is adjacent to the operation layer 2.

(Embodiment 3) Since the ohmic layer of the field effect transistor has a high impurity concentration, the impurity diffuses into the substrate to increase the leakage current toward the back surface, thereby increasing the two-dimensional effect (short channel effect, etc.). ) Aggravates the problem. In order to solve this problem, H, B,
There is known a method of implanting an ion species such as O to generate an electron trap level to partially increase the resistance of the substrate. However, in a device in which the ohmic layer is formed by the ion implantation method, it is However, there is a problem that the isolation ion species remain and prevent lowering of resistance of the ohmic layer. However, in the method of forming the ohmic layer by the selective growth method, since the ohmic layer is grown on the high resistance layer, there is no problem that the isolation ion species is contained in the ohmic layer.

FIG. 6 shows an embodiment in which a high resistance layer is formed under the ohmic layer. In this example, a case where the resistance under the source side ohmic layer formation region is made high by ion implantation is shown, but it is possible to provide a high resistance layer also under the drain side ohmic layer in order to improve the isolation property. is there.

(Embodiment 4) The device structure of the present invention is MI
SFET (Metal Insulator Semiconductor FET), JFET (Junction FET), HEMT (High Electr)
on Mobility Transistor), and an example thereof is shown in FIG. 7 in which an inverter circuit is constructed by using a GaAs JFET for driving.

A p + -GaAs layer 9 is formed on the n-GaAs operating layer 2.
As a gate, the ohmic layer 6 on the source side is connected from the side surface of the operating layer 2, and the ohmic layer 7 on the drain side is formed.
Are connected from the upper surface of the operating layer 2. Since the load FET needs to have a threshold voltage more negative than that for driving, an insulating film (Si ₃ N ₄ ) 14 is provided on the operating layer 2 to form a MISFET structure. Since the load FET can have a large design margin of variation in threshold voltage, the influence of the interface state between the operating layer 2 and the insulating film 14 does not pose a serious problem.

The device structure of the present invention was used for the driving FET, but the source electrode was used for the driving FET as the driving FET.
In order to serve also as the drain electrode of, the method of forming the selective growth method from above the channel layer 2 on both the source side and the drain side was used.

[0037]

According to the present invention, it is possible to obtain a Schottky junction gate field effect transistor having high performance and high reliability.

[Brief description of drawings]

1A and 1B show an embodiment of a field effect transistor of the present invention, where FIG. 1A is a sectional view in the case of a single gate structure, and FIG. 1B is a sectional view in the case of a parallel gate structure. (c) is a plan view of (b).

FIG. 2 is an explanatory view of the manufacturing process of FIG.

FIG. 3 is a cross-sectional view of a conventional device structure, where (a) is a case where an ohmic layer is provided on an active layer, and (b) is a case where an ohmic layer is provided adjacent to the active layer.

FIG. 4 shows a heterojunction FE as another embodiment of the present invention.
Explanatory drawing shown about the case of T.

FIG. 5 is a cross-sectional view of an example in which an E / D inverter circuit is configured.

FIG. 6 is a cross-sectional view of an embodiment in which the source side ohmic layer is insulated by implanting an isolation ion species.

FIG. 7 is a cross-sectional view of an example in which an inverter circuit of JFET is configured.

[Explanation of symbols]

1 ... Semiconductor substrate or buffer layer, 2 ... Operating layer (n-GaAs)
, 3 ... ohmic layer (n + -GaAs), 4 ... heterojunction buffer layer (un-Al _X Ga _{1 over X} As), 4 '... buffer layer (un-GaAs),
5 ... Gate electrode (WSi _X ), 6 ... Source electrode (AuGe), 7
... Drain electrode (AuGe), 8 ... Low resistance metal (Au or Al), 9 ... Semiconductor conductive layer (p + -GaAs), 10, 10 '...
Insulating film (SiO ₂ ), 11 ... Interlayer insulating film (SiO ₂ / PSG),
12 ... Organic coating film, 13 ... High resistance layer, 14 ... Insulating film (Si
₃ N ₄ ).

Front page continuation (72) Inventor Hidetoshi Matsumoto 1-280 Higashi-Kengokubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory

Claims (7)

[Claims] 1. A Schottky junction gate field effect transistor having a low resistance layer formed by a selective growth method between an operation layer and an ohmic electrode, wherein one of the low resistance layers at both ends of the operation layer is the operation layer. A field effect transistor characterized in that a connection is provided from a side surface and the other is provided from an upper surface of the operation layer. 2. The method according to claim 1, wherein a buffer layer made of another semiconductor material having a band gap larger than that of the semiconductor material forming the operating layer or an electron supply layer is provided between the operating layer and the gate electrode. Field effect transistor. 3. The field effect transistor according to claim 1, wherein a semiconductor layer of a conductivity type opposite to the operating layer or an insulating layer is provided between the operating layer and the gate electrode. 4. The same conductive property as the low resistance layer according to claim 1, 2 or 3, between one or both of the low resistance layers provided at both ends of the operation layer of the field effect transistor and the operation layer. A field effect transistor when another conductive layer having a mold is provided. 5. The composition according to claim 1, 2, 3, or 4, when a semiconductor material different from that of the operation layer is used for the low resistance layer, a composite layer made of a plurality of semiconductor materials is used, or a graded composition. Field effect transistor when using layers. 6. The method according to claim 1, 2, 3, 4, or 5.
A field effect transistor in which the low resistance layer is composed of a plurality of layers made of the same material and having different carrier concentrations, or composed of a modulation doped layer. 7. A field effect transistor according to claim 1, 2, 3, 4, 5, or 6, wherein a high resistance layer formed by ion implantation is provided below the low resistance layer.