JPH05144258A - Special mode control method for dynamic ram - Google Patents

Abstract

(57) [Summary] [Object] To provide a special mode control method of a dynamic RAM including a low power consumption mode capable of efficient, stable, and reliable operation. [Structure] A special mode is set by a combination of an address strobe signal and another control signal, and a dummy CBR refresh is performed to release the special mode. [Effect] By combining the timings of the external clocks including the address strobe signal, it is possible to set an efficient and reliable stable special mode including a low power consumption mode, and by performing a dummy CBR refresh to cancel the mode. The internal circuit can be returned to the normal state without destroying the stored data.

Description

Detailed Description of the Invention

[0001]

This invention relates to a dynamic RA
The present invention relates to a method for controlling a special mode of M (random access memory), for example, a technology effective when used for a device provided with a low power consumption mode only for the purpose of holding information.

[0002]

2. Description of the Related Art Operation modes of a dynamic RAM are a normal write / read mode, a test mode and a refresh mode. Dynamic type R
To reduce the power consumption of a memory system using AM,
Low power consumption modes such as battery backup have been proposed. Regarding such a battery backup mode, for example, the Institute of Electronics and Communication Engineers Technical Report ED
There is -90-78. This battery backup mode is set by fixing the CASB signal at the low level and the RASB signal at the high level for 16 ms or more after entering the auto-refresh in the CBR (CASB before RASB) mode.

[0003]

According to the mode setting method as described above, the CASB mode is set for 16 ms or more after the auto refresh state is once set in the CBR mode.
The signal has to be fixed to the low level and the RASB signal has to be fixed to the high level, which complicates the mode setting, and the stored information in the memory cell may be lost due to the accuracy of the timer measuring 16 ms. There is Further, although the mode is released by resetting the CASB signal, in order to reduce the power consumption of the dynamic RAM, the internal circuit is different from the normal operating state, so immediately after the mode is released. If the write / read operation is performed, the internal circuit may become unstable and malfunction may occur. The purpose of this invention is
It is an object of the present invention to provide a special mode control method for a dynamic RAM including a low power consumption mode that enables efficient, stable, and reliable operation. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the special mode is set by the combination of the address strobe signal and other control signals, and the dummy CBR refresh is performed as the mode release.

[0005]

According to the above-mentioned means, the special mode including the low power consumption mode can be set efficiently and surely by combining the timings of the external clocks including the address strobe signal, and the dummy C can be used to release the mode.
By executing the BR refresh, the internal circuit can be returned to the normal state without destroying the stored data.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a dynamic type R according to the present invention.
A functional block diagram of an embodiment in an AM (hereinafter sometimes simply referred to as a DRAM) is shown. The DRAM of this embodiment has an access mode including a read operation (READ) and a write operation (WRITE).
In this access mode, a row address signal is input in synchronization with the row address strobe signal RASB, similarly to the well-known dynamic RAM access method.
Subsequently, a column address signal is input in synchronization with the column address strobe signal CASB to select the address of the memory cell. Then, the write enable signal WEB is set to the low level for the write operation, and the write enable signal WEB is set to the high level for the read operation. There is also an early write cycle that is executed by setting the write enable signal WEB to low level prior to CASB. Here, in the present specification, R
It should be noted that signals such as ASB, CASB, and WEB which have B added to the end of the letters of the alphabet mean that the low level is the active level.

The test mode is mainly used for operation check at the time of manufacturing or shipping of DRAM. In this test mode, the write enable signal WEB and the column address strobe signal CASB are set to the low level before the row address strobe signal RASB.
It is performed in the R mode.

As is well known, a DRAM uses a memory cell composed of a MOSFET for address selection and a capacitor for information storage, and holds information corresponding to logic 1 and 0 depending on whether the information storage capacitor has information charge or not. It is a thing. The information charge held in the information storage capacitor is lost with the passage of time due to drain leakage current in the address selection MOSFET. Therefore, the DRAM has a refresh mode in which it is read before the stored charge of the memory cell is lost and is amplified and written in the original memory cell. This refresh mode includes row address strobe signal RA
Column address strobe signal CASB prior to SB
Is set to a low level, RAS only refresh is performed by setting the row address strobe signal RASB to a low level, and the signal RASB is reset from the read state and the read data is output. There is hidden refresh in which refresh is executed by RASB. Among the above refresh modes, RAS
The only refresh function may not be required as described below.

The DRAM of this embodiment is provided with a data holding mode as one of the special modes other than the above modes. This data holding mode is a low power consumption mode for reducing the operating current as much as possible in consideration of only the data holding operation of the memory cell as described later. Therefore, among the internal circuits, the circuits that are considered to be unnecessary for the data holding operation of the memory cell are in the inactive state even when placed in the middle of the refresh operation for the data holding operation, in other words, the operating current. Are placed in a state where they do not flow.

FIG. 2 shows an operation timing chart of an embodiment for setting the data holding mode.
In this embodiment, RAS is used in DRAM refresh.
Only refresh function is removed. That is, R
The AS-only refresh operation is an operation for operating a row internal circuit to perform a refresh operation of a memory cell. For that purpose, an address signal corresponding to a word line to be refreshed from the outside is required. An address generation circuit for generating a refresh address is needed. On the other hand, in the CBR refresh operation, the address is internally generated, so that the external circuit can be greatly simplified. Therefore, it is no exaggeration to say that there is no need for RAS-only refreshing from the present to the future.

Therefore, in this embodiment, as described above, R
With the AS-only refresh function removed and the CASB signal fixed at a high level as shown in FIG.
The data holding mode is entered at the timing of resetting the signal to low level and then to high level. In this data holding mode, the CASB signal is set to the active level of the low level and then the RASB signal is set to the low level to reset the mode. In other words, the data holding mode is released. That is, in this embodiment, the dummy refresh is performed simultaneously with the release of the holding mode by the CBR refresh. By inserting such a dummy CBR refresh, an internal circuit, which will be described later, required for the circuit to enter the normal mode from the data holding mode is initialized.

In this embodiment, the RASB signal and the CASB signal are
An extremely simple, stable, and reliable setting and cancellation of the data holding mode, which is a combination with a signal, can be realized, and the internal circuit therefor can be simplified.

FIG. 3 shows an operation timing chart of another embodiment for setting the data holding mode. In this embodiment, the test mode is temporarily entered. That is, as the first mode, the WEB signal and the CASB signal are set to the active level of the low level prior to the RASB signal to enter the WCBR mode.
The B signal is reset to a high level to give an instruction to stop the test, and the CASB signal is set to a low level to enter the data holding mode. And, although not particularly limited, the mode reset is performed by the RASB signal and the CA.
This is performed by resetting the SB signal to the high level. In this structure, a dummy cycle is required for initializing the internal circuit which is inactivated in the data holding mode. Therefore, as the mode reset, the above-mentioned C
BR refresh may be inserted as a dummy cycle. In this configuration, the DRAM apparently enters the test mode, which is rarely used in the system mounted state, and the data holding mode is entered by the subsequent level control of the CASB signal.
A simple, stable, and reliable setting and cancellation of the data holding mode can be realized by combining the EB signals, and the internal circuit therefor can be simplified. Also, in this embodiment, RA
The S-only refresh function can also be left, and full compatibility with the conventional DRAM can be maintained.

FIG. 4 shows an operation timing chart of another embodiment for setting the data holding mode. In this embodiment, the WEB signal and the CASB signal are set to low-level active levels prior to the RASB signal, the address signal ADD is fetched at the falling timing of the RASB signal, and the data signal holding mode is set by the address signal Z. enter. In this configuration, it is possible to set other special modes in addition to the data holding mode by combining the address signals.

Since the circuit can be miniaturized by the progress of semiconductor technology, a simple logical operation circuit is provided inside the DRAM, and for example, a logical operation is performed on internal data and external data and the operation result is written. Such a write mode that involves data processing, a write mode that externally rewrites only a specific bit of data that consists of multiple bits, or a bit that specifies a specific bit of data that consists of multiple bits. If they are the same, a special mode such as a search read mode for reading the data can also be provided.
When a plurality of special modes are provided in this manner, one mode can be efficiently, stably and surely selected from a plurality of prepared special modes by combining the address signals ADD.

FIG. 5 shows an operation timing chart of another embodiment for setting the data holding mode. In this embodiment, in addition to the WEB signal and the CASB signal prior to the RASB signal, when the output enable signal OEB exists, it is also set to the active level of the low level, and the RAS signal is raised to the low level. These signals CASB,
The low level of WEB and OEB is judged and the data holding mode is entered. With this configuration, it is possible to realize a simple, stable, and reliable setting and cancellation of the data holding mode, which is a combination of the RAS signal and the CASB signal with the WEB signal and the OEB signal, and the internal circuit therefor can be simplified.

FIG. 6 shows an operation timing chart of another embodiment for setting the data holding mode. In this embodiment, the internal timer circuit is activated immediately after the normal mode is ended by the RASB signal and the CASB signal. This timer circuit measures a predetermined time Tm. Although not shown in the figure, when the normal mode, the refresh mode, or the test mode as described above is executed within the time Tm, it is reset each time and the measurement operation is started when the standby state is entered.

The time Tm does not take the information holding time of the memory cell into consideration unlike the above 16 ms, but the information holding time of the memory cell is the information holding time of the memory cell and the set time in the timer circuit. It is set to a sufficiently short time in consideration of the worst case due to variations, temperature, and power supply fluctuations. If the memory cell is not accessed within the set time Tm, the internal circuit automatically enters the data retention mode. Then, a dummy CBR refresh is executed to reset the data holding mode.

With this structure, in a relatively small-scale memory system, attention is paid to frequent memory access in conjunction with data processing operations in a data processing device such as a microcomputer, and for a certain period of time or more. When the memory access is not performed for a long time, the data processing device is considered to be in the operation stop state and automatically enters the data holding mode as described above. Therefore, low power consumption can be achieved without requiring special operation control from the outside. Then, the memory access can be executed only by inserting a dummy CBR refresh for one cycle when the data processing device starts the operation.

FIG. 7 shows an operation timing chart of another embodiment for setting the data holding mode. As in the above embodiment, when the normal mode is terminated by the RASB signal and the CASB signal, the internal timer circuit is actuated to automatically enter the data holding mode when the time expires. May be limited to the memory system of Therefore, in this embodiment, the valid / invalid of the timer output can be controlled by using the WEB signal. For example, when the signal WEB is set to the low level within the time Tm, the time-over is validated and the data holding mode is automatically entered. If the signal WEB remains high level, the time-over signal is invalidated and the normal standby state is maintained without entering the data retention mode. With this configuration, it is possible to more finely control the data holding mode according to the memory system by combining the signal WEB.

In this embodiment, by utilizing the low level of the signal WEB and resetting it to the high level, the data holding mode is released. After this mode reset, the internal circuits automatically enter the normal standby state, and immediately thereafter, the normal operation mode can be entered. It is necessary to set the time Tn in order to shift from this data holding mode to the standby state. That is, after the signal WEB is reset to the high level to release the data holding mode, it is allowed to enter the normal mode after a lapse of time Tn. Instead of this configuration, the dummy CBR refresh as described above may be inserted to initialize the internal circuit and then enter the normal mode.

FIG. 8 shows an operation timing chart of another embodiment for setting the data holding mode. In this embodiment, the test mode is artificially set in the WCBR cycle as described above, and the WEB signal is maintained at the low level at the timing of resetting the RASB signal to enter the data holding mode. In this case, the CASB signal may be high level or low level. If the WEB signal is high level, the test mode is entered. Although not shown, the data holding mode is released by the dummy CBR refresh similar to the above, or the CASB signal is kept at the low level and the mode is reset at the timing when it is reset to the high level. It may be allowed to enter the normal mode after a lapse of a certain time Tn.

FIG. 9 shows an operation timing chart of another embodiment for setting the data holding mode. In this embodiment, the WCBR cycle similar to the above is executed and the CA is reset at the timing of resetting the RASB signal.
The data holding mode is entered by keeping the SB signal at a low level. In this case, WE
The B signal may be high level or low level. If the CASB signal is high level, the test mode is entered. Although not shown, the release of the data retention mode is performed by the dummy CBR refresh similar to the above, or the WEB signal is maintained at the low level, and the mode is reset at the timing when it is reset to the high level. It may be allowed to enter the normal mode after a lapse of a certain time Tn.

FIG. 10 shows an operation timing chart of another embodiment for setting the data holding mode. In this embodiment, a WCBR cycle similar to the above is executed, and C is executed at the timing of resetting the RASB signal.
Both the ASB signal and the WEB signal are kept at the low level so that the data holding mode is entered. Although the release of the data retention mode is not shown,
In addition to the same dummy CBR refresh as described above, the CASB signal or the WEB signal is maintained at a low level, and the mode is reset at the timing when the CASB signal or the WEB signal is reset to a high level.
It may be allowed to enter the normal mode after the elapse.

FIG. 11 shows an operation timing chart of still another embodiment for setting the data holding mode. In this embodiment, a CBR cycle similar to the above is executed, and the WEB signal is maintained at a low level at the timing of resetting the RASB signal to enter the data holding mode. Although not shown, the data holding mode is released by the dummy CBR refresh similar to the above, or the CASB signal is kept at the low level and the mode is reset at the timing when it is reset to the high level. It may be allowed to enter the normal mode after a lapse of a certain time Tn.

FIG. 25 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Each circuit block in the figure is drawn according to the geometrical arrangement in the actual semiconductor chip. In the following description, MOSFE
T is an insulated gate field effect transistor (IGFET)
Is used to mean. In this embodiment, in order to prevent the operation speed from being slowed down by lengthening various wiring lengths such as control signals and memory array drive signals due to the increase in chip size accompanying the increase in memory capacity, etc. , The following arrangements have been made in the arrangement of the memory array portion that constitutes the RAM and the peripheral portion that performs address selection and the like.

In the figure, a cross area formed by the vertical center portion and the horizontal center portion of the chip is provided. Peripheral circuits are mainly arranged in the cross-shaped area, and a memory array is arranged in an area divided into four by the cross-shaped area. That is, a cross-shaped area is provided in the central portion in the vertical and horizontal directions of the chip, whereby a memory array is formed in four divided areas. Although not particularly limited, each of the four memory arrays has a storage capacity of about 4 Mbits, which will be described later. Accordingly, the four memory arrays as a whole have a large storage capacity of about 16 Mbits. One memory mat 1 is arranged so that the word lines extend in the horizontal direction, and the complementary data lines or bit lines arranged in parallel in pairs in the vertical direction extend. Memory mat 1
A pair is arranged on the left and right around the sense amplifier 2.
The sense amplifier 2 is of a so-called shared sense amplifier system, which is commonly used for the pair of memory mats 1 arranged on the left and right. Of the memory arrays divided into four, the Y selection circuit 5 is provided on the central side. The Y selection line extends from the Y selection circuit 5 so as to extend over a plurality of memory mats of the memory array corresponding to the Y selection circuit 5, and the column switch MOS of each memory mat is extended.
Performs switch control of the FET gate.

An X system circuit 10 including an X address buffer, an X redundant circuit, and an X address driver (logical stage) is provided on the right side of the lateral center of the chip, and R
An AS system control signal circuit 11, a WE system signal control circuit 12, and a reference voltage generation circuit 16 are provided respectively. The reference voltage generation circuit 16 is provided near the center of this area,
A constant voltage VL corresponding to a voltage of about 3.3V supplied to an internal circuit is formed by receiving an external power supply VCC of about 5V. On the left side of the lateral center of the chip, a Y-system circuit 13 including a Y address buffer, a Y redundancy circuit and a Y address driver (logical stage), and a CA
An S-system control signal circuit 14 and a test circuit 15 are provided respectively. An internal step-down circuit 17 that forms a power supply voltage VCL for peripheral circuits such as an address buffer and a decoder is provided in the center of the chip. As described above, the redundancy circuit including the address buffer and the corresponding address comparison circuit, and the CAS and R for generating the control clock.
If the AS system control signal circuits and the like are centrally arranged in one place, high integration can be achieved by, for example, distributing the clock generation circuit and other circuits with the wiring channel sandwiched therebetween, in other words, sharing the wiring channel. At the same time, signals can be transmitted to the address driver (logical stage) or the like at the shortest distance and at the same distance.

The RAS control circuit 11 is used to receive the row address strobe signal RASB and activate the X address buffer. The address signal taken into the X address buffer is supplied to the X-system redundant circuit.
Here, the comparison with the stored defective address is performed,
Whether to switch to the redundant circuit is determined. The result and the address signal are supplied to the X-system predecoder. Here, a predecode signal is formed and supplied to each X decoder 3 provided corresponding to the above memory mat via the X address driver provided corresponding to each memory array. On the other hand, the RAS internal signal is supplied to the WE control circuit and C
It is supplied to the control circuit of the AS system. For example, RA
From the determination of the input order of the SB signal, the CASB signal and the WEB signal, the special modes including the automatic refresh mode (CBR), the test mode (WCBR) and the data holding mode as described above are identified. In the test mode, the test circuit 15 is activated, and the test function is set according to the specific address signal supplied at that time.

The CAS control circuit 14 is used to receive the CASB signal and form various Y control signals. The address signal taken into the Y address buffer in synchronization with the change of the CASB signal to the low level is supplied to the Y-system redundant circuit. Here, the stored defective address is compared to determine whether or not the redundant circuit is switched. The result and the address signal are supplied to the Y-system predecoder. Here, the predecode signal is formed. This predecode signal is supplied to each Y decoder via the Y address driver provided corresponding to each of the four memory arrays, while the CAS system control circuit 14 outputs the RASB signal as described above. When the test mode is determined from the determination of the input order upon receiving the WEB signal, the adjacent test circuit 15 is activated.

A total of 16 memory mats and 8 sense amplifiers are arranged symmetrically with respect to the central axis of this area in the upper part of the vertical center of the chip. Of these, four main amplifiers consisting of four corresponding memory mats and four sense amplifiers on the left and right.
Is provided. In addition, the boosted voltage generating circuit 21 for word line selection or the like receives an internal step-down voltage at the upper part of the vertical center.
Input pad areas 9B and 9C corresponding to input signals such as address signals and control signals are provided. Left and right 4 above
An internal step-down circuit 8 that divides into sets and forms an operating voltage of sense amplifier 2 is provided for each memory block. 8 in one block in this embodiment
Memory mats 1 and 4 sense amplifiers 2 are arranged, and a total of 16 memory mats 1 and 8 sense amplifiers 2 are allocated symmetrically about the vertical axis. With this configuration, a small number of main amplifiers 7 consisting of four
, The amplified signal from each sense amplifier 2 can be transmitted to the main amplifier 7 through a short signal propagation path.

A total of 16 memory mats and 8 sense amplifiers are arranged symmetrically with respect to the central axis of this area in the lower part of the vertical center of the chip. Of these, four main amplifiers consisting of four corresponding memory mats and four sense amplifiers on the left and right.
Is provided. In addition, in the lower part of the vertical center, a substrate voltage generation circuit 18 that receives an internal step-down voltage and forms a negative bias voltage to be supplied to the substrate, and an input pad area corresponding to an input signal such as an address signal and a control signal. 9A, data output buffer circuit 19, and data input buffer circuit 2
0 is provided. In the same manner as described above, the internal step-down circuits 8 for forming the operating voltage of the sense amplifier 2 are provided corresponding to the memory blocks by being divided into left and right four groups. As a result, the amplified signal from each sense amplifier 2 can be transmitted to the main amplifier 7 through a short signal propagation path while using a small number of the main amplifiers 7 such as 4 as described above.

Although not shown in the figure, in addition to the areas 9A to 9C as described above, various bonding pads are arranged in the vertical central area. Examples of these bonding pads are pads for external power supply, and in order to increase the level margin of the input, in other words, to supply the ground potential of the circuit in order to lower the power supply impedance, there are a total of more than 10 pads. And relatively many are arranged side by side on a straight line. These ground potential pads are connected to the ground potential leads extending in the vertical direction, which are formed by using the known LOC technique. Of these ground pads, those provided especially for clearing the word line and preventing floating due to coupling of the non-selected word line of the word driver, those provided for the common source of the sense amplifier, etc. It is provided mainly for the purpose of lowering the power source impedance. As a result, the ground potential of the circuit has a lower power source impedance with respect to the operation of the internal circuit, and the ground wiring between the plurality of types of internal circuits as described above is a low-pass filter including a LOC lead frame and a bonding wire. Therefore, it is possible to minimize the generation of noise and also to minimize the propagation of circuit ground line noise between internal circuits.

In this embodiment, pads corresponding to the external power supply VCC of about 5V are provided corresponding to the internal voltage down converting circuits 8 and 17 for performing the voltage converting operation.
This also lowers the power supply impedance in the same way as above, and also the voltage between internal circuits (between VCC, VDL and VCC)
This is for suppressing the noise propagation of. Address input pads A0 to A11, RASB, CASB,
Pads for control signals such as WEB and OEB are arranged in the areas 9A to 9C. In addition to this, the following pads are provided for pad control for data input and data output, bonding master, monitor and monitor pads. For the bonding master, there are one for designating the static column mode and one for designating the nibble mode and the write mask function in the x4 bit configuration. Internal voltage VC for each pad for monitoring
There is one for monitoring L, VDL, VL, VBB, VCH and VPL. Of this internal voltage, VCL is
This is a peripheral circuit power supply voltage of about 3.3 V, and is commonly formed by the internal step-down circuit 17. VDL is a power supply voltage supplied to the memory array of about 3.3V, that is, the sense amplifier 2. In this embodiment, four VDLs are provided corresponding to the above four memory blocks. VCH is a boost power supply voltage which selects the shared switch MOSFET and the selection level of the word line boosted to about 5.3V by receiving the internal voltage VDL. VBB is a substrate back bias voltage such as -2V, VPL is a plate voltage of the memory cell, and VL is a constant voltage supplied to the internal step-down circuits 8 and 17 of about 3.3V.

FIG. 12 is a block diagram showing an embodiment related to the data holding mode in the DRAM as described above. The data holding mode determination circuit is, for example, R
When the data retention mode is determined in response to ASB and WEB, a VBB generation circuit that forms a substrate back bias voltage, a VCH generation circuit that generates a boosted voltage for word boost, and an internal voltage of about 3.3V are generated. The operation of the step-down circuit, the Vref generation circuit that supplies the reference voltage to the step-down circuit, the mat selection signal generation circuit, the tref extension control circuit that extends the refresh cycle, and the column system circuit is switched to the operation for the data holding mode.

FIG. 13 is a block diagram for explaining a control example of an embodiment of the mat selection signal generating circuit. In the same figure, in order to facilitate understanding of the invention, the MAT
An example of 4 mats consisting of 0 to MAT3 is shown. In the figure, a sense amplifier is provided in the shaded portion provided in the center of the mat. 14A and 14B are logic diagrams of an embodiment of the mat selection signal generation circuit. During normal operation, only one mat designated by 2 bits of address signals Ai and Aj is activated among the four mats. That is, in FIG.
As shown in (A) and (B) of FIG.
Depending on the combination of i and Aj, one mat select signal MSi or MSj is generated by the NAND gate circuit G2 or G4.
Is generated. As a result, the consumption current can be concentrated on one mat, so that the power consumption can be reduced and the sense amplifier can operate at high speed. Such a mat selection operation is the same in the refresh operation.

When the data retention mode is determined by the combination of the RASB signal and the WEB signal, the determination circuit generates the control signal DRM instructing the data retention mode. This control signal DRM invalidates the address signal Ai in the embodiment of FIG. That is, the address signal Ai and the control signal DRM are the OR gate circuit G1.
Is input to the NAND gate circuit G2 via. Therefore,
When the control signal DRM becomes logic 1, the address signal Ai is invalidated and two memory mats designated by the address signal Aj are simultaneously selected. FIG. 14 (B)
In this embodiment, when the control signal DRM becomes logic 0, the control input of the NOR gate circuit G3 becomes logic 1 by the inverter circuit, and the address signal Ai is invalidated. As a result, another address signal Aj is output through the NAND gate circuit G4, and the two memory mats designated thereby are simultaneously brought into the selected state.

By increasing the number of memory mats refreshed in the data holding mode as compared with the normal read / write and refresh operations as in this embodiment, the number of operations of peripheral circuits for the refresh operation is reduced. It is intended to reduce power consumption. In the data retention mode, it is not necessary to speed up the operation. Therefore, as the number of memory mats increases as described above, the operating current in the sense amplifier is reduced to limit the increase in current consumption in the sense amplifier part. .. From this, when viewed comprehensively,
It is possible to significantly reduce the current consumption in the refresh operation in the data retention mode.

FIG. 15 is a block diagram showing an embodiment of the tref extension control circuit for extending the refresh cycle. When the data holding mode is determined by the combination of the RASB signal and the WEB signal, the determination circuit similarly generates the control signal DRM instructing the data holding mode. With this control signal DRM, the oscillation circuit OS
C is activated. The oscillating signal of this oscillating circuit is frequency-divided by the frequency dividing circuit and output as a pulse R0 which determines the refresh cycle through the OR gate circuit G5. That is, this signal R0 is input to the refresh address counter, and the refresh address is updated in synchronization with this signal R0. The RASB signal is input to the other input of the OR gate circuit G5. This makes the normal C
In BR refresh mode, RA input from outside
The refresh cycle is determined in synchronization with the SB signal. The extension of the refresh cycle reduces the current consumption due to the refresh operation in the data retention mode.

FIG. 16 is a block diagram showing an embodiment of the remaining other circuit whose operation is restricted in the data holding mode. In this embodiment, an internal booster circuit for an output buffer for outputting a read signal formed by a reduced internal voltage at a high voltage corresponding to a power supply voltage,
An internal booster circuit for a memory array that raises the selection voltage of the word line, a substrate bias circuit, and a half precharge voltage generation circuit are shown.

The internal booster circuit for the output buffer is composed of the following circuits. The oscillation circuit OSC1 is an active oscillation circuit whose oscillation operation is controlled by receiving the output signal of the input buffer CCB that receives the CASB signal, the address change detection pulse included in the address buffer AB and the output signal of the voltage detection circuit VS1. The booster circuit BOOT1 uses this oscillation output and the bootstrap capacitance CB1 to generate a boosted voltage and transmits it to the output buffer OB. The voltage detection circuit VS1 detects the boosted voltage and, when the boosted voltage reaches a desired voltage, stops the operation of the oscillation circuit OSC1 to suppress unnecessary current consumption. The oscillator circuit OSC2 operates steadily to form an oscillation pulse. This oscillation pulse is
The voltage is supplied to the booster circuit BOOT2 via the switch circuit DRS. The booster circuit BOOT2 receives the above-mentioned oscillation pulse and constantly forms a boosted voltage. Booster circuit BOOT2
Has a small current supply capacity to supplement the current consumed when the output buffer OB is in the inactive state.
On the other hand, the booster circuit BOOT1 is made to have a large current supply capability to supplement the large current consumed when the output buffer OB is activated. By combining such two boosting circuits BOOT1 and BOOT2, the current consumption of the internal boosting circuit for the output buffer can be suppressed small.

In this embodiment, in the data holding mode,
Paying attention to the fact that the output buffer OB is not activated, the operation of the oscillation circuit OSC1 and the voltage detection circuit VS1 is stopped by the control signal formed by the data holding mode determination circuit DRM. In this way, the oscillator circuit O
Stopping the operation of SC1 and the voltage detection circuit VS1 is
This is to prevent these circuits from being activated during the refresh operation in the data retention mode. On the other hand, the oscillating pulse generated by the oscillating circuit OSC2 is cut off from the direct supply to the booster circuit BOOT2 by the switch circuit DRS, and instead is input to the counter circuit COUNT, where the frequency dividing operation is performed. The booster circuit BOOT2 operates by the pulse whose cycle is lengthened by such frequency division to maintain the boosted output voltage. As a result, the power consumption of the booster circuit can be reduced. If the internal circuit is deactivated in this way, the first memory cycle becomes unstable when switching to the normal mode. Therefore, the dummy CB as described above
By performing the R refresh, the booster circuit BOOT1 having the large current supply capability is activated, and the boosted voltage required for stable operation of the output buffer OB can be obtained.

The internal booster circuit for the array is composed of the following circuits. The oscillator circuit OSC3 outputs the output signal of the input buffer RCB for receiving the RASB signal and the voltage detection circuit VS.
2 is an active oscillation circuit in which the oscillation operation is controlled by receiving the output signal of 2. The booster circuit BOOT4 uses the oscillation output and the bootstrap capacitance CB2 to generate a boosted voltage and transmits it to the memory array MARY as a word line selection voltage. The voltage detection circuit VS2 detects the boosted voltage and, when the boosted voltage reaches a desired voltage, stops the operation of the oscillation circuit OSC3 to suppress unnecessary current consumption. Boost circuit B
The OOT 3 receives the periodic pulse formed by the oscillation circuit OSC2 through the switch circuit DRS and constantly forms a boosted voltage. The booster circuit BOOT3 does not have a small current supply capability that compensates for a steady level drop in the word line of the memory array MARY. On the other hand, the booster circuit BOOT4 is made to have a large current supply capability to supplement the large current consumed when the word line rises to the selected state. By combining such two boosting circuits BOOT3 and BOOT4, the current consumption of the array internal boosting circuit can be suppressed to a small value.

In this embodiment, the current consumption in the booster circuit in the data holding mode is suppressed as follows. That is, the data retention mode determination circuit DR
The oscillator circuit OSC is controlled by the control signal generated by M.
3 and the operation of the voltage detection circuit VS2 are stopped. The operation of the oscillation circuit OSC3 and the voltage detection circuit VS2 is also stopped in this manner in order to prevent these circuits from being activated during the refresh operation in the data holding mode. On the other hand, the oscillating pulse generated by the oscillating circuit OSC2 is similar to the above-mentioned switch circuit DR
The direct supply to the booster circuit BOOT3 is cut off by S, and instead, it is input to the counter circuit COUNT, where the frequency dividing operation is performed. The boosting circuit BOOT3 operates by the pulse whose cycle is lengthened by such frequency division to maintain the boosted output voltage. As a result, the power consumption of the booster circuit can be reduced. If the internal circuit is deactivated in this way, the operation becomes unstable, such that a sufficient selection level cannot be obtained in the first memory cycle when switching to the normal mode. Therefore, by performing the dummy CBR refresh as described above, the booster circuit B having the large current supply capability is provided.
OOT4 is activated, and the boosted voltage required for the word line selection operation of the memory array can be obtained.

The substrate bias circuit is composed of the following circuits. The oscillation circuit OSC4 is an active oscillation circuit whose oscillation operation is controlled by receiving the output signal of the input buffer RCB that receives the RASB signal and the output signal of the voltage detection circuit VS3. The charge pump circuit ASBP receives this oscillation output, forms a negative substrate back bias voltage, and transmits it to the substrate SUB. The voltage detection circuit VS3 detects the Baice voltage and, when the bias voltage reaches a desired voltage, stops the operation of the oscillation circuit OSC4 to suppress unnecessary current consumption. The charge pump circuit SSBP receives the pulse formed by the oscillation circuit OSC2 through the switch circuit DRS and constantly forms a bias voltage. This charge pump circuit SSBP does not have a small current supply capacity to compensate for a leak current that constantly occurs in the substrate. On the other hand, the charge pump circuit A
The SBP is made to have a large current supply capability to supplement the large current consumed when the internal circuit operates. By combining such two charge pump circuits ASBP and SSBP, the current consumption in the substrate bias circuit can be suppressed small.

In this embodiment, the current consumption of the substrate bias circuit in the data holding mode is reduced as follows. That is, in the data retention mode, it is sufficient that the information storage operation of the memory cell is simply ensured, and the fluctuation of the back bias voltage on the substrate does not pose a problem.
Therefore, the operation of the oscillation circuit OSC4 and the voltage detection circuit VS3 is stopped by the control signal generated by the data holding mode determination circuit DRM. On the other hand, the oscillating pulse generated by the oscillating circuit OSC2 is cut off from the direct supply to the charge pump circuit SSBP by the switch circuit DRS in the same manner as described above, and is instead input to the counter circuit COUNT, where the frequency dividing operation is performed. Is done. The charge pump circuit SSBP operates by the pulse whose period has been lengthened by such frequency division to perform the substrate bias voltage. As a result, the power consumption of the substrate bias circuit can be reduced. If the internal circuit is substantially deactivated in this way, the first memory cycle becomes unstable when switching to the normal mode. Therefore, by performing the dummy CBR refresh as described above, the charge pump circuit ASBP having the large current supply capability is activated and the necessary substrate bias voltage can be immediately obtained.

Harp precharge voltage generation circuit HVCG
Is provided to compensate for the decrease in the half precharge level of the data line pair placed in the non-selected state due to the leak current. In the voltage generation circuit HVCG, in the data holding mode, the amplification MOSFET that receives the reference voltage for low power consumption is intermittently operated by the periodic pulse formed by the oscillation circuit OSC2. That is, also in the voltage generating circuit HVCG, in the data holding mode, the refresh operation is executed at a longer cycle than the normal operation, and in the refresh operation, the sense amplifier undergoes the current limiting operation and relatively slowly performs the amplifying operation. Corresponding to that, the operation of the amplification MOSFET is also intermittently performed.

FIG. 17 shows a circuit diagram of an embodiment of the limiter control circuit included in the data holding mode determination circuit. In the following description, each gate circuit and MOSF
Although some circuit symbols such as ET assigned to each element are partially duplicated, it should be understood that each has a different circuit function for each drawing. Signals REL and HLE
Is generated by the delay circuit DLY and the NAND gate circuit G2 when the write pulse WYPB, the address signal change detection signal ATDB or the RASB signal changes in the normal mode, corresponding to one shot pulse corresponding to the delay time of the delay circuit. As a result, as a limiter output buffer,
It is composed of two circuits, one that operates during operation and one that operates steadily for standby, and those that operate during operation are intermittently activated by the signals REL and HLE.

To the limiter control circuit as described above, NAND gate circuits G4 and G5 controlled by a signal DRTB obtained by inverting the control signal DRT in the data holding mode by the inverter circuit N2 are added to change the signal WYPB, ATDB or RASB signal. The signals RLE and HLE are forcibly set to the low level regardless of the one-shot pulse that is sometimes generated. Thus, in the data holding mode, the operation of the limiter output buffer is forcibly stopped even if there is a refresh operation or the like. These limiter output buffers will be described in detail later.

FIG. 18 shows a circuit diagram of an embodiment of the limiter output buffer for the memory array. The limiter output buffer is composed of an amplifier circuit which receives a reference voltage VL such as about 3.3V formed by a limiter reference voltage generation circuit described later and amplifies the reference voltage VL. That is, the N-channel type differential MOSFET Q1
And Q2, P-channel type load MOSFETs Q3 and Q4 in the current mirror form provided on the drain side, and N-channel type MOSFET Q5 forming an operating current source provided to the common source of the differential MOSFETs Q1 and Q2.
And a P-channel type output MOSFET Q6 for receiving the output signal of the differential circuit, which constitutes an amplifier circuit. The output of this amplifier circuit is the inverting input M
The voltage follower circuit is configured by feeding back to the gate of the OSFET Q2, and the internal step-down voltage VCL corresponding to the reference voltage VL is output. The resistor R and the capacitor C are a stabilizing smoothing circuit.

The amplifier circuit forms an operating current M in order to operate intermittently by the signal REL.
The signal RLE is supplied to the gate of the OSFET Q5. Further, a P-channel type switch MOSFET Q7 is provided between the gate and source (power supply voltage VCC) of the output MOSFET Q6, and the control signal RLE is supplied. As a result, when the signal RLE is set to low level, the N-channel MOSFET Q5 is turned off, so that the amplifying operation of the differential circuit, in other words, current consumption is stopped. In response to the low level of the signal RLE, the P-channel MOSFET Q7 is turned on and the output MOSFET Q6 is turned off.

FIG. 19 shows a circuit diagram of an embodiment of the limiter reference voltage generating circuit. This circuit is MO
Start-up circuit composed of SFETs Q1 to Q3 and inverter circuits N1 and N2, MOSFETs Q4 to Q7 and resistor R
Constant current generating circuit consisting of 1, R2 and MOSFET Q8
A VCC detection circuit composed of Q11 and resistors R3 and R4;
It is composed of a constant voltage generating circuit including MOSFETs Q12 to Q17. In this embodiment, in the data holding mode, the limiter reference voltage generating circuit is also stopped in response to stopping the operation of the internal step-down circuit (limiter circuit) as described above. For this reason, the P-channel MOS is connected to the power supply line supplied to these circuits.
A power switch composed of the FET Q18 is provided, and the switch is controlled by the control signal DRT. In other words, when the data holding mode is entered, the P-channel MOSFET Q18 is turned off by the high level of the signal DRT to cut off the supply of the operating voltage VCC to the limiter reference voltage generating circuit composed of the above circuits. is there.

FIG. 20 shows a circuit diagram of an embodiment of the limiter output buffer for the peripheral circuit. The limiter buffer for operation is composed of a circuit similar to that shown in FIG. However, when the operation of the limiter output buffer is stopped, an N-channel type switch MOSFET Q8 that transmits the operating voltage VCC as it is to the internal circuit is added to secure the operating voltage of the peripheral circuits. The switch MOSFET Q8 is turned on by the high level of the control signal DRT generated in the data holding mode, and replaces the limiter output buffer with the power supply voltage VCC.
Tell as it is. Actually, when the signal DRT is at a high level such as VCC, a voltage such as VCC-Vth is supplied as the operating voltage of the peripheral circuit. Where Vth
Is the threshold voltage of MOSFET Q8.

The operation of the limiter output buffer for the peripheral circuit is controlled by the signal HLE. In the data holding mode, since the signal HLE is forcibly fixed to the low level as described above, the operation limiter output buffer is prevented from operating during the data holding mode. Further, the standby limiter output buffer also includes a differential circuit and an output MOSFET similar to the above. This standby limiter output buffer is also added with a P-channel MOSFET for receiving the signal DRTB which is set to the low level in the data holding mode in order to stop the operation in the data holding mode.
The output of the differential circuit is forcibly set to a high level like the power supply voltage VCC by the ON state of the SFET. As a result, the standby limiter output buffer is also forced to stop operating.

FIG. 21 is a circuit diagram showing another embodiment of the limiter output buffer for peripheral circuits. In this embodiment, the operation limiter output buffer is provided with a P-channel type switch MOSFET Q8, which is controlled by an inverted control signal DRTB. As a result, in the data holding mode, the P-channel MOSFET Q8 is turned on according to the low level of the signal DRTB, and the power supply voltage VCC is transmitted to the peripheral circuits as it is.

FIG. 22 shows an operation timing chart of one embodiment for explaining the limiter control method. The limiter output buffer for operation of the peripheral circuit generates one pulse each at the time of setting and resetting the RAS clock in the normal operation mode, in other words, at the fall to the low level and the rise to the high level. Is activated each time in synchronization with the operation timing of. Further, in order to correspond to the high speed page mode, it is activated in synchronization with the ATD pulse corresponding to the change of the address signal and the WYP pulse for writing.

On the other hand, when the data holding mode is entered, all the limiter output buffers including the reference voltage generating circuit and the standby limiter output buffers of the peripheral circuits are stopped. Instead of stopping the limiter output buffer as described above, the external voltage VCC is an N-channel MOSFET.
Alternatively, it is directly supplied through the switch of the P-channel type MOSFET. In this case, since the power source impedance becomes extremely high as a supply source of the internal voltage, the voltage becomes unstable to some extent, but the current consumption in the step-down circuit becomes zero, which is suitable for the data retention mode. In this data retention mode, since only the refresh operation is performed with a long cycle generated inside the chip, there is a concern that the fluctuation of the internal voltage due to the increase of the power supply impedance as described above may adversely affect the access time. There is no.

FIG. 23 shows the switch circuit D of FIG.
A circuit diagram of one embodiment of RS is shown. Oscillator output (Standby OSC) and control signal (Data Retentio)
n) is input to the NAND gate circuit. The output signal of the NAND gate circuit is supplied to a counter (Counter) and a half precharge voltage generation circuit (Half VCC Generator). Output of the above oscillation circuit (Standby OSC)
And the control signal (Data Retention) are input to the NOR gate circuit. The output signal of this NOR gate circuit is switch-controlled by a control signal (Data Retention) C
Standby booster circuit (Standby
Booster).

In the data holding mode, the control signal (Data
Retention) is set to high level. As a result, CM
The OS switch circuit is turned off and the output is set to a high impedance state. Then, the NAND gate circuit opens the gate to transmit the oscillation pulse to the counter circuit and the half precharge circuit. As a result, the standby booster circuit and the charge pump circuit as described above are operated by the pulse divided by the counter circuit to enter the low power consumption mode. On the other hand, in the normal mode, the oscillation pulse is output through the NOR gate circuit according to the low level of the control signal (Data Retention), and the CM
The OS switch circuit is turned on, and the oscillation pulse is input to the standby booster circuit or the like. At this time, the output of the NAND gate circuit is fixed to the high level, the operation of the counter circuit is stopped, and the amplification circuit of the half precharge circuit is activated.

FIG. 24 shows a circuit diagram of an embodiment of the half precharge voltage generation circuit HVCG. This circuit generates a reference voltage such as VCL / 2 by a voltage dividing circuit composed of capacitors C1 and C2. This voltage is supplied to an amplifier circuit composed of a P-channel type MOSFET Q1 and an N-channel type MOSFET Q2 for power amplification. In this amplifier circuit, negative feedback is performed by connecting the input and output in common. In data retention mode, switch MOS is activated by oscillation pulse
The FETs Q3 and Q4 are provided and are operated intermittently to reduce the direct current.

In this embodiment, in the data holding mode,
In order to perform the intermittent operation of the amplifier circuit, the oscillation pulse of the oscillation circuit OSC is transmitted through the switch circuit DRS to the switch M.
It is supplied to the gates of OSFETs Q3 and Q4. The switch circuit DRS is controlled by the control signal DRT,
In the data holding mode, the oscillation pulse is supplied as described above by the high level of the signal DRT, and the high level is output in the normal mode.

The functions and effects obtained from the above-mentioned embodiment are as follows. That is, (1) By setting the special mode by combining the address strobe signal and other control signals, it is possible to set the special mode including the efficient and reliable stable low power consumption mode. Be done. (2) As a special mode provided in the DRAM, by adding a data retention mode for reducing the power consumption by stopping the operation of the internal circuit that does not adversely affect the data retention operation, a hatchery backup such as a static RAM is provided. It is possible to obtain the effect that the applications of DRAM such as non-volatile memory and battery-powered data processing device can be further expanded. (3) As a method of releasing the special mode, a dummy C
By using the BR refresh, the effect that the internal circuit can be initialized to the normal state without considering the adverse effects such as the destruction of the stored data is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, deactivating the internal circuit in the data retention mode is
Various embodiments can be adopted according to the internal configuration of the. Further, the special mode may be a plurality of types in addition to the data holding mode. As for the layout of the entire DRAM, in addition to the structure shown in FIG. 25, various embodiments can be adopted for the mat structure of the memory and the arrangement of its peripheral circuits. The present invention can be widely used for dynamic RAM.

[0064]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. In other words, by setting the special mode by combining the address strobe signal and other control signals, it is possible to set the special mode including the low power consumption mode which is efficient and reliable and stable. By using the dummy CBR refresh, the internal circuit can be initialized to the normal state without considering the adverse effects such as the destruction of the stored data.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of a dynamic RAM according to the present invention.

FIG. 2 is an operation timing chart showing an embodiment for setting a data holding mode according to the present invention.

FIG. 3 is an operation timing chart showing another embodiment for setting the data holding mode according to the present invention.

FIG. 4 is an operation timing chart showing another embodiment for setting the data holding mode according to the present invention.

FIG. 5 is an operation timing chart showing another embodiment for setting the data holding mode according to the present invention.

FIG. 6 is an operation timing chart showing another embodiment for setting the data holding mode according to the present invention.

FIG. 7 is an operation timing chart showing another embodiment for setting the data holding mode according to the present invention.

FIG. 8 is an operation timing chart showing another embodiment for setting the data holding mode according to the present invention.

FIG. 9 is an operation timing chart showing another embodiment for setting the data holding mode according to the present invention.

FIG. 10 is an operation timing chart showing another embodiment for setting the data holding mode according to the present invention.

FIG. 11 is an operation timing chart showing still another embodiment for setting the data holding mode according to the present invention.

FIG. 12 is a block diagram showing an embodiment related to a data holding mode in a DRAM to which the present invention is applied.

FIG. 13 is a block diagram for explaining a control example of an embodiment of a mat select signal generation circuit in a DRAM to which the present invention is applied.

FIG. 14 is a logic diagram showing an embodiment of a mat selection signal generation circuit.

FIG. 15 is a block diagram showing an embodiment of a tref extension control circuit for extending a refresh cycle in a DRAM to which the present invention is applied.

FIG. 16 is a block diagram showing an embodiment of the remaining other circuit of which operation is restricted in the data holding mode in the DRAM to which the present invention is applied.

FIG. 17 is a circuit diagram showing an example of a limiter control circuit included in the data holding mode determination circuit.

FIG. 18 is a circuit diagram showing an embodiment of a limiter output buffer for a memory array.

FIG. 19 is a circuit diagram showing one embodiment of a limiter reference voltage generating circuit.

FIG. 20 is a circuit diagram showing an embodiment of a limiter output buffer for peripheral circuits.

FIG. 21 is a circuit diagram showing another embodiment of the limiter output buffer for peripheral circuits.

FIG. 22 is an operation timing chart showing an embodiment for explaining the limiter control method.

23 is a circuit diagram showing an embodiment of the switch circuit DRS of FIG.

FIG. 24 is a half precharge voltage generation circuit H of FIG.
It is a circuit diagram which shows one Example of VCG.

FIG. 25 is a dynamic RAM to which the present invention is applied.
It is a block diagram which shows one Example.

[Explanation of symbols]

MAT0 to MAT3 ... Memory mat, OSC, OSC1
OSC4 ... Oscillation circuit, RCB, CCB ... Input buffer, AB ... Address buffer, BOOT1 to BOOT4
... Booster circuit, CB1, CB2 ... Bootstrap capacitance,
OB ... Output buffer, VS1 to VS3 ... Voltage detection circuit,
COUNT ... Counter circuit, DRS ... Switch circuit, H
VCG ... Half precharge voltage generation circuit, MARY ...
Memory array, ASBP, SSBP ... Charge pump circuit, SUB ... Substrate, G1 to G5 ... Gate circuit, N1 to N
5 ... Inverter circuit, DLY ... Delay circuit, Q1-Q18
... MOSFET, R, R1 to R4 ... Resistance, C, C1, C
2 ... Capacitor, 1 ... Memory mat, 2 ... Sense amplifier, 3 ... X decoder, 4 ... Mat control signal generation circuit, 5
... Y selection circuit, 6 ... Word clear circuit, 7 ... Main amplifier, 8 ... Internal step-down circuit (for sense amplifier), 9A to 9C
... input pad area, 10 ... X system circuit, 11 ... RAS
System control signal circuit, 12 ... WE system signal control circuit, 13 ... Y
System circuit, 14 ... CAS system control signal circuit, 15 ... Test circuit, 16 ... Reference voltage generation circuit, 17 ... Internal step-down circuit, 1
8 ... Substrate voltage generation circuit, 19 ... Data output buffer circuit, 20 ... Data input buffer circuit, 21 ... Boosted voltage generation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H01L 27/108 8728-4M H01L 27/10 325 V (72) Inventor Yutaka Ito Imai, Ome, Tokyo 2326 Address Hitachi, Ltd. Device Development Center (72) Inventor Kazuya Ito 2326 Imai, Ome City, Tokyo Hitachi Ltd. Device Development Center (72) Inventor Wataru Arakawa 2326 Imai, Ome City, Tokyo Hitachi Ltd. Device Development Center (72) Inventor Hidetoshi Iwai 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Toshiyuki Sakuda 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center

Claims (10)

[Claims] 1. Among address strobe signals for multiplexing and inputting a row address signal and a column address signal, only the row address strobe signal is set to a low level and used for setting a special mode other than the refresh mode. And a special mode control method for a dynamic RAM. 2. A column address strobe signal and a write control signal are used prior to the row address strobe signal by using an address strobe signal and a write control signal for multiplexing and inputting a row address signal and a column address signal. Is set to the active level, and the special mode control method of the dynamic RAM is characterized by resetting the column address strobe signal from the state of the first mode and then setting the special mode as the active level again. 3. An address strobe signal, a write control signal, and an address signal for multiplexing and inputting a row address signal and a column address signal are used,
The special mode is set by setting the column address strobe signal and the write control signal to the active level prior to the row address strobe signal and fetching the address signal at the timing when the row address strobe signal is set to the active level. A special mode control method for a dynamic RAM. 4. An address strobe signal for multiplexing and inputting a row address signal and a column address signal, a write control signal and an output control signal are used,
A special mode control method for a dynamic RAM characterized in that a special mode is set by setting a column address strobe signal, a write control signal and an output control signal to an active level prior to a row address strobe signal. 5. A column address strobe signal is activated prior to the row address strobe signal by using an address strobe signal for multiplexing and inputting a row address signal and a column address signal and another operation control signal. A special mode control method for a dynamic RAM, characterized in that the special mode is set by a combination of a first mode for setting a level and a column address strobe signal and another operation control signal at a timing of resetting a row address strobe signal. . 6. A timer circuit that starts operation from the end of the write / read mode and the refresh mode is used, and the timer circuit is reset each time the write / read mode or the refresh mode is performed. A special mode control method for a dynamic RAM, which is characterized by automatically setting a special mode by output. 7. A timer circuit that starts operation from the end of the write / read mode and the refresh mode is used, the timer circuit is reset every write / read mode or refresh mode, and the overtime by the timer circuit is increased. A special mode control method for a dynamic RAM, wherein a special mode is selectively set by a combination of an output and a control signal. 8. The special mode is dynamic RA
6. The low power consumption mode in which each circuit of M is activated in consideration of only the information holding operation, claim 1, claim 2, claim 3, claim 4, claim 5, claim 5. 6. The special mode control method for a dynamic RAM according to claim 6 or 7. 9. The special mode is released by performing a refresh operation as a dummy operation, claim 1, claim 2, claim 3, claim 4, claim 5, claim 5. A special mode control method for a dynamic RAM according to claim 6 or 7. 10. As the dummy operation, the refresh operation uses an address strobe signal for multiplexing and inputting a row address signal and a column address signal, and the column address strobe signal is supplied prior to the row address strobe signal. 10. The special mode control method for the dynamic RAM according to claim 9, wherein the special mode control is performed by setting the active level.