JPH05143333A - Parallel arithmetic processor - Google Patents

Abstract

PURPOSE:To make it possible to use the same field as a data storing area by processing the content of an optional instruction word field in an instruction word as NOP data independently of data set up in the field. CONSTITUTION:A VLIW type instruction 10 having instruction fields 11-1 to 11-n is provided with an invalidation specifying field 12 constituted of (n) bits for specifying that the data of the fields 11-1 to 11-n are invalid as original instruction word field data correspondingly to respective bits. When invalidation is specified by the bits 0 to n-1 of the field 12, plural decoders 20-1 to 20-n for decoding the set data of the fields 11-1 to 11-n output signals indicating NOP to their corresponding computing elements 30-1 to 30-n independently of the set data of the fields 11-1 to 11-n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel arithmetic processing device which receives an instruction word composed of a plurality of instruction word fields and processes the operations designated by the respective instruction word fields in parallel, and is particularly invalid. The present invention relates to a parallel arithmetic processing device suitable when a large number of instruction words having an instruction word field exist.

[0002]

2. Description of the Related Art In recent years, an instruction word is divided into a plurality of instruction word fields, and independent arithmetic units are provided corresponding to the individual instruction word fields, and the data set in the corresponding instruction word field for each arithmetic unit. So called VLIW (Very Long Instruction Word)
) System parallel arithmetic processing devices have been developed.

An instruction word applied in this VLIW type parallel arithmetic processing device is called a VLIW type instruction. VLI
Generally, an instruction code (OP code) and operand designation data such as a source and a destination are set in each instruction word field forming the W-type instruction, and the OP designated for the operand designated by the operand designation data is set. The operation specified by the code is performed.

Now, in each instruction execution cycle of the VLIW type parallel arithmetic processing unit, a programmer or a compiler determines which arithmetic unit is to be executed in parallel. Based on the result of this judgment, the programmer or the compiler places the data designating the operation in the instruction word field in the VLIW type instruction corresponding to the arithmetic unit to be operated in parallel. Further, special control data for instructing non-operation, that is, NOP (no operation) data is arranged in the instruction word field in the VLIW type instruction corresponding to the arithmetic unit that does not need to be operated.

In general, instruction processing having a dependency relationship (for example, an instruction A and an instruction B using the operation result of this instruction A)
Instruction processing by etc.) cannot be executed in parallel. In such a case, most of the instruction word fields in the VLIW type instruction are NOP data. Also, in the case of a program in which there are many arithmetic units that do not need to be operated in parallel regardless of the presence / absence of dependence, most of the instruction word fields in the VLIW type instruction are NOP data.

As is well known, since an instruction word is stored in the main memory, a plurality of instruction word fields (setting data)
When there are many instruction words (VLIW type instructions) in which most of the data are NOP data, the utilization efficiency of the main memory area becomes extremely poor.

Therefore, in order to avoid this, another method has been applied in which the NOP data is stored in the main memory as another instruction data with the omission, and when this is read, it is converted into the original instruction format. ..

[0008]

As described above, in the conventional parallel arithmetic processing device, when the arithmetic unit is not operated,
Since the NOP data is set in the instruction word field of the instruction word (VLIW type instruction) corresponding to the arithmetic unit, there is a problem that the utilization efficiency of the main memory for storing the instruction word is poor.

Further, in order to improve the utilization efficiency of the main memory,
There is also a method in which the NOP data is stored as another instruction data that is omitted, and when this is read, it is converted into the original instruction format, but the original instruction format (VLIW type instruction)
Since the instruction format in the main memory is different, the overhead of decoding processing is large, and the instruction length control (where to read) becomes extremely complicated because the instruction length is variable. there were.

The present invention has been made in view of the above circumstances, and an object thereof is to enable the contents of an arbitrary command word field in a command word to be handled as NOP data regardless of the setting data thereof. It is an object of the present invention to provide a parallel arithmetic processing device which makes it possible to use a word field as a data storage area and thereby effectively utilize the main memory.

[0011]

SUMMARY OF THE INVENTION According to the present invention, in a parallel arithmetic processing device having a plurality of arithmetic units that operate in parallel according to the contents of a plurality of instruction word fields in an instruction word, each instruction word field in the instruction word. The invalidation designation data is set in the same command word to indicate whether or not the invalidation data is invalid. Based on the data of this invalidation designation field, the invalidation designation data is invalidated by the data. The invalidation control means for invalidating the operation of the arithmetic unit corresponding to the designated instruction word field is provided, and the instruction word field invalidated in the instruction word can be used as the data storage area. It is a feature.

[0012]

In the above structure, an invalidation designation field is provided in an instruction word (VLIW type instruction) having a plurality of instruction word fields. In this invalidation specification field,
Invalidation designation data is set to indicate whether or not the data in each instruction word field in the same instruction word is invalid, for example, for each instruction word field in bit correspondence.

Such a new format instruction word (VLIW
Type instruction) is fetched from storage means such as main memory or cache, the invalidation control means follows the data in the invalidation designation field of the fetched instruction word, and the instruction word invalidated by the data is specified. The operation of the arithmetic unit corresponding to the field is invalidated regardless of the setting data of the instruction word field. This invalidation control is realized by outputting a signal indicating NOP to the arithmetic unit or invalidating the arithmetic result of the arithmetic unit.

As described above, according to the above configuration, even if NOP data is not set in the command word field, the operation of the arithmetic unit corresponding to the command word field can be invalidated in the same manner as when the NOP is designated. You can Therefore, the command word field where the NOP data is originally set is
By using it as a setting area (data storage area) for constants and variables used by the program, even if there are many invalid command word fields in a command word, this field can be used effectively and efficient use of main memory Can be achieved.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a main part of a VLIW type parallel processing device according to an embodiment of the present invention.

In FIG. 1, reference numeral 10 is a VLIW type instruction to be executed by this apparatus. VLIW type instruction 10
Is invalid as the original instruction word field data for designating the operation etc. in addition to the n instruction word fields 11-1 to 11-n. This is specified by bit correspondence (here, "1"
Has an invalidation designation field 12 of n-bit configuration (bits 0 to n-1).

20-1 to 20-n are VLIWs to be executed
Data of the instruction word fields 11-1 to 11-n of the type instruction 10 and bits 0 to n- of the invalidation designation field 12
Decoders 30-1 to 30-n for inputting the set bit data of 1 and performing decoding processing are provided corresponding to the instruction word fields 11-1 to 11-n of the VLIW type instruction 10, and the field 11-1 is provided. Decoder 20-1 performs operations specified by 11-n
It is an arithmetic unit that executes according to the decoding result of 20 to 20-n.

Next, the operation of the configuration shown in FIG. 1 will be described. First, in the decoding stage of the VLIW type instruction 10, the decoders 20-1 to 20-n correspond to the setting data of the corresponding instruction word fields 11-1 to 11-n in the instruction 10 and the invalidation designation field 12. Bits 0 to n-1 are input respectively.

Each decoder 20-i (i = 1 to n) decodes the input data of the input setting data of the instruction word field 11-i and the setting bit data of the bit i-1 of the invalidation designation field 12. ..

At this time, if the bit i-1 of the invalidation designation field 12 is "1", that is, the bit i-1 indicates that the data of the corresponding instruction word field 11-i is invalid. If so, the decoder 20-i determines that the arithmetic unit 30 is irrelevant to the setting data of the instruction word field 11-i.
It outputs a signal indicating NOP to -i. As a result, the operation of the arithmetic unit 30-i causes the command field 11-i to be NOPed.
Even if the data is not set, it becomes NOP.

On the other hand, if the bit i-1 of the invalidation designation field 12 is "0", that is, the data of the instruction word field 11-i corresponding to the bit i-1 is not invalid (valid). Is indicated, the decoder 20-i decodes the setting data of the instruction word field 11-i and outputs the operation instruction indicated by the data to the arithmetic unit 30-i. As a result, the arithmetic unit 30-i performs the arithmetic operation designated by the instruction word field 11-i.

As described above, according to this embodiment, if the data in the corresponding instruction word field 11-i is indicated by the bit i-1 of the invalidation designation field 12 as invalid, the instruction word is invalid. Even if the NOP data is not set in the field 11-i, the NOP can be designated for the arithmetic unit 30-i, that is, the operation of the arithmetic unit 30-i can be invalidated.

Therefore, it is possible to use the instruction word field 11-i in the VLIW type instruction 10 which has conventionally been required to set NOP data as a storage area for data such as constants and variables used by a program. Becomes An example of using such a VLIW type instruction 10 is shown in FIG.

First, in FIG. 2A, the instruction word field 1 is set by setting "1" in bit 1 of the invalidation designation field 12.
The data of 1-2 is designated to be invalidated (the execution of the operation according to the instruction word field 11-2 is designated to be invalidated), the constant # 1 is set in the same field 11-2, and the constant 11 is set to the constant # 1. An example of the storage area of

In FIG. 2B, "1" is set in bits 0 and n-1 of the invalidation designation field 12 to invalidate and designate the data in the instruction word fields 11-1 and 11-n. Variable # 1 and constant # 2 in the same fields 11-1 and 11-n
And set the same fields 11-1 and 11-n to this variable #
An example in which the storage area for the constant 1 and the constant # 2 is used is shown below.

Further, in FIG. 2C, "1" is set to the bit n-1 of the invalidation designation field 12 to invalidate the data of the instruction word field 11-n, and at the same time, to the field 11-n. An example in which the variable # 2 is set and the same field 11-n is used as the storage area of the variable # 2 will be shown.

As described above, the conventional VLIW type instruction 10 is configured by using the instruction word field in the VLIW type instruction 10 in which the NOP data is set as the data storage area.
It is possible to effectively use an area such as a main memory in which is stored.

Although the VLIW type instruction has an independent invalidation designation field in addition to the instruction word field in the above embodiment, the present invention is not limited to this. For example, when the number n of instruction word fields (decoder, arithmetic unit) is small, a part of the specific instruction word field in the VLIW type instruction may be used as the invalidation designation field. However, in this method, since the area that can be used as the original command word field becomes small, the types of commands that can be specified in the specific command word field are limited.

In the above embodiment, the case where each bit data of the invalidation designation field is supplied to the corresponding decoder has been described. However, it is also possible to directly supply the data to the arithmetic unit to invalidate the operation of the arithmetic unit. Is.

[0030]

As described in detail above, according to the present invention,
The instruction word for parallel operation processing is provided with an invalidation designation field in which invalidation designation data is set to indicate whether or not the data of each instruction word field in the instruction word is invalid. NOP data is set in the instruction word field by providing an invalidation control means for invalidating the operation of the arithmetic unit corresponding to the instruction word field invalidated by the data based on the data in the instruction specification field. Without doing so, it becomes possible to invalidate the operation of the arithmetic unit corresponding to the same command word field, so that the following operational effects can be obtained.

(1) Since the instruction word field in the instruction word for which NOP data should be set in the conventional case can be used as a data storage area for storing constants and variables used by the program, even if parallel Even in the case of a program having a small number of arithmetic units that need to be operated, the main memory area in which the instruction word is stored can be effectively used, and the main memory area is not wasted due to the long instruction word length.

(2) When the command word data in the main memory is read, it is not necessary to convert the command format, and the command word data in the main memory can be directly used as the command format of the command word to be executed. The instruction load at the time of decoding and branching can be easily controlled, and the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a main part of a VLIW system parallel arithmetic processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific example in which an instruction word field in a VLIW type instruction 10 shown in FIG. 1 is used as a data storage area.

[Explanation of symbols]

10 ... VLIW type command (command), 11-1 to 11-n ... Command field, 12 ... Invalidation designation field, 20-1
20-n ... Decoder (invalidation control means), 30-1 to 30
-n ... calculator.

Claims (1)

[Claims] 1. An instruction word is composed of a plurality of instruction word fields, and in order to execute an operation designated by each instruction word field of this instruction word in parallel, an independent operation is made to correspond to each instruction word field. In a parallel arithmetic processing device which is provided with an operation unit and operates each of these arithmetic units in parallel according to the contents of the corresponding instruction word field, an invalid value indicating whether or not the data of each instruction word field in the instruction word is invalid. An invalidation designation field in which the invalidation designation data is set is provided in the same instruction word, and based on the data of the invalidation designation field, the arithmetic unit corresponding to the instruction word field invalidated by the data. The invalidation control means for invalidating the operation of the above is provided, and the instruction word field to be invalidated in the instruction word can be used as a data storage area. Parallel processor according to claim.