JPH05143039A - Cursor generator - Google Patents

Abstract

PURPOSE:To provide the cursor generator which can output cursor data at a high speed with good efficiency by processing pixel data in one complete process. CONSTITUTION:While M-bit data are read out of a RAM 3 having an M*M-bit storage area corresponding to a cursor area of M*M pixels on a graphic screen with one clock, data on the graphic screen which are determined by the number of output pixels are shifted, bit by bit, and the M-bit data are inputted to a parallel-in serial-out type shift register 5 in order in parallel and also transferred, thereby processing the pixel data in one complete process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cursor generator for outputting display data of a cursor displayed on a graphic screen, and more particularly to a cursor generator for outputting a plurality of pixel values.

[0002]

2. Description of the Related Art A monitor for a personal computer or the like is usually 40
0 * 400 (pixel) * 60 (frame / sec), that is, effective about 15 (M
Hz) is sufficient, so only one pixel output can be used, whereas high resolution monitors such as workstations are generally 1280 * 1024 (pixel) * 6.
Since 0 (frame / sec), that is, a frequency of about 80 (MHz) is required, it is not practical to output 1 pixel, and by outputting 5 or 4 pixels with 1 clock,
The effective frequency is set to 4 times or 5 times.

To increase the effective frequency by a factor of 4 or 5, M
The M-bit data of the RAM having the M * M-bit storage area corresponding to the * M-pixel cursor area, that is, the data of the pixel row in the horizontal (horizontal direction) row of the cursor is divided into several bits and output. 4 more in another part
Alternatively, it may be divided into 5 bits, and processing may be performed later so as to connect the division breaks neatly. According to this, as the number of output bits from the RAM is small and the number of wiring lines is reduced,
That part can be made compact.

[0004]

However, in such a method, since it is necessary to perform a process of neatly connecting the breaks of the division after the division, the structure of the portion for joining is complicated and the data is output. However, there is a drawback that it is disadvantageous in terms of increasing the output speed and increasing the efficiency, because it requires several processes before the process.

Therefore, an object of the present invention is to provide a cursor generator capable of outputting cursor data at high speed and efficiently by processing pixel data in one integrated process.

[0006]

In the cursor generator according to the present invention, a memory having a memory area of M * M bits corresponding to a cursor area of M * M pixels on a graphic screen is input in parallel in units of a plurality of bits. A parallel input serial output type shift register that transfers data in sequence and outputs serially, and at the same time reading M-bit data from the memory in one clock, while shifting data on a graphic screen determined by output conditions in bit units. A control means for controlling so as to sequentially input M bits of data in parallel to the parallel input serial output type shift register is provided.

[0007]

In the cursor generator for outputting a plurality of pixel values, the pixel data of one horizontal (horizontal) row of the cursor, which is the output data corresponding to the horizontal scanning period in which the highest speed operation is required, is a slow-moving memory. By reading from the RAM in one clock, the load on high-speed operation can be reduced. Further, since it is only necessary to shift and set the data at the same time as reading the data from the RAM and to transfer the data set by the structure of the shift register as it is, it is not necessary to perform the joining process by dividing the data into a plurality of bits. As a result, since the pixel data can be processed by one integrated process, the cursor data can be output at high speed and efficiently.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a system block diagram showing an embodiment of a cursor generator according to the present invention. In addition,
It is assumed that a cursor in an area of M * M pixels is displayed on a graphic screen (not shown), and in this embodiment, M
A case of = 64 will be described as an example.

In the figure, an MPU (microprocessor) interface 1 is connected via a bus line 2 to a host computer (not shown) and a RAM 3 which is a slow-moving memory. RAM3 is M * corresponding to the cursor area of M * M pixels on the graphic screen.
It has an M-bit storage area. In this RAM3,
Pixel data corresponding to a cursor having a desired shape is stored.

The coordinate position information of the cursor is input to the MPU interface 1 from a mouse or the like, and the MPU interface 1 specifies the X and Y coordinates for the cursor position detection circuit 4 based on this input information. The cursor position detection circuit 4 detects the designated X coordinate position on the graphic screen by counting the clock (CK), and the designated X coordinate position on the graphic screen by counting the horizontal synchronizing pulse (H-sync). By detecting the Y coordinate position, the position detection clock is supplied to the RAM 3 at the X and Y coordinate positions designated by the MPU interface 1, and the data on the graphic screen determined by the output condition (number of output pixels) of the cursor data. The bit information to be shifted is supplied to the shift register 5.

Here, a case will be described as an example in which when outputting cursor data on a graphic screen, data for 5 pixels which cannot be represented by a plurality of pixel values, for example, 2 ^N , is output in one clock. In FIG. 2, the relationship between the pixel data output on the graphic screen and the clock timing is normally as shown in (a).
When it is desired to output the pixel data at the position of (b) with respect to the coordinates of (a), the timing of the clock of (a) cannot be changed. Therefore, the data of (a) corresponds to the position of (b) by 2 bits. Only, and outputs at the timing of (a). As a result, as shown in (c), data for 5 pixels can be output from the specified position in one clock. The number of bits to be shifted is supplied from the cursor position detection circuit 4 to the shift register 5 as the previous shift bit information.

From the RAM 3, the cursor position detecting circuit 4
When the position detection clock is supplied from, the 64-bit pixel data corresponding to one horizontal (horizontal) pixel row of the cursor is read in one clock, and these pixel data are supplied to the shift register 5. The shift register 5 is a parallel in (parallel input) -serial out (serial output) type shift register, and shifts the pixel data output from the RAM 3 based on the shift bit information supplied from the cursor position detection circuit 4. The cursor data to the target position with an arbitrary number of pixels,
For example, 5, 4, or 1 pixel is output.

The parallel-in / serial-out type shift register 5 outputs the cursor data output condition (output pixel number) by 5, 4 or 1 pixel at a time,
As shown in FIG. 3, five shift registers 51a to 51e corresponding to the maximum value “5” are provided, and pixel data from the RAM 3 is input gate circuit 52 to correspond to the output condition of the cursor data among the shift registers 51a to 51e. Input to the registered register in parallel while the output gate circuit 53
The serial output is performed in sequence. This serial output data is output as cursor data of the number of pixels according to the output conditions via the output format circuit 6.

In the present example, three of the five shift registers 51a to 51e are 17 bits and one is 16 bits, and one is 16 in correspondence with the output of 4 pixels which is the output condition of the cursor data.
Bit, the remaining one has 13 bits,
A total of 80 (= 1 for 64-bit set data)
7 * 3 + 16 + 13) bit registers are prepared.

Next, a method of setting data in the parallel-in / serial-out type shift register 5 will be described. FIG. 4 shows the case where the number of output pixels is "5",
(A) is the case where the number of shift bits is 0, (b) is the case where the number of shift bits is 1, (c) is the case where the number of shift bits is 2,
(D) shows the case where the number of shift bits is 3, and (e) shows the case where the number of shift bits is 4. FIG. 5 shows the case where the number of output pixels is “4”, (a) shows the case where the shift bit number is 0, (b) shows the case where the shift bit number is 1,
(C) shows the case where the number of shift bits is 2, and (d) shows the case where the number of shift bits is 3.

As apparent from FIGS. 4 and 5, as shown by the positions of 64 numbers (0 to 63) in each output condition, the number of output pixels (5 , 4) and the number of shift bits (0 to 4), data is set in each 80-bit register.

For 1 pixel output, the number of shift bits is considered to be 0 bit, and data is set in the same manner as in the case of 4 pixel output and the number of shift bits is 0 bit. For example, a 2 bit counter is externally provided. By using
This can be achieved by making the clocks valid in order from the left of the four-row shift registers 51a to 51d and collecting the four-row output data in one place.

Due to the operation of the parallel-in-serial-out type shift register 5, a plurality of pixel value outputs including a number that cannot be represented by 2 ^N can be dealt with, and moreover, pixel data can be processed by one integrated process. Pixel data output through the above can be output in a form that is well connected by satisfying the output condition, and at high speed and efficiently, only by transferring the pixel data in the shift register 5.

In the above embodiment, the case where the pixel data output conditions are 5, 4, and 1 has been described, but for data transfer in a graphic display system in which the number of output pixels other than these is not so large, , By expanding the structure according to the number of output pixels.

[0020]

As described above, according to the present invention,
In a cursor generator that outputs multiple pixel values,
The load for high-speed operation can be reduced by reading the pixel row data for one row (horizontal direction) of the cursor, which is the output data corresponding to the horizontal scanning period in which the highest-speed operation is required, from the slow RAM in 1 clock. , And RA
Since it is only necessary to perform the shift setting at the same time as reading the data from M and to transfer the data set by the structure of the shift register as it is, there is no need to perform the joining process by dividing the data into a plurality of bits. Since the data can be processed in one integrated process, it is possible to output the data at high speed and efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a cursor generator according to the present invention.

FIG. 2 is a timing chart showing the relationship between pixel data and clocks when outputting 5 pixels.

FIG. 3 is a block diagram showing an example of a configuration of a parallel-in-serial-out type shift register.

FIG. 4 is a state diagram of a data set to a parallel-in / serial-out type shift register when outputting 5 pixels.

FIG. 5 is a state diagram of a data set to a parallel-in / serial-out type shift register when outputting 4 pixels.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 MPU interface 3 RAM 4 Cursor position detection circuit 5 Parallel in-serial out type shift register 51a to 51e Shift register 52 Input gate circuit 53 Output gate circuit

Claims (1)

[Claims] 1. A memory having a memory area of M * M bits corresponding to a cursor area of M * M pixels on a graphic screen, and parallel input for sequentially transferring and serially outputting data input in parallel in units of a plurality of bits. A serial output shift register and M bits of data are read from the memory in one clock, and at the same time, data of M bits are shifted in units of bits on a graphic screen determined by output conditions, and the data of M bits is input in parallel. A cursor generator comprising: a control unit for controlling parallel input to the output type shift register in order.