JPH0514192A - Digital phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To shorten the time till synchronization is established even when the frequency of input occurrence of phase information is low by providing a frequency division ration adjustment circuit storing a phase comparison signal and outputting a phase control signal at a frequency of occurrence based on the result of storage to the relevant circuit. CONSTITUTION:The offset direction of a clock signal with respect to a synchronization object signal from an input terminal 9 is detected by an offset direction detection circuit 4 counting a clock from an oscillation circuit 8 and a phase comparison signal with respect to a frequency division clock from a variable frequency division circuit 7 is outputted by a phase comparator circuit 2. The comparison signal is stored in a frequency division ration adjustment circuit 5 and a frequency division ratio decision circuit 6 is controlled by a 2nd control signal outputted based on the frequency of occurrence of the result of storage of the circuit 5 together with a 1st control signal outputted from a sequential loop filter 3 and the variable frequency division circuit 7 is controlled by a frequency division ratio control signal outputted from the circuit 6. Through the constitution of provision of the frequency division ratio adjustment circuit as above, even when the frequency of input occurrence of phase information is low, the time till the synchronization is established is less and the locking is implemented at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase lock circuit, and more particularly to a digital phase lock circuit for generating a clock phase-locked with an input signal.

[0002]

2. Description of the Related Art FIG. 4 shows "How to use PLL-IC; pp14
6 to pp154; Akiha Shuppan; Hata and Furukawa, Co., Ltd.].

In the digital phase locked loop circuit (51), the oscillator circuit (8) outputs a predetermined fixed frequency clock signal (Cf) to the variable frequency divider circuit (57).

The variable frequency dividing circuit (57) divides the fixed frequency clock signal (Cf) into 1 / M to generate an output clock signal (Co), and the phase comparison circuit (52) and output terminal (60). Output to. The frequency division ratio 1 / M will be described later.

The phase comparison circuit (52) has an input terminal (5
9) The phase information (Pi) input from 9) is compared with the output clock signal (Co) to determine whether the output clock signal (Co) is “advanced” or “delayed” with respect to the signal to be synchronized (not shown). If it is determined to be “advance”, <+1> is output to the sequential loop filter (53), and if “delayed”, <−1> is output to the sequential loop filter (53).

Sequential loop filter (53)
Has a bidirectional counter whose count value changes from "+ N" to "-N". Then, the output of the phase comparison circuit (52) is added to the count value of the bidirectional counter, and when the count value reaches "+ N" as a result, the "advancing phase control" signal is output to the variable frequency dividing circuit ( 57) and, on the other hand, when the count value reaches "-N", the "delay phase control" signal is output to the variable frequency dividing circuit (57). Also, the count value is reset to "0" after the "leading phase control" signal or the "forward phase control" signal is output. This is a so-called random walk filter.

The variable frequency dividing circuit (57) changes the frequency dividing ratio from the reference frequency dividing ratio 1 / M to a new frequency dividing ratio when the "advancing phase control" signal is inputted from the sequential loop filter (53). Change to 1 / (M + 1). On the other hand, when the "lag phase control" signal is input, the reference frequency division ratio 1 / M is changed to a new frequency division ratio 1 / (M-1). Then, after the next output clock signal (Co), the division ratio is returned to the reference division ratio 1 / M.

FIG. 5 shows the digital phase lock circuit (5
In 1), the signal to be synchronized and the output clock signal (C
It is a schematic diagram which shows how the phase difference of o) changes with time. The horizontal axis indicates the timing of appearance of the output clock signal (Co), and the vertical axis indicates the phase difference between the signal to be synchronized and the output clock signal (Co). The phase difference is
Expressed by the number of pulses of the fixed frequency clock signal (Cf), the output clock signal (Co) is output with respect to the signal to be synchronized.
<+> When is advanced and <-when is delayed
>. Six pulses of the fixed frequency clock signal (Cf) correspond to the phase difference π. ● indicates phase information (Pi)
Is input. The sequential loop filter (53) has N = 1. In the variable frequency dividing circuit (57), M = 12 has a reference frequency dividing ratio. Further, it is assumed that the frequency offset of the fixed frequency clock signal (Cf) with respect to the signal to be synchronized is “advanced” by 0.5 pulse of the fixed frequency clock signal (Cf).

First, at the # 1 pulse of the output clock signal (Co), the output clock signal (Co) is ahead of the signal to be synchronized by four pulses of the fixed frequency clock signal (Cf) (position). Phase difference <+4>). At this time, since the phase information (Pi) is input, the phase comparison circuit (52)
<+1> is output to the sequential loop filter (53). Then, the sequential loop filter (5
3) is a variable frequency dividing circuit (57) for the "leading phase control" signal.
Output to. As a result, the variable frequency dividing circuit (57)
= 13. As a result, the lead of the output clock signal (Co) is about to be corrected by 3 pulses (phase difference <+3>), but the offset of the fixed frequency clock signal (Cf) is “lead” by 0.5 pulse. Therefore, in the case of the # 2 pulse of the output clock signal (Co), the total phase difference is corrected to advance by 3.5 pulses (phase difference <+
3.5>).

In the case of the # 2 pulse of the output clock signal (Co), the phase difference is <+3.5>. At this time, since the phase information (Pi) is not input, only the “advance” of 0.5 pulses of the offset of the fixed frequency clock signal (Cf) is effective, and when the output clock signal (Co) is the pulse # 3. , The phase difference becomes <+4.0>.

Thereafter, similarly, the output clock signal (C
When the pulse of (o) appears, a total of 0.5 pulse is corrected when the phase information (Pi) is input, and a total of 0.5 pulse is corrected when the phase information (Pi) is not input. The progress is added.

In the example of FIG. 5, since the frequency of inputting the phase information (Pi) is high, the frequency of correcting the phase difference is high, and it is easy to bring the phase information into the synchronized state. FIG. 6 is a diagram corresponding to FIG. 5 when the frequency of inputting the phase information (Pi) is low. Since 6 pulses of the fixed frequency clock signal (Cf) correspond to the phase difference π, the phase difference is folded back from <+6> to <-6>. When the frequency of inputting the phase information (Pi) is low as shown in FIG. 6, the frequency of correcting the phase difference is low, and it is difficult to bring the phase information into the synchronized state.

[0013]

In the conventional digital phase synchronizing circuit 51, the frequency of correcting the phase difference is determined by the frequency of inputting the phase information (Pi). For this reason, when the frequency of inputting the phase information (Pi) is low, it is difficult to pull in the synchronization state, it takes time to establish synchronization, and the pull-in range (width of frequency offset that can be pulled into the synchronization state) becomes narrow. There is a problem.

The present invention has been made in order to solve the above-mentioned problems. Even when the frequency of inputting phase information is low, it takes no time to establish synchronization and the pull-in range is not narrowed. The purpose is to provide a circuit.

[0015]

SUMMARY OF THE INVENTION A digital phase locked loop circuit of the present invention includes an oscillator circuit for outputting a predetermined fixed frequency clock signal and an offset circuit for detecting and outputting an offset direction of the fixed frequency clock signal with respect to a signal to be synchronized. A direction detection circuit, a phase comparison circuit that detects a phase difference of an output clock signal with respect to a signal to be synchronized and outputs a phase comparison signal generated according to a predetermined rule based on the phase difference and the offset direction; A sequential loop filter that outputs a first phase control signal based on a comparison signal; a frequency division ratio adjustment circuit that accumulates the phase comparison signal and outputs a second phase control signal at a frequency based on the accumulation result; A frequency division ratio determining circuit that outputs a frequency division ratio control signal based on the first and second phase control signals, and the frequency division ratio control signal Zui by setting the division ratio, characterized by comprising; and a variable frequency dividing circuit to divide and output clock signal the fixed frequency clock signal at its division ratio.

[0016]

In the digital phase synchronizing circuit of the present invention, the frequency division ratio adjusting circuit accumulates the phase comparison signal and outputs the second phase control signal at a frequency based on the accumulation result, so that the frequency of inputting the phase information is low. Even in such a case, it takes no time until the synchronization is established, and the pull-in range does not become narrow.

[0017]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a block diagram showing the configuration of a digital phase locked loop circuit according to an embodiment of the present invention. The digital phase synchronization circuit (1) includes a phase comparison circuit (2), a sequential loop filter (3), an offset direction detection circuit (4), a frequency division ratio adjustment circuit (5), a frequency division ratio determination circuit (6), It is composed of a variable frequency dividing circuit (7) and an oscillation circuit (8).

In the digital phase locked loop circuit (1), the oscillator circuit (8) outputs a predetermined fixed frequency clock signal (Cf) to the offset direction detecting circuit (4) and the variable frequency dividing circuit (7).

The offset direction detection circuit (4) counts the input interval of the phase information (Pi) input from the input terminal (9) with the fixed frequency clock signal (Cf), and this count value is a variable frequency divider circuit. If there is a multiple of the reference frequency division ratio of (7) or is very close to that multiple, "no offset" is output to the phase comparison circuit (2), and if it is larger than the closest multiple of the count value, "positive offset". Is output to the phase comparison circuit (2), and when it is smaller than the nearest multiple of the count value, a "negative offset" is output to the phase comparison circuit (2).

The variable frequency dividing circuit (7) divides the fixed frequency clock signal (Cf) into 1 / M to generate an output clock signal (Co), and the phase comparison circuit (2) and output terminal (10). Output to. The frequency division ratio will be described later.

The phase comparator circuit (2) receives the phase information (Pi) input from the input terminal (9) and the output clock signal (C).
o) and compares the phase difference of the output clock signal (Co) with respect to the signal to be synchronized (not shown) to "advance"<L / 2.
> Stage and “delay” <L / 2> stage of L stage. Then, based on the evaluation result of the phase difference and the output from the offset direction detection circuit (4), <+1> or <-1> is added to the sequential loop filter (3) according to the following rules (a) to (f). And the frequency division ratio adjusting circuit (5).

(A) If the phase difference is between "advance" from the first stage to the K stage, <+1> is output to the sequential loop filter (3) and the frequency division ratio adjusting circuit (5) (where 1≤). K <L / 2). (B) If the phase difference is "leading" (K
When the output from the offset direction detection circuit (4) is a "negative offset" between the +1) stage and the L / 2 stage, <-1> is set to the sequential loop filter (3) and the frequency division ratio adjustment circuit ( Output to 5). (C) From the (K + 1) stage where the phase difference is “advanced” to the L / 2 stage,
When the output from the offset direction detection circuit (4) is not "negative offset", <+1> is output to the sequential loop filter (3) and the frequency division ratio adjustment circuit (5). (D) If the phase difference is between the first stage and the K stage of "delay", <-1> is output to the sequential loop filter (3) and the division ratio adjusting circuit (5). (E)
When the output from the offset direction detection circuit (4) is a "positive offset" between the (K + 1) stage and the L / 2 stage where the phase difference is "delay", <+1> is set to the sequential loop filter (3). And the frequency division ratio adjusting circuit (5). (F) The offset direction detection circuit (4) between the (K + 1) stage and the L / 2 stage in which the phase difference is “delayed”.
<-1 if the output from is not a "positive offset"
> Is output to the sequential loop filter (3) and the frequency division ratio adjusting circuit (5).

FIG. 2 illustrates the above rule when L = 12 and K = 3.

The sequential loop filter (3) is
It has a bidirectional counter whose count value changes from "+ N" to "-N". Then, the output of the phase comparison circuit (2) is added to the count value of the bidirectional counter, and when the count value reaches "+ N" as a result, the "advance phase control" signal is output to the frequency division ratio determination circuit. Output to (6). On the other hand, when the count value reaches "-N", the "lag phase control" signal is output to the frequency division ratio determination circuit (6).
Also, the count value is reset to "0" after the "leading phase control" signal or the "forward phase control" signal is output. This is a so-called random walk filter.

The frequency division ratio adjusting circuit (5) includes a bidirectional counter whose count value changes from "+ J" to "-J". Then, when the output of the phase comparison circuit (2) is added to the count value of the bidirectional counter and the count value is <+ H>, H times per J pulses of the output clock signal (Co). At the frequency of, the "leading phase control" signal is output to the frequency division ratio determination circuit (6). Also,
When the count value is <-H>, the "delay phase control" signal is output to the frequency division ratio determination circuit (6) at a frequency of H times per J pulses of the fixed frequency clock signal (Cf). ..

The frequency division ratio determining circuit (6) transmits the output from the sequential loop filter (3) and the output from the frequency division ratio adjusting circuit (5) to a variable frequency dividing circuit (7).

The variable frequency dividing circuit (7) receives the "advancing phase control" signal from the sequential loop filter (3) and the frequency dividing ratio adjusting circuit (5).
The division ratio is changed from the reference division ratio 1 / M to the new division ratio 1 / (M +
Change to 1). On the other hand, when the "lag phase control" signal is input, the new division ratio 1 / M is changed from the reference division ratio 1 / M.
Change to (M-1). Then, after the next output clock signal (Co), the division ratio is returned to the reference division ratio 1 / M.

FIG. 5 is a schematic diagram showing how the phase difference between the signal to be synchronized and the output clock signal (Co) temporally changes in the digital phase locked loop circuit (1). The conditions are the same as in the case of FIG.
However, it is assumed that the frequency division ratio adjusting circuit (5) has J = 50.

First, at the # 1 pulse of the output clock signal (Co), the output clock signal (Co) leads the signal to be synchronized by four pulses of the fixed frequency clock signal (Cf) (position). Phase difference <+4>). At this time, since the phase information (Pi) is input, the phase comparison circuit (2) evaluates the phase difference <+4> as the fourth step of “advance”, and the offset direction detection circuit (4) outputs “positive”. Since "offset" is input, <+1> is output to the sequential loop filter (3) and the frequency division ratio adjusting circuit (5). Then, the sequential loop filter (3) outputs a "leading phase control" signal to the variable frequency dividing circuit (7). As a result, the variable frequency dividing circuit (7) sets M = 13. As a result, the lead of the output clock signal (Co) is about to be corrected by 3 pulses (phase difference <+3>), but the offset of the fixed frequency clock signal (Cf) is “lead” by 0.5 pulse. Therefore, the output clock signal (Co) # 2
, The total phase difference is corrected to the advance of 3.5 pulses (phase difference <+3.5>). The count value H in the frequency division ratio adjusting circuit (5) becomes <+1>.

When the pulse # 2 of the output clock signal (Co), the phase difference is <+3.5>. At this time, since the phase information (Pi) is not input, only the “advance” of 0.5 pulses of the offset of the fixed frequency clock signal (Cf) is effective, and when the output clock signal (Co) is the pulse # 3. , The phase difference becomes <+4.0>.

Similarly, when the pulse of the pulse output clock signal (Co) appears, if the phase information (Pi) is input, a correction of 0.5 pulses is made in total, and the phase information (Pi) is corrected. When there is no input, the total is 0.
The advance of 5 pulses is added. The count value H in the frequency division ratio adjusting circuit (5) is obtained from the phase comparing circuit (2) as <+1>.
Increases each time is input.

When the output clock signal (Co) is # 9,
When the phase difference exceeds <+6>, 6 pulses of the fixed frequency clock signal (Cf) correspond to the phase difference π, so the phase difference folds back to the delay side. Therefore, the output clock signal (C
At the time of # 10 of o), the phase difference becomes <−5.5>.

When the output clock signal (Co) is # 10,
The phase difference is <-5.5>. At this time, the phase information (P
Since there is an input of i), the phase comparison circuit (2) evaluates the phase difference <−5.5> as the fifth stage of “delay”, and the offset direction detection circuit (4) gives a “positive offset”. Since it is input, <+1> is output to the sequential loop filter (3) and the frequency division ratio adjusting circuit (5). Then, the sequential loop filter (3) outputs a "leading phase control" signal to the variable frequency dividing circuit (7). As a result, the variable frequency dividing circuit (7) sets M = 13. As a result, the phase difference tends to be delayed by one pulse,
Fixed frequency clock signal (Cf) offset is 0.5
Since the pulse signal is “advanced”, the total phase difference is delayed by 0.5 pulse and becomes the phase difference <−6> at the time of the # 11 pulse of the output clock signal (Co). The count value H in the frequency division ratio adjusting circuit (5) is incremented by 1 and <+
3>.

Thereafter, similarly, the phase difference changes as shown by the solid line in FIG. The count value H in the frequency division ratio adjustment circuit (5) increases each time <+1> is input from the phase comparison circuit (2).

Although not shown in FIG. 3, when the count value H is, for example, <+3>, the frequency division ratio adjusting circuit (5)
Frequency division ratio determination circuit (6) for the "leading phase control" signal at a frequency of 3 times per 50 pulses of the output clock signal (Co)
Output to. Since the count value H increases, the frequency that the frequency division ratio determining circuit (6) outputs also increases. When the phase information (Pi) is input, both the output of the sequential loop filter (3) and the output of the frequency division ratio determination circuit (6) are added to the variable frequency division circuit (7). Therefore, even if the frequency of inputting the phase information (Pi) is low, it takes no time until the synchronization is established, and the pull-in range does not become narrow.

When there is a synchronization probability, the phase comparison circuit (2)
The appearance frequencies of <+1> and <-1> from are equal, and the count value H converges to a certain value. This convergence value represents the frequency offset.

[0037]

According to the digital phase locked loop circuit of the present invention, the phase control can be activated at an appropriate frequency even when the frequency of inputting the phase information is low. Therefore, it is possible to speed up the pull-in. Also, the pull-in range can be expanded.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital phase locked loop circuit according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram of an output rule of a phase comparison circuit.

FIG. 3 is a chart for explaining the operation of the digital phase locked loop circuit of FIG.

FIG. 4 is a block diagram showing a configuration of an example of a conventional digital phase synchronization circuit.

5 is a chart for explaining the operation of the digital phase locked loop circuit of FIG. 4. FIG.

FIG. 6 is another chart for explaining the operation of the digital phase locked loop circuit of FIG.

[Explanation of symbols]

 1 Digital phase synchronization circuit 2 Phase comparison circuit 3 Sequential loop filter 4 Offset direction detection circuit 5 Frequency division ratio adjustment circuit 6 Frequency division ratio determination circuit 7 Variable frequency division circuit 8 Oscillation circuit 9 Input terminal 10 Output terminal

Claims (1)

Claim: What is claimed is: 1. An oscillator circuit that outputs a predetermined fixed frequency clock signal, an offset direction detection circuit that detects and outputs an offset direction of the fixed frequency clock signal with respect to a signal to be synchronized, and a synchronization target. A phase comparison circuit for detecting a phase difference of the output clock signal with respect to the signal of (1) and outputting a phase comparison signal generated according to a predetermined rule based on the phase difference and the offset direction; and a first phase comparison circuit based on the phase comparison signal. A sequential loop filter that outputs a phase control signal, a frequency division ratio adjustment circuit that accumulates the phase comparison signal and outputs a second phase control signal at a frequency based on the accumulation result, and the first and second phase controls A frequency division ratio determining circuit that outputs a frequency division ratio control signal based on the signal, and a frequency division ratio setting circuit that sets the frequency division ratio based on the frequency division ratio control signal. In digital phase locked loop characterized by comprising comprises a variable frequency divider circuit wherein the fixed frequency clock signal to the frequency dividing an output clock signal.