JPH05138947A - Image forming device - Google Patents

Abstract

PURPOSE:To make it easy to express intermediate tone of image and to process at high speed by fetching data from frame memories so as to calculate and storing the calculated result in corresponding frame memories. CONSTITUTION:A color control means separates colors based on a designated color and sets pattern of each original color, and informs pattern generating means 15-17. After a preparation for generating pseudo-intermediate gradation is made, the pattern generating means 15-17 inform a color control means 18. When there is provided an instruction of drawing such as diagram, an image forming means 14 outputs drawing data to calculation means 19-21. Thus, the calculation means 19-21 operate in parallel, fetch the drawing data from the image forming means 14, data from the corresponding pattern generating means 15-17, and data from corresponding frame memories 11-13 and calculate them. The calculated result is stored in the frame memories 11-13, so that patterns of each original color expressed with intermediate tone are drawn in the frame memories 11-13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus applied to a multicolor image output apparatus such as a color printer.

[0002]

2. Description of the Related Art For example, as shown in FIG. 10, a printing apparatus using an electrophotographic system fetches a command and data from a host computer 1 into a bitmap creating apparatus 3 via a communication control unit 2 to create a bitmap. The device 3 draws an output image in the bitmap format on the frame memory 4 based on an instruction and data. The output image thus drawn on the frame memory 4 is printed out on paper by the print engine (printing unit) 5. For example, in a laser beam type electrophotographic printing apparatus, the laser beam is modulated according to the bit string read from the frame memory 4, the electrostatic latent image is recorded on the photosensitive member, and the electrostatic latent image is developed with toner. It is designed to be transferred and printed on recording paper. Normally 1 on the frame memory 4
If the bit value is "1", it becomes a black dot.

When a halftone image is printed by such a printing apparatus, a two-dimensional array of dots on the output paper surface is divided into rectangular grids of the same size. That is, the same number of dots belong to each lattice, and if some dots are made black and the remaining dots are made white in each lattice, halftone can be approximately represented. For example, in one lattice n
If the dots belong, then from white to black (n +
1) The step can be expressed, and when the number of dots to be black in the grid is determined, the position of the dot to be black is determined using a dedicated algorithm. Of FIG.
(a) shows an example in which one grid is formed by four dots, and one of the dots is black. When a triangular figure using such a lattice pattern is filled,
The results shown in (b) are obtained. That is, a triangle in which black is printed in 25% halftone is obtained.

Therefore, if a figure or the like is drawn on the frame memory 4 in such a lattice pattern, halftone printing can be approximately performed. It should be noted that if the number of dots in one grid is increased, halftones can be expressed at a finer stage.

In the print engine 5, for example, when outputting dots in four stages from white to black, every two bits are collectively associated with one dot. That is, "00"
Is a white dot, “11” is a black dot, and “01” and “10” are different halftone dots. In forming an image on the frame memory 4 in this case, first, the original bitmap is laterally doubled. Subsequently, a grid is created in units of 2 bits, and a grid pattern is created so as to show a desired halftone. Then, by drawing with the grid pattern created on the frame memory 4, a desired halftone image can be obtained.

Further, for example, in a printing apparatus, when it is desired to obtain a designated color, high quality printing can be performed by mixing ink so that the designated color is obtained and performing solid printing. Further, when it is desired to obtain a designated color in a display device, the color can be expressed by using a display element of that color.

However, since these methods require a very complicated device, they are not very feasible, and in practice, designated colors are expressed by using several kinds of primary colors. That is, the desired color is separated into three or four colors, and the designated color is expressed using three or four color inks or display elements.

Therefore, in the color printing apparatus,
For example, when three primary colors of yellow, magenta and cyan are used, three frame memories are used corresponding to each primary color. And if there is a color designation, the designated color is 3
Separated into primary colors. For example, yellow 80%, magenta 5
%, Cyan 7%. Then, the pattern of each primary color is drawn in each frame memory by a drawing command of a figure or a character. That is, the frame memory for yellow has 8
Drawing is performed in 0% halftone, 5% is drawn in the magenta frame memory, and 7% is drawn in the cyan frame memory. Then, if the print engine prints out the primary colors of yellow, magenta, and cyan on the recording paper based on the pattern drawn in each frame memory, the specified color can be printed. As a data creation method for such color printing, for example, those disclosed in Japanese Patent Laid-Open Nos. 2-55265 and 2-273826 are known.

The former one is designed to sequentially form a pattern of characters and figures in each frame memory (bitmap memory) by using the color separation method described above, and the latter one is It is designed to access a plurality of memories at the same time to create a pattern of characters and figures.

[0010]

However, although the former one is capable of halftone expression, there is a problem that drawing processing takes time because the frame memories for each primary color are separately accessed, and the latter one. Is capable of high-speed processing because it accesses multiple memories at the same time, but there is a problem that halftone expression cannot be performed. Therefore, the present invention is intended to provide an image forming apparatus for forming a multicolor image, which can relatively easily express halftone images and perform high-speed processing.

[0011]

According to the present invention, as shown in FIG. 1, a plurality of frame memories (storage means) 11 for storing an output image corresponding to each primary color used for printing or displaying,
12, 13 and image creating means 14 for outputting drawing data based on the drawing color designation to create an output image, and the frame memories 11 to 13 which are provided in correspondence with each other and are for generating pseudo halftones. A plurality of pattern generating means 15, 16, 1
7, and color control means 18 for performing color separation based on a designated color to set a pattern for each primary color, and for causing each pattern generation means 15 to 17 to prepare for generation of pseudo halftones by the pattern for each primary color. The drawing data from the image creating means 14, the data from the corresponding pattern generating means 15 to 17 and the data from the corresponding frame memories 11 to 13 are provided corresponding to each of the frame memories 11 to 13 and the calculation is performed. Frame memory 1
1 to 13 are provided with a plurality of arithmetic means 19, 20 and 21 that operate in parallel with each other.

[0012]

In the present invention having such a structure, when the drawing color is designated, the color control means 18 performs color separation based on the designated color to set the pattern of each primary color, and the pattern generation means 15 to 17 are set. Notice. As a result, each of the pattern generating means 15 to 17 prepares for the generation of the pseudo halftone, and when the preparation is completed, the color controlling means 18 is notified of it. In this way, the drawing color designation process is completed. Then, when there is an instruction to draw a figure or the like, the image forming means 14 outputs drawing data to the respective arithmetic means 19 to 21. As a result, each computing means 19-21
Operate in parallel, fetch drawing data from the image creating means 14, data from the corresponding pattern generating means 15 to 17 and data from the corresponding frame memories 11 to 13 and perform an operation and correspond the operation result. The frame memories 11 to 13 are respectively stored. In this way, the patterns of the respective primary colors expressed in the halftone are drawn in the respective frame memories 11 to 13.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the invention is applied to the image formation of a color page printer.

In FIG. 2, reference numeral 31 is a main processing unit for controlling the entire apparatus and creating an output image, which is a CPU, ROM, RAM.
And a non-volatile RAM. Reference numeral 32 denotes an externally connected host computer, which transmits commands and data regarding printing to the image forming apparatus. A communication control unit 33 controls communication with the host computer 32 and sequentially transmits the received commands and data to the main processing unit 31. The main processing unit 31 takes in commands and data from the communication control unit 33, and sends an error state and an execution state to the communication control unit 33. The communication control unit 33 is the main processing unit 3.
When an error status or an execution status is received from 1, the information is transmitted to the host computer 32.

Reference numeral 34 denotes a color calculation unit which performs conversion of a numerical expression of a designated color and conversion of a color that cannot be output by this device by a color that can be output. Reference numeral 35 denotes a density calculation unit, which separates the color processed by the color calculation unit 34 into four primary colors of yellow, magenta, cyan, and black, and determines the halftone of each primary color, that is, the density (0 to 100%). It is designed to process. 36 is a pattern designating section,
A halftone pattern is created for each primary color based on the density. 37a, 37b, 37c, 37d
Is a pattern command bus for transmitting the designation of the lattice pattern and transmitting a signal indicating the end of pattern development in the opposite direction.

A pattern set flag 38 is reset by the main processing unit 31 and set by the color computing unit 34. A QP signal is supplied from the pattern set flag 38 to the main processing section 31 and the font processing section 39. 40
Is a font active flag, which is the font processing unit 3
It is reset at 9 and set by the main processing section 31. The QF signal is supplied from the font active flag 40 to the main processing unit 31, the multiplexer 41 and the demultiplexer 42.

As shown in FIG. 3, the font processing unit 39 is a font control unit 391 that controls the entire processing unit and sends and receives commands and data to and from other parts, and a font that stores font data such as an outline font. A data storage unit 392, a character generation unit 393 that creates bitmap data of characters from the font data from the font data storage unit 392, and a font cache 394 that holds the bitmap data created by the character generation unit 393 for each character. It is composed by.

The font control unit 391 outputs the bit map data of characters to the outside according to an instruction from the main processing unit 31. That is, the font processing unit 39 converts the bit map data of the character into the character drawing bus 4
It outputs 3 bytes one by one.

Reference numeral 44 is a main drawing bus, 45 is a common drawing bus, and each of the buses 44, 45 and the character drawing bus 43 is a set of a data bus, an address bus, an address transmission signal and a data transmission signal.

The multiplexer 41 sends the signal of the character drawing bus 43 to the common drawing bus 45 when the QF signal from the font active flag 40 is on, and the signal of the main drawing bus 44 when the QF signal is off. Is sent to the common drawing bus 45. The demultiplexer 42 sends the all-data confirmation signal AC from the 4-input AND circuit 46 to the font processing section 39 when the QF signal from the font active flag 40 is on, and when the QF signal is off. The all data confirmation signal AC is sent to the main processing section 31.

A data confirmation signal D from the color plate creating sections 47, 48, 49 and 50 is applied to each input terminal of the AND circuit 46.
C1, DC2, DC3, and DC4 are input.

Each of the color plate producing units 47 to 50 has the same configuration. For example, the configuration of the color plate producing unit 47 will be described with reference to FIG.
As shown in FIG. 3, the pattern generation unit 471, the pattern memory 472, the pattern selection unit 473, the operation transfer unit 474, the access control unit 475, and the data register 476 are used to generate the drawing source via the data bus 451 of the common drawing bus 45. The data is transferred to the operation transfer unit 474, and the address on the frame memory 51 to which the data is written is transferred to the pattern selection unit 473, the access control unit 475 and the frame memory 51 via the address bus 452. .. In addition, each of the color plate creating units 47 to 5
4 frame memories 51, 52, 53 corresponding to 0,
54 is provided, and each of the frame memories 51 to 54 constitutes a storage means.

An address transmission signal 453 of the common drawing bus 45 is supplied to the pattern selection unit 473 and the access control unit 475. This address transmission signal 4
When 53 is Low, the value of the address bus 452 is invalid, and when it is High, the value of the address bus 452 is valid. Further, the data transmission signal 454 of the common drawing bus 45 is supplied to the access control unit 475. When the address transmission signal 454 is Low, the value of the data bus 451 is invalid, and when it is High, the value of the data bus 451 is valid.

The pattern generation section 471 is connected to the pattern instruction section 36 by the pattern instruction bus 37a.
The halftone pattern is expanded on the pattern memory 472 in accordance with the instruction from, and when the expansion is completed, an end signal is sent to the pattern instruction unit 36 via the pattern command bus 37a.

The pattern memory 472 is a memory for holding an area having the same size as the repetition period of the halftone pattern in the frame memory 51 shown in FIG. 5A, and is the area shown in FIG. 5B. .. For example, in the case of the pattern shown in FIG. 11A, two rows of the frame memory 51 have a repeating period, so the pattern memory 472 may hold the halftone patterns of two rows of the frame memory 51.

The pattern selecting section 473 is adapted to calculate a pattern address from the value of the address bus 452. For example, if the value of the address bus 452 is Am, the start address of the frame memory 51 is Af, the start address of the pattern memory 472 is As, and the repetition period of the halftone pattern is 1, the value of the pattern address Ap is Ap =
It is calculated by As + {(Am-Af) mod (1)}.
However, (a) mod (b) is a remainder obtained by dividing a by b, and is an integer of 0 or more and less than b.

The pattern selection unit 473 supplies the value of the pattern address to the pattern memory 472 via the pattern address bus 477 and also supplies the pattern address transmission signal 478 to the pattern memory 472. Pattern address transmission signal 47
When 8 is Low, the value of the pattern address bus 477 is invalid, and when it is High, the value of the pattern address bus 477 is valid.

Address data is supplied from the pattern memory 472 to the operation transfer section 474 via a pattern data bus 479. Also, the pattern memory 4
The pattern data confirmation signal 480 is supplied from 72 to the access control unit 475. When the pattern data confirmation signal 480 is Low, the pattern data bus 479
Value is invalid, and when it is High, pattern data bus 4
A value of 79 is valid.

The access control section 475 controls the timing of various access operations and transfers data. Data is supplied from the access control unit 475 to the data register 476 via a register data bus 481 and a write signal 482 is also supplied. When the write signal 482 is High, the contents of the data register 476 is the register data bus 48.
It can be rewritten to a value of 1. The data register 476 is adapted to hold the data read from the frame memory 51. The data in the data register 476 is supplied to the operation transfer unit 474 via the data bus 483.

The operation transfer section 474 constitutes an operation means and logically operates the input data bit by bit. As shown in FIG. 6, each bit is composed of one knot circuit 484 and 3 knot circuits 484 and 3.
A logical operation is performed by a circuit including NAND circuits 485, 486, 487.

For example, the value from the data bus 483 is f, the value from the data bus 451 is d, and the pattern data bus 47.
When the value from 9 is p, the output x is x = (p logical product d) logical sum {f logical product (−d)}. A schematic example of this calculation is shown in FIG. That is, assuming that the value f from the data bus 483 is (a) in FIG. 7, the value p from the pattern data bus 479 is (b) in FIG. 7 and the value d from the data bus 451 is (c) in FIG. Becomes as shown in FIG. 7 (d). The shaded area in the figure corresponds to bit "1", and the white area corresponds to bit "0". The output from the operation transfer unit 474 is supplied to the access control unit 475 via the data bus 488.

The access control unit 475 is connected to the frame memory 51 via a frame memory data bus 489, and transfers the write data to the frame memory 51 or receives the read data from the frame memory 51. There is. Further, a frame memory data confirmation signal 490 is supplied from the frame memory 51 to the access control unit 475, and the access control unit 4
75 to the frame memory 51, a frame memory read signal 491, a frame memory data transmission signal 4
92 and a frame memory address transmission signal 493 are supplied. The frame memory read signal 491 is R
In the format of / not W, reading is shown when it is High and writing is shown when it is Low. The frame memory data transmission signal 492 becomes High when the value of the frame memory data bus 489 is valid in the write operation, and becomes Low when the value is invalid. This also applies to the reading operation. When the frame memory address transmission signal 493 is High, the value of the address bus 452 is valid, and when it is Low, it is invalid.

Further, the access control section 475 outputs a data confirmation signal DC1 to the AND circuit 46. The data confirmation signal DC1 changes to High when the writing operation to the frame memory 51 is confirmed, and changes to Low when the access operation is completed.

Each of the frame memories 51 to 54 is adapted to store a bit map image for one page.
For example, the frame memory 51 stores the bitmap image of the yellow plate, the frame memory 52 stores the bitmap image of the magenta plate, the frame memory 53 stores the bitmap image of the cyan plate, and the frame memory 5
4 stores a black plate bitmap image.

An output control unit 55 controls the output device 56 to output the contents of each of the frame memories 51 to 54 according to an instruction from the main processing unit 31. The output device 56 is composed of a printing mechanism section of a color printer.

The main processing section 31, the color calculation section 34, the density calculation section 35, the pattern designating section 36, the pattern set flag 38, and the font active flag 40 constitute color control means, and the main processing section 31, the font processing. The unit 39, the multiplexor 41, and the demultiplexer 42 form an image forming unit. The pattern generating section 471, the pattern memory 472, and the pattern selecting section 473 of the color plate producing sections 47 to 50 constitute pattern generating means. Next, the operation of this embodiment will be described.

First, an initialization process is performed before communication with the host computer 32 is started. In this initialization processing, the font active flag 40 is reset and turned off.
The contents of the frame memories 51 to 54 are cleared. The main processing unit 31 instructs the color calculation unit 34 to set the drawing color to black. When the setting is completed, the color calculation unit 34 sets the pattern set flag 38 to turn it on.

When the above initialization processing is completed, communication with the host computer 32 is started. Host computer 3
When the command and data come from 2, the communication control unit 33 receives the command and data and transfers them to the main processing unit 31. The commands in the main processing unit 31 are classified into color designation commands, graphic drawing commands, character drawing commands, print execution commands, and other commands.

The main processing section 31 sequentially processes the received command and data. The color designation command is a command for designating a color for subsequent drawing. The graphic drawing command is a command for drawing a bitmap of a graphic on the frame memories 51 to 54. The character drawing command converts the bitmap of the character into the frame memory 51.
Up to 54. The print execution command is a command for causing the output device 56 to output the contents of the frame memories 51 to 54. This instruction is given from the main processing unit 31 to the output control unit 55, and the output device 56 executes print output. When it is a color designation command, the main processing unit 31 processes in the following procedure.

It is confirmed that the QP signal from the pattern set flag 38 is on. If it is off, wait. Then, the pattern set flag 38 is reset.
In this state, the color designation command is transmitted to the color calculation section 34.

When the color calculator 34 receives the color designation command,
In the color designation command, the colors are expressed in RGB or HSB format, so this is the CMYK format (percentage value of the four primary colors of cyan, magenta, yellow, and black).
Convert to. Then, the obtained CMYK values are sent to the density calculator 35. In this state, the density calculator 35 waits for a setting completion signal to be sent. Pattern set flag 3
Set 8.

The density calculator 35 receives the CMY from the color calculator 34.
When the color data in the K format is received, the color that cannot be output by the output device 56 is replaced with another color, and the color data is converted so as to match the characteristics of the output device 56. Then, the obtained value is sent to the pattern instruction unit 36. When a pattern completion signal is sent from the pattern instruction unit 36, it is transferred to the color calculation unit 34.

The pattern designating section 36 determines a halftone pattern of four colors from four density values of CMYK. That is, the position of the dot to be filled is determined for each color. However, the number of vertical dots and the number of horizontal dots are fixed to appropriate values. For example, if both the number of vertical dots and the number of horizontal dots are 16, then 256 levels of halftone can be expressed. When the halftone pattern is determined, the overlapping of four color plates (images on the frame memory) is also taken into consideration. For example, consider the case of 25% in which one dot is filled in all four color plates of 2 dots × 2 dots. If a pattern such as that shown in FIG. 8A is defined for CMYK, the four color fills overlap and the color quality deteriorates. Therefore, if the pattern is determined as shown in FIG. 8 (b), there will be no overlap of filling, and a good color will be obtained. That is, the positions of the dots to be filled in for each color are determined so that the dots of the four color plates do not overlap as much as possible.

When the position of the dot to be filled in for each color is determined, the pattern is sent to the pattern generator 471 of the color plate generators 47-50. Then, the process waits until the setting completion signals are sent from all the color plate creating units 47 to 50. When the setting end signals are received from all the color plate creating units 47 to 50, the setting end signal is sent to the density calculation unit 35.

Upon receiving the pattern instruction, the pattern generating section 471 of each of the color plate producing sections 47 to 50 develops the instructed pattern on the pattern memory 472. The expansion is performed on the entire necessary area of the pattern memory 472. Then, a setting end signal is sent to the pattern instruction unit 36. In the case of a character drawing command, the main processing unit 31 processes according to the following procedure.

QF from the font active flag 40
Make sure the signal is off. If it is on, wait until it turns off. Then, the font active flag 40 is set. An instruction for character drawing (character code, font, size, italic angle, rotation angle, drawing position) is given to the font processing unit 39. This instruction is not necessarily for each character, but may be for several characters collectively. Then, the process proceeds to the next command processing.

The font processing unit 39 uses the font cache (not shown) for the bitmap data of the designated character.
Prepare inside. It is confirmed that the QP signal from the pattern set flag 38 is on. If it is off, wait until it is on. The bit map data of the character is output to the character drawing bus 43 in 1-byte units. At this time, since the QF signal is in the ON state, the data is sent to the common drawing bus 45 and supplied to the four color plate creating units 47 to 50 at the same time. Output of each byte is H when all data confirmation signals AC
Complete after becoming igh. When the drawing output of all bytes of all characters is completed in this way, font active flag 4
0 is reset. In the case of a graphic drawing command, the main processing unit 31 processes in the following procedure.

Data to be drawn is prepared in byte units.
It is confirmed that the QP signal from the pattern set flag 38 is on. If it is off, wait until it is on. It is confirmed that the QF signal from the font active flag 40 is off. If it is on, wait until it turns off. Then, the data is output to the main drawing bus 44 byte by byte. Since the QF signal is in the off state, the data is sent to the common drawing bus 45 and supplied to the four color plate creating units 47 to 50 at the same time. The output of each byte is completed after the all data confirmation signal AC becomes High. Next, the operation of each of the color plate creating units 47 to 50 when drawing characters and figures will be described. The drawing data is simultaneously given to each of the color plate creating units 47 to 50 on the common drawing bus 45 byte by byte. As a result, the color plate creating units 47 to 50 operate in parallel. The timing of the drawing operation in each of the color plate creating units 47 to 50 is as shown in FIG.

That is, after the signal on the address bus 452 shown in FIG. 9 (b) becomes stable, the address transmission signal 453 becomes High at the timing of t1 as shown in FIG. 9 (d). After the signal on the data bus 451 shown in FIG. 9 (a) becomes stable, the data transmission signal 454 becomes High at the timing of t3 as shown in FIG. 9 (c).

After the address transmission signal 453 becomes High, the pattern selection unit 473 calculates the pattern address and sends it to the pattern address bus 477 as shown in (l) of FIG. And pattern address bus 4
After the 77 signal stabilizes, the pattern address transmission signal 4
78 is Hig at the timing of t6 as shown in (m) of FIG.
becomes h. After the pattern address transmission signal 478 becomes High, the pattern memory 472 sends the pattern data to the pattern data bus 479 as shown in (k) of FIG. After the signal on the pattern data bus 479 becomes stable, the pattern data confirmation signal 480 becomes High at the timing of t9 as shown in (n) of FIG.

Further, after the address transmission signal 453 becomes High, the frame memory data transmission signal 492 and the frame memory address transmission signal 493 are shown in FIG.
As shown in (h), it becomes High at the timing of t2. After the frame memory data transmission signal 492 and the frame memory address transmission signal 493 become High, the frame memories 51 to 54 store the data at the address specified in the frame memory data bus 489 as shown in (f) of FIG. Is sent. And the frame memory data bus 48
After the signal of 9 is stabilized, the frame memory data confirmation signal 490 becomes H at the timing of t4 as shown in (j) of FIG.
Become igh. Further, frame memory data confirmation signal 49
After 0 becomes High, the contents of the data register 476 are updated by the write signal 482 and the register data bus 481. Thus, as shown in FIG. 9 (o), the value of the register data 483 changes at the timing of t5.

The frame memory data confirmation signal 490 is H
After a certain time after becoming igh, the frame memory address transmission signal 493 and the frame memory data transmission signal 492 are set to L at the timing of t7 as shown in (h) and (g) of FIG.
become ow. After the frame memory address transmission signal 493 and the frame memory data transmission signal 492 are Low, the frame memory data confirmation signal 490 is shown in FIG.
As shown in, it becomes Low at the timing of t8.

Further, the data transmission signal 454 becomes High at the timing t3, and after a certain time or more, and after the content of the data register 476 is updated at the timing t5 or more, and the pattern data confirmation signal 480 is t9. The value of the operation output 488 is fixed when the time becomes High at a timing and after a certain time or more.

After the value of the operation output 488 is confirmed,
The frame memory read signal 491 becomes Low at the timing of t10 as shown in FIG. 9 (i), and the frame memory address transmission signal 493 becomes High at the timing of t10 as shown in FIG. 9 (h). .. After the frame memory address transmission signal 493 becomes High, the frame memories 51 to 54 change the frame memory data confirmation signal 49.
0 at the timing of t12 as shown in (j) of FIG.
To When the frame memory data confirmation signal 490 becomes high, the data confirmation signal DC1 becomes high at the timing of t13 as shown in (p) of FIG. After a certain time after the frame memory data confirmation signal 490 becomes High, the frame memory address transmission signal 493 and the frame memory data transmission signal 492 become Low at the timing of t14 as shown in (h) and (g) of FIG. ..

Thus, all data confirmation signals DC1 ...
When DC4 becomes High, all data confirmation signals AC are shown in FIG.
As shown in (e) of the above, it becomes High at the timing of t17.
Then, after a certain time after all the data confirmation signals AC become High, the address transmission signal 453 and the data transmission signal 454 are transmitted.
Becomes Low at the timing of t18 as shown in (d) and (c) of FIG. After the address transmission signal 453 and the data transmission signal 454 become Low, the signals of the address bus 452 and the data bus 451 become indefinite values.

After the address transmission signal 453 and the data transmission signal 454 become Low, the pattern address transmission signal 478 becomes Low at the timing of t19 as shown in (m) of FIG. Further, after a certain period of time when the address transmission signal 453 and the data transmission signal 454 become Low, the data confirmation signal DC1 becomes Low at the timing of t20 as shown in (p) of FIG. Pattern address transmission signal 478 is Low
After a certain period of time, the pattern data confirmation signal 480 becomes Low at the timing of t22 as shown in (n) of FIG. Further, after the pattern address transmission signal 478 becomes Low, the signals of the pattern address bus 477 and the pattern data bus 479 become indefinite values. Data confirmation signal DC
When any one of 1 to DC4 becomes Low, the all data confirmation signal AC becomes Low at the timing of t21 as shown in (e) of FIG.

The operation performed at the above timing will be described. The pattern selection unit 473 is the address bus 45.
The address of the pattern is calculated from the value of 2. The pattern data is read from the pattern memory 472 by the address value and sent to the operation transfer unit 474. Further, data is read from the frame memory according to the value of the address bus 452, and is sent to the operation transfer unit 474 via the data register 476. Further, the data bus 451 is connected to the arithmetic transfer unit 474.

After the three inputs to the operation transfer unit 474 are stabilized, the content of the operation output 488 is changed to the address bus 45.
The value of 2 is used to write to the frame memory. Then, the data confirmation signal DC1 is set to High to notify the end of processing.

As a result of the above operation, a logical operation is performed between the data from the data bus 451, the original data of the frame memory, and the data from the pattern memory 472, and the result is stored in the frame memory. Written.
For each bit, if the data from the data bus 451 is "0", the content of the frame memory does not change, and if the data from the data bus 451 is "1", the data from the pattern memory 472 is written to the frame memory. ..

When the frame memories 51 to 54 are viewed from the main processing section 31 and the font processing section 39, it seems that there is only one side of the frame memory for the color plate of the designated color. For this reason, the drawing processing of the main processing unit 31 and the font processing unit 39 only needs to transfer data once, so that the configuration is simple and high-speed processing can be realized. In this way, it is possible to perform the formation processing of a color image that is expressed in halftone at high speed.

Although each data is handled in the unit of 1 byte in the above embodiment, it is not limited to this, and it may be handled in the unit of 2 bytes or the unit of 3 bytes or more. Although the clock pulse is not mentioned in this embodiment, it may be constituted by a synchronous circuit.

The color calculation section 34, the density calculation section 35, and the pattern designating section 36 do not need to be constructed by separate circuits, and the CP
It can also be configured by a ROM storing U and a dedicated program. Further, the functions of the color calculation section 34, the density calculation section 35, and the pattern designating section 36 may be realized by installing a dedicated program in the main processing section.

Further, in the above-described embodiment, four color plate forming parts and four frame memories are used, and yellow, magenta, cyan,
Although the four primary colors of black are supported, the number of primary colors used is not limited to this, and any number of sets may be used depending on the number of primary colors used.

In the above embodiment, the present invention is applied to the image formation of a color page printer, but the present invention is not limited to this and can be applied to other printers and display devices.

[0065]

As described in detail above, according to the present invention, it is possible to provide an image forming apparatus capable of relatively easily performing halftone expression and high-speed processing in forming a multicolor image.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a font processing unit of the embodiment.

FIG. 4 is a block diagram showing a configuration of a color plate creating unit according to the embodiment.

FIG. 5 is a view for explaining the relationship between the frame memory and the pattern memory of the same embodiment.

FIG. 6 is a diagram showing a configuration of an arithmetic transfer unit of the same embodiment.

FIG. 7 is a diagram for explaining the operation of the arithmetic transfer unit of the embodiment.

FIG. 8 is a diagram for explaining processing for avoiding pattern overlap in the embodiment.

FIG. 9 is a diagram showing the timing of drawing processing in the color plate creating unit of the embodiment.

FIG. 10 is a block diagram showing the overall configuration of a printing apparatus using an electrophotographic method.

FIG. 11 is a diagram showing an example of a halftone pattern.

[Explanation of symbols]

11 to 13 ... Frame memory (storage means), 14 ... Image forming means, 15-17 ... Pattern generating means, 18 ... Color control means, 19-21 ... Computing means, 31 ... Main processing section, 34 ...
Color computing unit, 35 ... Density computing unit, 36 ... Pattern designating unit,
39 ... Font processing unit, 47-50 ... Color plate creating unit, 51
~ 54 ... Frame memory.

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Claims (1)

[Claims] 1. A plurality of storage means for storing an output image corresponding to each primary color used for printing or displaying, and an image forming for outputting the drawing data based on the drawing color designation to create the output image. And means provided for each of the storage means,
A plurality of pattern generating means for generating pseudo halftones, and color separation based on designated colors to set patterns for each primary color, and the pattern generating means prepares pseudo halftones for each pattern generating means. Color control means for performing
The drawing data from the image creating unit, the data from the corresponding pattern generating unit, and the data from the corresponding storing unit are provided in correspondence with each of the storage units, and the calculation is performed. An image forming apparatus comprising: a plurality of arithmetic units that operate in parallel and are stored in a storage unit.