JPH0513721A - Semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a structure that prevents data destruction of a memory cell storage node due to diffusion of electrons generated in a protection diode of an input protection unit while suppressing an increase in occupied area. A semiconductor memory device that uses a P-type semiconductor substrate and operates by an internal power supply voltage lower than the external power supply voltage by lowering the external power supply voltage inside the chip and supplying it to an internal circuit. There are N-type well regions and P-type well regions alternately formed on the substrate so that the transistors operating at each voltage are separated from each other.
The memory cell transistor formed in the P-type well region and the protective P-type well region connected to the signal input end of the P-type well region are surrounded by the protective P-type well region. Is further provided with an input protection portion having an N-type well region for protection having a deeper junction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to a well structure in a substrate of a semiconductor chip, in which a half-micron (0.5 μm to 0.6 μm gate length) fine transistor is used and an external voltage is applied to the inside of the chip. The present invention relates to a semiconductor memory device that needs to be stepped down and supplied to an internal circuit.

[0002]

2. Description of the Related Art Conventionally, a half-micron fine CMOS
In a structured LSI, if a 5V power supply of the TTL standard is directly applied to the elements inside the chip, performance deterioration due to hot carriers of the MOS transistor or TDD of the gate oxide film will occur.
Destruction due to B (Time-Dependent Dielectric Breakdown) occurs and the reliability of the element cannot be maintained. Therefore, in the inside of the LSI memory chip, the voltage obtained by stepping down the external 5V power supply voltage to 3 to 4V is 0.5μ in the chip.
It is applied to an m-order MOS transistor. By adopting this method, high integration of elements is realized.

FIG. 6 is a block diagram of an LSI memory chip having the above structure. The inside of the memory chip 71 depends on the standard of the input / output interface and is external power source, for example, 5V
Signal input circuit in which (hereinafter referred to as Vext) is directly used
The voltage is internally stepped down by the input / output circuit part of the signal output circuit 72 and the signal output circuit 73 and the power supply voltage down circuit 74.
(referred to as t) is applied to the circuit portion of the internal circuit 75.

The input / output circuit portion has an element size of 0.5.
It is made larger than μm to ensure the reliability of the device in the operation of Vext specifications. The internal circuit 15 to which Vint is applied is composed of a device having a device size of 0.5 μm.

As described above, circuit parts having different applied voltages are mixed in the LSI chip. For this reason, it is necessary to separate the biases of the N-well regions of the P-channel type MOS transistor operating at Vext and the P-channel type MOS transistor operating at Vint for the semiconductor chip. Therefore, use a P-type substrate silicon wafer. There are many.

By the way, DRAM (dynamic RA
In the memory such as M) or SRAM, it is necessary to suppress the leak characteristic at the element or the semiconductor junction portion to a level which is almost completely within the chip because of the storage retention method. This is because the occurrence of a leak defect in these elements or junction causes a data retention defect in the memory cell. If there is a defect in even one cell beyond the number that can be repaired by the redundant memory cell, the chip becomes a defective product.

Although all the causes of the leak failure in such elements or junctions have not been clarified, in many cases, crystal defects and the like existing in the semiconductor substrate are highly likely to cause. The cause of this crystal defect is often due to the processing method in the manufacturing process, but it is also influenced by the difference in the type of the silicon substrate. Ie N
There is data that crystal defects are less likely to occur in the P-type substrate than in the P-type substrate, and there is a tendency that the P-type substrate is used more than the N-type substrate.

7 and 8 show a CMOS type SRA using a high resistance load type memory cell formed by using a P type substrate.
It is sectional drawing which shows the structure of M (static RAM).
As described above, the P-type substrate has both a region to which the power supply voltage Vext is supplied and a region to which Vint, which is the power supply voltage reduced inside the chip, is supplied. The supply regions for Vext and Vint are separated by the P-well region, and CM
A memory LSI having an OS structure is configured.

In FIG. 7, an N well region 82, a P well region 83, an N well region 84 and a P well region 85 are formed on a P type substrate 81. A MOS transistor is formed in each of these regions. 87 indicates the gate on the insulating film in each MOS transistor. N well region 82
Is applied to Vext and the P-well region 83 is applied with the ground voltage GND to form the external power supply drive circuit EXT. N well area
Vint is applied to 84, and the ground voltage GND is applied to the P well region 85. Of these, N ⁺ of the storage node of the memory cell transistor 86 Vint is applied to the region 88 through the high resistance load 89. The N well region 84 and the P well region 85 form an internal power supply drive circuit INT. A phenomenon will be described below when the input signal is temporarily lower than the ground level due to undershoot or the like and is applied to the electrode pad 90 in the above configuration.

In order to protect the internal circuit from excessive voltage input in the input signal, the input signal is first input to the input protection unit 91 and then input to the input buffer. The input protection unit 91 is, for example, a P-type well region 85 biased to the ground voltage GND, and an N ⁺ in the P-type well region 85. It has a diode structure in which an input signal is taken into the mold region 92.

In the structure as described above, when the input signal applied to the electrode pad 90 temporarily becomes lower than the ground level due to undershoot or the like, the input protection diode portion is forward biased, so that the P well is formed. The electrons, which are the minority carriers, are injected into the region 85.

In FIG. 7, the memory cell 86 and the input protection portion 91 are included in a continuous P well region 85. P-well area 85
The electrons injected into the P-well region 85 diffuse into the N ^{+ +} The mold area 88 can be reached (arrow 93). When the depletion region near the N + type region 88 is reached, if a high voltage is held there, the stored charges are discharged by the diffused electrons, and the stored data disappears. On the other hand, FIG. 8 shows a case where no memory cell is included in the continuous P-well region including the input protection part.

A P well region 102, N
Well region 103, P well region 104, N well region 105
, P-well regions 106 are formed. A MOS transistor is formed in each of these regions. Vint is applied to the N well region 103, and the ground voltage GND is applied to the P well region 104. Vext is applied to the N well region 105, and the ground voltage GND is applied to the P well region 106. P-well area 10
An input protection unit 107 is formed at 6. Also, GND
Memory cell 108 in the P-well region 102 biased to
Are formed. N ⁺ of the storage node of the memory cell 108
Vint is applied to the region 109 via the high resistance load 110. The P well regions 102 and 104 and the N well region 103 form an internal power supply drive circuit INT, and the N well region 105 and the P well region 106 form an external power supply drive circuit EXT.

In the structure shown in FIG. 8, the P well region 102 is used.
And 106 are not consecutive. However, the electrons injected from the electrode pad 109 into the diode portion of the input protection unit 107 diffuse from the P well region 106 including the input protection unit 107 to the P well region 102 including the P type substrate 101 and the memory cell 108. As a result, the injected electrons are stored in the memory cell N ^+. The data reaches the region 109 and the data held at the high voltage is erased.

In most large-capacity SRAMs, the high resistance loads 89 and 110 (shown in FIGS. 7 and 8) that are generally used as load elements of storage flip-flops are very high, of the order of a few teraohms. Therefore, when the stored data is destroyed by the diffused electrons as described above, recovery of the voltage from the load side cannot be expected in terms of time constant. The same applies to DRAMs having a similar memory retention mechanism.

[0016]

As described above, in the conventional structure in which the P-type substrate is used and the transistors formed in the external power source drive region and the internal power source drive region are separated from each other,
There is a drawback that the diffusion of electrons generated in the protection diode of the input protection unit destroys the stored data in the memory cell.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor memory device having a structure capable of preventing the destruction of stored data in a memory cell storage node. .

[0018]

A semiconductor memory device of the present invention uses a P-type semiconductor substrate and lowers an external power supply voltage inside the chip to supply the internal circuit with an internal power supply voltage lower than the external power supply voltage. And a P-type well region alternately formed on the substrate so that the transistors operating with the external power supply voltage and the internal power supply voltage are separated from each other. The memory cell transistor formed in the well region and the protection P-type well region connected to the signal input end of the P-type well region are surrounded by the protection P-type well region deeper than the protection P-type well region. It is characterized by including an input protection section having an N-type well region for protection having a junction.

[0019]

In the present invention, the deep N well region is introduced into the P type substrate, but generally, only the input protection portion having a relatively large occupied area is formed in the deep N well region. This allows
The increase in the area of the protection circuit is suppressed. In the input protection part surrounded by the N well region, when the diode in the input protection part is forward biased, the generated electrons cannot reach the memory cell region and are absorbed by the external terminal through the N well region. .

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

First, the structure which is the premise of the present invention will be described with reference to FIGS. FIG. 4 is a cross-sectional view of a configuration for preventing stored data destruction due to electrons injected by the forward bias. As a measure for preventing the destruction of the stored data due to the injected electrons, an N well region having a deeper junction than that in FIG. 7 is further introduced.

In FIG. 4, an N well region 22, a P well region 23, an N well region 24 and a P well region are formed on a P type substrate 21.
25, an N well region 26, and a P well region 27 are formed. A MOS transistor is formed in each of these regions 22, 23, 24 and 25. Vext is applied to N well region 22 and ground voltage GND is applied to P well region 23 to form external power supply drive circuit EXT. In the N well region 24, Vint is P
The ground voltage GND is applied to the well regions 25 and 17. Of these, N ⁺ of the storage node of the memory cell 28 Vint is applied to the region 29 through the high resistance load 30. N well region 26
Vint is applied to the N well regions 24 and 26 and are connected by a deep N well region 31. As a result, the P well region 25 including the memory cell 28 becomes the N well regions 24, 26, 31.
Surrounded by. These areas 24, 25 and 26 form an internal power supply drive circuit INT.

By configuring the internal power supply drive circuit INT, which is driven by the internal power supply voltage Vint, such as a memory cell, in the deep N well region 31, even if electrons are injected and the P type region is diffused, it reaches the memory cell. It becomes a structure that cannot be done. For example, the electrons diffused by the signal voltage applied to the electrode pad 32 are P well region 25 including the memory cell 28.
Vint is absorbed by the terminal to which Vint is applied before reaching (arrow 33). Therefore, data destruction can be prevented.

However, according to the above configuration, the deep N
Since the well region 31 is biased by the internal power supply voltage Vint, the load on the power supply voltage dropping circuit 74 shown in FIG. 6 for generating Vint becomes heavy.

That is, when a large peak current is generated at the terminal to which Vint is applied, the internal power supply voltage is temporarily increased until the deep N well region 31 having a large junction capacitance with the substrate 21 is charged. It may fall and the circuit operation may become unstable.

As a measure for avoiding such a problem, as shown in FIG. 5, there is a method in which only memory cells are formed in a deep N well region biased to Vext. The configuration of FIG. 5 will be described below.

An N well region 42 to which Vext is applied is formed on the P-type substrate 41, and the GND is provided so as to sandwich this region 42.
P well regions 43 and 44 to which is applied are formed. P
A memory cell portion 45 is formed adjacent to the well region 44. The memory cell portion 45 is a P formed with a cell transistor.
The well region 46 is formed so as to sandwich the N well regions 47 and 48. These P well region 46 and N well regions 47, 48
A deep N-well region 49 is formed underneath. Further, a memory cell portion 53 is formed so as to separate the PMOS region in the memory cell array of the N well region 52 sandwiched between the P well regions 50 and 51. In the memory cell portion 53, the P well region 54 in which the cell transistor is formed is replaced with the N well regions 55 and 56.
Are formed so as to sandwich. These P well regions 54,
A deep N well region 57 is formed below the N well regions 55 and 56. A P well region 59 to which an input signal is applied from an electrode pad 58 is formed in contact with the N well region 56.

According to this structure, for example, the electrons diffused by the signal voltage applied to the electrode pad 58 reach the N well region 56 around the memory cell portion 53, and Vext
Is absorbed by the terminal 60 to which is applied (arrow 61). Therefore,
Data destruction can be prevented.

According to the above structure, the N channel type MOS transistor regions of the memory cell portions 45 and 53 are formed in the deep N well regions 49 and 57, and the deep N well regions 49 and 57 are formed.
Since 57 is biased to Vext, the problem of driving force in the power supply voltage dropping circuit 74 in FIG. 6 is eliminated. However, although it is preferable that the memory cell array is composed of only N-channel type MOS transistors, there is a problem in the case of including P-channel type MOS transistors as in this structure.

N including a P-channel type MOS transistor
Well region 52 is normally biased at Vint. Therefore, it must be removed from the deep N-well region. On the pattern layout, sandwich the border of the deep N-well region,
Since it is necessary to arrange the elements with a certain distance, an extra area is required, which causes an increase in chip area.

In fact, in recent large-capacity SRAMs, the memory cell array is often divided in the word line direction. In this case, the word line has a double structure of a main word line and a divided section word line, and it becomes necessary to dispose a P-channel type MOS transistor for driving this section word line in the memory cell array.
Therefore, the problem of increasing the chip area cannot be ignored.

The present invention solves the above problems.
Prevents stored data destruction at the memory cell storage node due to diffusion of electrons generated in the protection diode of the input protection unit,
In addition, a structure that does not impose a heavy load on a drive circuit inside the chip that generates the internal power supply voltage Vint and does not sacrifice in area is realized.

FIG. 1 is a sectional view showing the structure of an embodiment of the present invention. Similar to FIGS. 4 and 5, a deep N well region is introduced into the P-type substrate, but it is characterized in that only the input protection portion is formed in this deep N well region.

N well region 2, P well region 3, N well region 4, P well region 5, N well region 6, P well region 7, N well region 8, P well region on P type substrate 1.
9 is formed. Of these, the regions 6, 7, 8 constitute the input protection section 10, and the deep N-well region 11 is formed in the lower layer of the regions 6, 7, 8.

A P-channel or N-channel MOS transistor is formed in each of these regions 2, 3, 4, and 5. N well region 2, N well region of input protection unit 10
Vext is applied to 6 and 8, ground voltage GND is applied to the P well regions 3 and 5 and the P well region 7 of the input protection section 10, and Vint is applied to the N well region 4. Also,
N ⁺ of the memory cell 12 in the P well region 5 Vint is applied to the region 13 via the high resistance load 14.

According to the configuration of the above embodiment, the input protection unit 10
Due to the N well regions 6 and 8 and the deep N well region 11 in, the P well regions 5 and 7 are not continuous. That is,
When an input signal is applied to the electrode pad 15 and the diode of the input protection unit 10 is forward biased, the generated electrons cannot reach the area of the memory cell 12. Therefore,
The data stored in the memory cell is not destroyed by the diffusion of injected electrons. The deep N-well region 11 has an external power source Vext.
There is no problem with the driving force of the power supply voltage drop circuit because it is directly biased by In addition, since the area other than the input protection section 10 can be laid out with the same structure as the conventional one, the increase in area and other problems do not occur.

A new deep N well region 11 is provided in the input protection section.
However, the input protection unit 10 has not been miniaturized as in the internal circuit such as the memory cell array, and a very large size is used to alleviate an electrical overload from the outside. Therefore, the increase in area is not a problem.

A problem with the structure of the above embodiment is that the structure of the input protection section 10 is N ⁺ to which an input signal is applied from the P-type substrate 1 side. The region 16 up to the PNPN structure has a concern about resistance to latch-up. However, the deep N well region 11 is approximately + 5V due to Vext.
Since it is biased at, the parasitic NPN bipolar transistor is basically saturated, that is, the collector,
Bias between bases is unlikely to be forward.

However, as another biasing method, as shown in FIG. 2, the deep N well region 11 is biased to the ground level, and the emitter, base and collector of the PNP bipolar transistor are all biased to the ground level. A method of making it difficult to turn on can be considered.

Further, in order to make it harder to turn on the parasitic PNP transistor, that is, in order to prevent the junction between the P well region 7 and the deep N well region 11 from being forward biased, a deep N well corresponding to the collector of the parasitic NPN transistor is formed. Embedded N ^{+ in} region 11 A configuration in which the region 17 is provided is also conceivable.

[0041]

As described above, according to the present invention,
By forming only the input protection portion in the deep N-well region, a drive circuit inside the chip that generates the internal power supply voltage is not overloaded and the area is not sacrificed. It is possible to provide a semiconductor memory device capable of preventing the stored data from being destroyed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a configuration according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a configuration according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a configuration of a semiconductor memory device which is a premise of the present invention.

FIG. 5 shows a second semiconductor memory device according to the present invention.
FIG.

FIG. 6 is a block diagram of a semiconductor memory device according to the present invention.

FIG. 7 is a cross-sectional view showing the configuration of a conventional semiconductor memory device.

FIG. 8 is a sectional view showing a configuration of a conventional semiconductor memory device.

[Explanation of symbols]

1 ... P-type substrate, 2, 4, 6, 8 ... N-well region, 3, 5
, 7, 9 ... P-well region, 10 ... Input protection part, 11 ... Deep N-well region, 12 ... Memory cell, 13, 16, 17 ... N ⁺ Area, 14 ... High resistance load, 15 ... Electrode pad.

Claims (4)

[Claims] 1. A semiconductor memory device that uses a P-type semiconductor substrate and operates at an internal power supply voltage lower than the external power supply voltage by lowering the external power supply voltage inside the chip and supplying it to an internal circuit. , N-type well regions and P-type well regions alternately formed on the substrate so that the transistors operating at the respective internal power supply voltages are separated from each other, and memory cell transistors formed in the P-type well regions, A protective N-type well region having a junction deeper than the protective P-type well region is provided so as to surround the protective P-type well region connected to the signal input end of the P-type well region. And a semiconductor memory device comprising: 2. The semiconductor memory device according to claim 1, wherein the protective N-type well region is biased by the external power supply voltage. 3. A buried N ⁺ in which the protective N-type well region is biased by the external power supply voltage and a high-concentration N-type impurity is introduced into the protective N-type well region. The semiconductor memory device according to claim 1, wherein a region is provided. 4. A buried N ⁺ structure in which the protective N-type well region is biased by a ground voltage and a high-concentration N-type impurity is introduced into the protective N-type well region. The semiconductor memory device according to claim 1, wherein a region is provided.