JPH05137110A - Recording/reproducing device - Google Patents

Abstract

PURPOSE:To easily obtain a satisfactory reproducing image even at the time of high speed reproduction by executing an in-frame encoding processing of a prescribed number of image areas for forming one picture in a prescribed period and recording the number of divisions, and the number of tracks per one frame in a prescribed recording medium through a code replacing circuit, etc. CONSTITUTION:For instance, one picture is formed by (n)=2640 pieces of image areas, the image areas are subjected to in-frame encoding processing by a quantizing circuit 15, a variable length encoding circuit 16, etc., in (f)=11-frame period, and one piece of track of a magnetic tape 26 is divided into (d)=10 pieces, etc., and recorded in (c)=one piece of track per one frame. In this case, based on a video code subjected to band compression from the circuit 16 and a code position signal of a refresh block from a refresh block control circuit 40, a code replacing circuit 39 rearranges the refresh block and a non-refresh block as necessary, recording medium areas of the same number as (d)X(c)X(f) pieces of image areas for executing an in-frame code processing correspond thereto, and a satisfactory high speed reproducing image is obtained easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention converts a video signal or the like into a digital signal, performs band compression by combining intra-frame coding processing and inter-frame coding processing, and records on tape, for example, by a helical scan method. The present invention relates to a recording / reproducing apparatus for reproducing the same, and more particularly to a recording / reproducing apparatus capable of easily obtaining a good reproduced image during high-speed reproduction.

[0002]

2. Description of the Related Art As is well known, when digitally transmitting a video signal, band compression is performed by combining a transmission method using a variable length coding method or a combination of intraframe coding processing and interframe coding processing. Transmission methods are being studied. Among them, a technique for performing band compression by combining intraframe coding processing and interframe coding processing and transmitting the data is disclosed in, for example, the document IEEE Trans.on Broadcastin.
Woo Paik: “Digi described in g Vol.36 NO.4 DEC 1990
It is a band compression technology as shown in "tal compatible HD-TV Broadcast system", and its characteristic part is explained below.

In FIG. 8, the video signal input to the input terminal 11 is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, respectively. The subtraction circuit 12 performs a subtraction process, which will be described later, and the output thereof is input to a DCT (discrete cosine transform) circuit 14. The DCT circuit 14 takes in 8 pixels in the horizontal direction and 8 pixels in the vertical direction as a unit block (8 × 8 pixels = 64 pixels), and outputs a coefficient obtained by converting the pixel array from the time axis domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15 has 10 or 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantizing circuit 15 is provided with a quantizing table so that the amount of generated information and the amount of transmitted information are within a certain range.

The coefficient data output from the quantizing circuit 15 is zigzag-scanned from the low frequency band to the high frequency band for each unit block, and is extracted.
It is inputted to 6 and variable-length coded with the number (run length) following the zero coefficient and the non-zero coefficient as one set. The encoder is a variable length encoder having a different code length depending on the frequency of occurrence of Huffman code or the like. The variable-length coded data is input to a FIFO (first-in-first-out) circuit 17 and read out at a prescribed speed, and then, via an output terminal 18, a multiplexer at the next stage (not shown). [Control signals, voice data, sync data (SYN
C), multiplex NMP etc. described later] is supplied to the transmission path.

The output of the quantization circuit 15 is input to the inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the adder circuit 21. The output of the frame delay circuit 22 is supplied to the motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 10
Is the input signal from the input terminal 11 and the frame delay circuit 2
The output signal of 2 is compared to detect the overall motion of the image, and the phase position of the signal output from the motion compensation circuit 23 is controlled. In the case of a still image, the original image and the image one frame before are compensated so as to match. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. The basic operation of this system includes intraframe coding processing and interframe coding processing. The intra-frame coding process is performed as follows. When this process is performed, both switches 24 and 25 are off. The video signal of the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. The quantized signal is subjected to variable length coding processing and then output to the transmission line via the FIFO circuit 17. The quantized signal is supplied to the inverse quantization circuit 19
The signal is returned to the original signal by the inverse DCT circuit 20, and delayed by the frame delay circuit 22. Therefore, in the intra-frame coding process, it is equivalent to that the information of the input video signal is variable length coded as it is. This intra-frame processing is performed in a proper cycle in units of predetermined blocks and scene changes of the input video signal.

Next, the interframe coding process will be described. When the inter-frame coding process is executed, both the switches 24 and 25 are turned on. Therefore, a signal corresponding to the difference between the input video signal and the video signal one frame before is obtained from the subtraction circuit 12. This difference signal is
It is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. Further, since the differential signal and the video signal are added by the adding circuit 21 and input to the frame delay circuit 22,
A predicted video signal that predicts the input video signal from which the differential signal was created is created and input.

FIG. 9 shows a line signal in a state in which the video signal of the high-definition television signal has been subjected to the intraframe processing and the interframe processing as described above and sent out on the transmission path. This signal is a signal of a transmission line, and is shown in a state in which a control signal, a voice signal, a synchronization signal (SYNC), a system control signal, NMP and the like are multiplexed. FIG. 9A shows the signals of the first line, and FIG. 9B shows the signals of the second and subsequent lines. If this video signal has undergone intra-frame processing, a normal video signal can be obtained by inverse conversion. However, in the case of a video signal that has been subjected to interframe coding processing, the difference signal is only reproduced even if this signal is inversely converted. Therefore, a normal video signal can be reproduced by adding the video signal (or predicted video signal) reproduced one frame before to this difference signal.

According to the above system, all the information in the signal processed in the frame is variable-length coded, and the signal processed in the inter-frame after the next frame transmits the difference information. It means that compression is realized.

Next, the definition of the set of pixels processed by the band compression system will be described. That is, a block: an area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction. Super block: An area consisting of 4 blocks in the horizontal direction and 2 blocks in the vertical direction of the luminance signal. This area includes one block as the color signals U and V. The image motion vector obtained from the motion evaluation circuit 13 is included in units of super blocks. Macroblock: 11 superblocks in the horizontal direction. Also, when the code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and these are transmitted as a set to transmit the code of the block. The end of block signal is added at the end. Then, the motion vector of the motion correction performed in units of super blocks is added and transmitted in units of macro blocks.

With respect to the transmission signal shown in FIG. 9, further related items will be further described below. The first line synchronization (SYNC) signal indicates a frame synchronization signal in the decoder, and all the timing signals of the decoder are generated using one synchronization signal per frame. The NMP signal on the first line indicates the number of video data from the end of this signal to the beginning of the macroblock of the next frame. This is because the code is configured by adaptively switching between the intra-frame coding process and the inter-frame coding process, so that the code amount of one frame differs for each frame, and the code position differs. This is because of Therefore, the code position corresponding to one frame is set to N
This is indicated by the MP signal.

Further, as a countermeasure when the user changes the channel, periodical intraframe processing is performed. That is, in this band compression system, as described above, 11 super blocks in the horizontal direction are referred to as macro blocks, and 44 super blocks exist in the horizontal direction of one screen. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. Then, in this band compression system, FIGS.
Also, as shown in FIGS. 11A to 11C, refresh is performed in units of four macroblocks in each vertical column of the superblock, and all the superblocks are refreshed in a cycle of 11 frames. That is, as shown in FIG. 11 (d), the refreshed super block is accumulated for 11 frames, so that the intra-frame processing is performed in all areas.
Therefore, for example, during normal reproduction of a VTR (video tape recorder) or the like, the above-described intraframe processing is performed at an 11-frame cycle, so that the reproduced image can be viewed without any problem.

Head data is inserted at the beginning of the macroblock. This head data contains
The motion vector, field / frame determination, PCM / DPCM determination, quantization level, etc. of each super block are inserted together.

By the way, the band compression system described above is
It is used as an encoder for band compression of television signals, and the decoder is used on the receiving side. Now, consider recording the above transmission signal in a VTR.
A general VTR is a system in which a video signal of one field is converted into a fixed length code, a certain amount of information is generated, and recorded on X (X is a positive integer) tracks.

On the other hand, when the transmission signal obtained by the band compression system is used as it is for recording / reproducing on the VTR, the variable length code is used as it is for the code subjected to the intra-frame processing and the inter-frame processing. Since the position where the code processed in the frame is recorded is not fixed, a block that is not refreshed may occur during high speed reproduction.

Specifically, FIG. 12 shows a track pattern when the variable length coded signal as described above is helically recorded on the magnetic tape 26. In the track patterns T1 to T11, the thick line portions indicate the switching positions of the frames F1 to F11. The switching positions of the frames F1 to F11 are not aligned because the record data is created by the variable length code. When the magnetic tape 26 is normally reproduced by the VTR, all the track patterns T1 to T1 are recorded.
Since 1 is sequentially scanned by the magnetic head, a normal video signal can be reproduced without any problem by passing the reproduction output through the decoder. That is, during normal reproduction, it is possible to reproduce all of the intra-frame processed code and the inter-frame processed code recorded on the magnetic tape 26, so that an image can be constructed using all the codes.

However, in the VTR, there are cases in which only a limited number of tracks are reproduced, as in the double speed reproduction mode in special reproduction. At this time, the magnetic head jumps the track and picks up the recording signal. In this case, there is no problem if the tracks of the signal subjected to the intra-frame coding process are reproduced one after another, but if the tracks subjected to the inter-frame coding process are reproduced, only the image by the differential signal is obtained.

FIG. 13 shows trace loci X1 to X11 of the magnetic head when the double speed reproduction is performed. In FIG. 13, since the signals subjected to the intraframe coding processing are dispersed and recorded in the frames F1 to F24, the position of the intraframe processing portion reproduced in the screen is indefinite. 14A to 14H and 15A to 15C show signals processed in the frame that can be reproduced at the double speed reproduction. Then, when these 11 frames are accumulated, as shown in FIG. 15 (d), there is no code for which the intra-frame processing is performed periodically, that is, there is a portion in which a refreshed super block does not exist, and reproduction is performed. There will be some parts that cannot compose the image.

[0019]

As described above, the helical scan type recording / reproducing apparatus having the conventional band compression system has a problem that high-speed reproduction such as double-speed reproduction becomes difficult.

Therefore, the present invention has been made in consideration of the above circumstances, and an object thereof is to provide an extremely good recording / reproducing apparatus capable of easily obtaining a good reproduced image at high speed reproduction.

[0021]

A recording / reproducing apparatus according to the present invention comprises an intra-frame processed signal obtained by subjecting a video signal to intra-frame encoding processing using information in the frame,
A signal processing method that creates an inter-frame processed signal that has been subjected to inter-frame coding processing using difference information between frames and that performs inter-frame coding processing after intra-frame coding processing It is intended to include a band compression unit that adaptively repeats according to the evaluation, and record and reproduce the output of the band compression unit on a recording medium.

In the image area of one screen, a number (a
Is a positive integer), a number of image areas covering one image area are formed, and an intra-frame code is applied to a number of image areas at a period of f frames (f is an integer of f ≧ 2). Intra-frame coding processing means for performing coding processing and one track on the recording medium are divided into approximately equal parts (d is a positive integer), and c tracks (c is a positive integer) per frame are used. , A unit for forming d × c × f recording medium areas per f frame, a number of a image areas to be subjected to intra-frame coding processing, and d × c × f recording medium areas are associated with each other. The recording means for recording is provided.

[0023]

According to the above construction, since the signal subjected to the intra-frame coding processing can be accurately obtained at the time of high speed reproduction, a good reproduced image can be obtained.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. In this embodiment, the intraframe coding processing is performed on 2640 areas per screen in 11 frames, so the number of areas in one screen is a = 2640, and the intraframe coding processing period f is 11 frames. Further, here, an example in which the a = 2640 areas do not overlap each other is used, but they may overlap. further,
In order to describe the case where one track is divided into ten and the average video code for one frame is recorded in one track, the number of divisions of one track d = 10, and the number of tracks for recording the average video code for one frame c = 1. Therefore, the number of recording medium areas is d × c × f = 10 × 1 × 11 = 110. The correspondence between the screen area and the recording medium area will be described in the case of equal distribution. It should be noted that in the present invention, it is not always necessary to equally distribute. Therefore, the number of screen areas in one recording medium area e = a / d × c × f = 2640
/ 10 × 1 × 11 = 24, and d = e = 24
The case of associating with × c × f = 110 regions will be described.

In FIG. 1, the same parts as those in FIG. 8 are designated by the same reference numerals, and different parts from the conventional system will be mainly described. Further, FIG. 2 shows the operation timing of this system. Here, this embodiment will be described using a block diagram on the encoder side for simplification of description, but it can also be realized on the decoder side for receiving the transmission data shown in FIG. Referring to FIG. The input terminal 27 has a sync signal S for the input video signal.
YNC is supplied. This synchronization signal SYNC is SYNC
It is input to the C signal detection circuit 28 and detected. SYNC
The signal detection circuit 28 synchronizes with the synchronization signal SYNC.
An NC pulse is generated and supplied to the track formation signal generation circuit 29. In the case of implementation in a decoder, the sync signal SYNC in the transmission data shown in FIG. 9 may be detected and input to the SYNC signal detection circuit 28.

FIG. 2A shows an input video signal, Y is a luminance signal, U and V are chrominance signals, and the numbers entered in the frame indicate the frame numbers. Figure 2
(B) is an SY signal obtained from the SYNC signal detection circuit 28.
The NC pulse is generated and is generated in synchronization with the switching point of the frame of the input video signal shown in FIG. FIG. 2C shows the track formation signal obtained from the track formation signal generation circuit 29. A and B added to the track forming signal specify a period in which the A head and the B head alternately form tracks. A
As shown in FIG. 1, the head and the B head are attached at a position opposed to the rotary drum 30 by 180 °. Here, the case where heads are attached one by one facing each other will be described. However, when the code amount that can be recorded in one track is small, p heads (p is a positive integer) are arranged facing each other. It is good, and the gist of this invention does not change. In this embodiment, the generation timing of the SYNC pulse shown in FIG. 2B and the switching timing of the track formation signal shown in FIG. 2C are synchronized. FIG. 2D shows tracks formed by the A head and the B head, and the numbers written in the frame indicate the track numbers.

The track formation signal output from the track formation signal generation circuit 29 is supplied to the track formation control circuit 31. This track formation control circuit 31
Controls the rotation phase of the rotary drum 30, and
The timing of supplying a recording signal to the head and the B head is controlled. In this embodiment, since the average code generation amount of one frame corresponds to one track, the rotary drum 3
A case where the number of revolutions of 0 is 900 rpm will be described. However, the gist of the present invention does not change when the average generated code of one frame is recorded on c tracks (c is a positive integer). Further, the gist of the present invention does not change even when the number of rotations of the rotary drum 30 is set to a different number of rotations such as 1800 rpm to form the c tracks.

Next, the code exchange method used in the present invention in order to enable the high speed reproduction of the VTR will be described. First, the color signals U supplied to the input terminals 32 and 33,
The multiplexer 37 converts each signal obtained by passing V through the decimators 34 and 35 and the luminance signal Y supplied to the input terminal 36 into a multiplexer 37.
The one combined in the subtraction circuit 12 is used as an input video signal.
And the variable length coding circuit 16 outputs the band compression coded video code.

Here, in the conventional band compression system shown in FIG. 8, the video signal is variable length coded and transmitted.
As shown in FIG. 2 (i), the switching points of the frames of the video code are different depending on the frames. Figure 2 (h)
The NMP signal shown in (1) indicates the switching point of the frame of this video code. Conventionally, 26 per frame
There are 40 superblocks and this 264
Zero super blocks are included in one frame period shown by the NMP signal in FIG.

Further, conventionally, there are four macro blocks in the horizontal direction on one screen, and these macro blocks are composed of 11 super blocks. Then, one superblock in the macroblock per frame is forced to use the intraframe processing. The sequence forcibly using the in-frame processing is included in the system control signal of FIG. Here, the super block for which the intra-frame processing is forcibly performed is referred to as a refresh block, and the super block for which the intra-frame processing is not forcibly performed is referred to as a non-refresh block.

That is, as the definition of the word, when the intra-frame processing is forcibly performed by one super block in one frame period of the refresh block: macro block, the super block subjected to the intra-frame processing is called a refresh block. Macroblock is 1
Since it is composed of one super block, the intra-frame processing is forcibly performed every 11 frame cycles. Non-refresh block: A super block other than the above-mentioned refresh block. Within this super block, there are a block subjected to intra-frame processing and a block subjected to inter-frame processing depending on the contents of the image. For example, when a scene change or the like occurs in the input video signal, in-frame processing may be used, but this is also a non-refresh block.

Here, 240 refresh blocks (= 2640/11) are present in one frame period. Therefore, conventionally, 240 refresh blocks are present in one frame period shown in FIG. 2H as shown in FIG. Then, the conventional signal is used as it is for VT.
When recording with R, the position of the refresh block is not fixed and high-speed reproduction cannot be performed as described above.

FIGS. 3A and 3B show video signals of frame numbers F5 and F6, respectively. In the figure, portions indicated by G5 and G6 indicate refresh blocks, and portions indicated by H5 and H6 indicate non-refresh blocks. Then, hereinafter, between the frame number, the refresh block number and the non-refresh block number, the refresh block number of the frame of the frame number Fn (n is an integer) is set to Gn and the non-refresh block number is set to Hn.

In the present invention, the arrangement of the refresh block and the non-refresh block on the track is different. That is, this embodiment shows the case where one track is divided into ten and recorded. When one track is divided into 10, high-speed reproduction can be performed up to 10 times speed. During high-speed playback of 11 times or more, all refresh blocks cannot be played.
Similar to the diagram shown in FIG. 5 (d), an area where an image cannot be formed occurs. If VTR specifications are 2
When it is desired to realize high speed reproduction of 0 × speed, one track may be divided into 20. Further, when it is desired to realize fast high speed reproduction, refresh blocks may be arranged on the track at equal intervals.

FIG. 2 (e) shows a timing pulse for dividing one track into ten, and the one track period shown in FIGS. 2 (b) and 2 (c) is divided into ten equal parts.
Then, this one divided period is referred to as a sector. That is, as the definition of the term, it means a period obtained by dividing a sector: one track period by d (10 in this case) into approximately equal parts.

In this embodiment, as shown in FIG. 2 (f), 24 refresh blocks are put in one sector. In this way, one track consists of 10 sectors, and 240 refresh blocks are inserted in one track, which is equal to the number of refresh blocks in one frame of the video signal. That is, the number of refresh blocks e in one sector is b, which is the number of super blocks on which periodic intraframe processing is performed,
If b intra-frame processed signals are recorded on c tracks, e = b / c × d (in this case, 240/1 × 10
= 24).

By performing the code exchange as described above, the refresh block for one frame is conventionally arranged in one frame period indicated by the NMP signal so that the refresh block exists in one track period. Can be placed.

FIG. 4 shows a track pattern. That is, tracks T1 to T1 on the magnetic tape 26
G1 to G11 entered in the frame of 1 correspond to the refresh block number Gn described above. The relationship between the refresh block and the track Tn is that the refresh block with the number Gn is recorded in the track Tn. Further, H1 to H11 entered in the frames of the tracks T1 to T11 correspond to the above-mentioned non-refresh block number Hn. The switching point of the non-refresh block is the thick line portion shown in the frame of the tracks T1 to T11.

Track 38 in FIG. 4 shows the relationship between sectors and tracks. The track 38 is divided into 10 and d =
It is divided into 10 sectors. In this one sector,
e = 24 refresh blocks are arranged. The non-refresh block is inserted between the refresh blocks.

The tracks T5 and T6 will be described in detail as an example. The refresh block G5 of the frame F5 is recorded on the track T5. Also, track T
In 6, a refresh block G6 of the frame F6 is recorded. A non-refresh block is recorded in the free space where this refresh block is arranged. The non-refresh blocks H5 and H6 are recorded on the track T5, and the non-refresh blocks H6 and H7 are recorded on the track T6.

Therefore, in order to realize the above recording mode, the band compression encoded video code obtained from the variable length encoding circuit 16 in FIG. 1 is supplied to the code exchange circuit 39 again. Further, the refresh block control circuit 40 generates the code position signal of the refresh block described above, and this code position signal is supplied to the code exchange circuit 39. The code exchange circuit 39 rearranges refresh blocks and non-refresh blocks based on the input video code and code position signal.

That is, a process of inserting 24 refresh blocks into each of 10 sectors provided in one track is performed. In order to perform this processing, the code is temporarily stored in a memory (not shown), and when the code is read from the memory, 24 refresh blocks are read in one sector.

The output of the code exchange circuit 39 is
It is supplied to the index insertion circuit 41. The index insertion circuit 41 inserts an index signal into the control data section of each sector so that it can be detected during reproduction that the non-refresh block is partially separated and recorded. The index signal is prepared by the index generation circuit 42 to which the code position signal from the refresh block control circuit 40 is supplied. The output of the index insertion circuit 41 is
The data is supplied to the A head and the B head via the multiplexer 43 and recorded on the magnetic tape 26.

When the refresh block and the non-refresh block are exchanged in the decoder, the PCM / DPCM of the head data existing at the head of the macro block inside the video code shown in FIG.
The refresh sequence code included in the determination code and the system control signal may be detected and used as the output signal of the refresh block control circuit 40.

FIGS. 5A and 5B show trace traces X1 to X11 of the head during double speed reproduction.
The refresh blocks Gn and the non-refresh blocks Hn are shown in the frames of the tracks T1 to T22 as in FIG. Then, in the head trace at the time of double speed reproduction shown in FIG. 5, refreshable blocks that can be reproduced are shown in FIGS. 6 (a) to 6 (h) and 7 (a) to 7 (a).
It is shown in (c). This figure (a)-(h) and FIG.
Frames 1 to 11 shown in FIGS. 5A to 5C are shown in FIG.
Head trace loci X1 to X11 during double speed reproduction shown in
Shows a refresh block that can be reproduced.

For example, in frame 1, by performing the head trace X1, it is possible to display the refresh block G1 in the upper half of the screen and the refresh block G2 in the lower half of the screen. Similarly, in frames 2 to 11, refresh block G3
Up to G22 can be reproduced. For this reason,
By accumulating the reproducible refresh blocks from frames 1 to 11, the codes of all the screen areas can be reproduced as shown in FIG.

The code subjected to interframe processing and the code subjected to intraframe processing according to the contents of the image are put between the codes subjected to the intraframe coding processing periodically. Then, these codes have no correspondence between the image area and the recording medium area.
The a image areas and the d × c × f recording medium areas may be associated with each other at a ratio of 1: 1 or 1 :.
Any correspondence may be used, such as 2, 2: 1 correspondence, or a correspondence in which a space is inserted in the area of the recording medium. The present invention can also be applied to a video disc, in which case one round of the disc corresponds to one track of the tape.

With respect to claim 2, in claim 1,
Considering that f frames are f × g, it is considered that there are g types of association between a image regions to be subjected to intra-frame coding processing and d × c × f recording medium regions, and f × g frames are considered. If it is repeated in a cycle, the same applies as in claim 1.

The present invention is not limited to the above embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0050]

As described in detail above, according to the present invention,
It is possible to provide a very good recording / reproducing apparatus that can easily obtain a good reproduced image during high-speed reproduction.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a recording / reproducing apparatus according to the present invention.

FIG. 2 is a timing chart shown for explaining the operation of the embodiment.

FIG. 3 is a diagram showing a relationship between refresh blocks having frame numbers F5 and F6 and non-refresh blocks in the embodiment.

FIG. 4 is a diagram showing a track pattern in the same embodiment.

FIG. 5 is a diagram showing a head trace locus during double speed reproduction in the example.

FIG. 6 is a diagram showing refreshable refresh blocks of frames 1 to 8 in the embodiment.

FIG. 7 is a diagram showing a reproducible refresh block of frames 9 to 11 and a refresh block in which 11 frames are accumulated in the embodiment.

FIG. 8 is a block diagram showing a conventional band compression system.

FIG. 9 is a diagram showing a format of a signal transmitted from the conventional system.

FIG. 10 is a diagram showing refresh blocks that can be played back in frames 1 to 8 during normal playback in the conventional system.

FIG. 11 is a diagram showing refreshable blocks that can be played back in frames 9 to 11 and refresh blocks that have accumulated 11 frames during normal playback in the conventional system.

FIG. 12 is a diagram showing a track pattern in the conventional system.

FIG. 13 is a diagram showing a head trace locus during double-speed reproduction in the conventional system.

FIG. 14 is a diagram showing refresh blocks capable of reproducing frames 1 to 8 during double speed reproduction in the conventional system.

FIG. 15 is a diagram showing a refresh block capable of reproducing from frames 9 to 11 and a refresh block accumulating 11 frames during double speed reproduction in the conventional system.

[Explanation of symbols]

11 ... Input terminal, 12 ... Subtraction circuit, 13 ... Motion evaluation circuit, 14 ... DCT circuit, 15 ... Quantization circuit, 16 ... Variable length coding circuit, 17 ... FIFO circuit, 18 ... Output terminal,
19 ... Inverse quantization circuit, 20 ... Inverse DCT circuit, 21 ... Addition circuit, 22 ... Frame delay circuit, 23 ... Motion compensation circuit,
24, 25 ... Switch, 26 ... Magnetic tape, 27 ... Input terminal, 28 ... SYNC signal detecting circuit, 29 ... Track forming signal generating circuit, 30 ... Rotating drum, 31 ... Track forming control circuit, 32, 33 ... Input terminal, 34, 35 ... Decimator, 36 ... Input terminal, 37 ... Multiplexer, 38
... track, 39 ... code exchange circuit, 40 ... refresh block control circuit, 41 ... index insertion circuit,
42 ... Index generating circuit, 43 ... Multiplexer.

Claims (2)

[Claims] 1. An intra-frame processed signal obtained by subjecting a video signal to intra-frame coding processing using information within a frame, and an inter-frame signal subjected to inter-frame coding processing using difference information between frames. And a band compression unit that adaptively repeats a signal processing method for creating a processed signal and performing the inter-frame coding process after the intra-frame coding process according to the motion evaluation of the input video signal. In a recording / reproducing apparatus for recording and reproducing the output of the compression means on a recording medium, in the image area of one screen, a number (a is a positive integer) of the a area covering the image area of the one screen Image areas are formed, and the intra-frame encoding processing means is configured to perform the intra-frame encoding processing on the a number of image areas in a cycle of f frames (f is an integer of f ≧ 2); 1 track is almost equal Means for forming d × c × f recording medium areas per f frame by using d tracks (d is a positive integer) for one frame and using c tracks (c is a positive integer) per frame, A recording / reproducing apparatus comprising: a recording means for recording a number of image areas to be subjected to intra-frame coding processing and the d × c × f recording medium areas in association with each other. 2. When associating the a number of image areas to be subjected to the intra-frame coding processing with the d × c × f number of recording medium areas, there is one type of association per f frame, and f Xg frames (where g is a positive integer) have g types of correspondences, and the image regions to be subjected to the a-frame intra-frame coding processing and the d × c × f number of the a × g frame are cycled. The recording / reproducing apparatus according to claim 1, wherein the g type is associated with a recording medium area and recorded.