JPH05136691A - Synchronizing counter - Google Patents

Abstract

PURPOSE:To obtain the synchronizing counter of a multi-bit length operated at a high speed. CONSTITUTION:Outputs of T-FFs 102-104 are subject to re-clock by D-FFs 201-203 and outputs of the D-FFs 201, 202 are given to next-stage T-FF 103, 104. Thus, the outputs of the T-FFs 102-104 are delayed by stages of the flip- flops in comparison with a clock signal CKa. Thus, re-clock is attained by the D-FFs 201-203 and the synchronizing counter of a multi-bit length operated at a high speed is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous counter that operates in synchronization with a clock signal in a semiconductor integrated circuit or the like.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
Tadao Saito "Digital Circuit" 6th Edition (Sho 62-10-3
0) Corona, P. 102-103. The configuration will be described below with reference to the drawings.

FIG. 3 is a circuit diagram showing an example of the configuration of a conventional 4-bit synchronous counter. This 4-bit synchronous counter has four JK-type flip-flops (hereinafter, JK-
FF) 10 to 13, and the least significant bit (L
The logic "1" is connected to the two input terminals J and K of the SB) JK-FF10. Of the positive phase output terminal Qa and the negative phase output terminal Qb of the JK-FF10, the output terminal Qa is
Output terminal Q0 of LSB, two input terminals J and K of JK-FF11, and AND gate (A) for carry (carry).
ND gates) 21 and 22, respectively.

The output terminal Qa of the JK-FF11 is connected to the output terminal Q1 and AND gates 21 and 22, and its A
The ND gate 21 is connected to the two input terminals J and K of the JK-FF12. The output terminal Qa of the JK-FF 12 is connected to the output terminal Q2 and the AND gate 22, and its AN
The D gate 22 is connected to the two input terminals J and K of the JK-FF 13, and the output terminal Qa of the JK-FF 13 is connected to the output terminal Q3 of the most significant bit (MSB). The clock input terminal of each JK-FF10-13,
The anti-phase clock signal CKb is commonly connected.

The JK-FFs 10 to 13 have two input terminals J,
When both K are set to "0", the current state is held, and when both are set to "1", the output is inverted. By the negative edge trigger (falling edge) of the clock signal CKb, the JK-FF10
Is a signal obtained by dividing the clock signal CKb by 1/2,
Output to the output terminal Q0, the input terminals J and K of the JK-FF11, and the AND gates 21 and 22.

The output terminal Q0 of the JK-FF11 is "1".
At this time, the output state is inverted in synchronization with the negative edge trigger of the clock signal CKb, and it is output to the output terminal Q1 and the AND gates 21 and 22. JK-FF12,13,
When the output terminals Q1 and Q2 are "1", the output states are inverted in synchronization with the negative edge trigger of the clock signal CKb and are output from the output terminals Q2 and Q3, respectively.
In this way, a 4-bit binary counter operation is executed.

By the same connection method as in FIG. 3, n JK-
An n-bit synchronous counter can be configured using the FF.

[0008]

However, the synchronous counter having the above structure has the following problems.

(A) When the number of JK-FFs 10 to 13 is increased to increase the number of bits, the LSB JK-FF 10 is increased.
The number of JK-FFs 11 to 13 connected to the output terminal Qa of the JK-FF 10 increases, and the fanout number (1
The number of parallel loads connected to the output terminals of one gate increases. Therefore, there is a problem that the operation speed of the synchronous counter becomes slow.

(B) When the number of bits increases, the number of fan-ins of the AND gate 22 connected to the input terminals J and K of the JK-FF 13 of the MSB (the number of inputs that can be connected to one gate in the logic gate). However, there is also a problem that the operation speed of the synchronous counter is slowed down.

The present invention provides a synchronous counter which solves the problem that the above-mentioned prior art has the problem that the operating speed is reduced due to an increase in the number of bits.

[0012]

In order to solve the above problems, the present invention provides an n-bit (where n is a natural number) synchronous counter that operates in synchronization with a clock signal, and outputs based on the clock signal. A first toggle flip-flop (hereinafter, referred to as T-FF) whose state is inverted, a second to nth T-FF, and an output side of the second to nth T-FF, respectively, The first to (n-1) th delay flip-flops (hereinafter referred to as D-FFs) are provided, which receive the output of each T-FF in synchronization with the clock signal and output at a predetermined timing. ..

The second T-FF is the first T-FF.
The third to nth T- are operated in synchronization with the output of the FF.
The FF is operated in synchronization with the outputs of the first to (n-2) th D-FFs, and further, the output of the first T-FF and the first to (n-1) th D-FFs. And the output of are counter outputs.

[0014]

According to the present invention, since the synchronous counter is constructed as described above, the first T-FF receives the clock signal, inverts the output state based on the clock signal, and outputs the LS signal.
The counter output of B is transmitted. The counter output of the LSB is input to the second T-FF, and the output of the second T-FF is sent to the first D-FF. In the first D-FF, the output of the second T-FF is input in synchronization with the clock signal, and the counter output of the second bit is sent out at a predetermined timing. The output of the counter of the second bit is the third T-
Input to FF. The same operation is performed thereafter, and the second to nth T
The output of the −FF is reclocked by the first to (n−1) th D-FFs, and the output of the first to (n−2) th D-FFs is the third.
~ Is sequentially input to the n-th T-FF. Therefore, the above problem can be solved.

[0015]

1 is a circuit diagram of a 4-bit synchronous counter showing an embodiment of the present invention. The 4-bit synchronous counter includes first to fourth T-FFs 101 to 104 and first to fourth T-FFs 101 to 104.
The third D-FFs 201 to 203 have a function of counting the clock pulses in synchronization with the positive phase clock signal CKa and outputting the clock pulses from the 4-bit output terminals Q0 to Q3. Each of the T-FFs 101 to 104 has clock terminals C1 to C4 and output terminals TQ1 to TQ4, respectively. In addition, each of the D-FFs 201 to 203 has input terminals D1 to D3, clock terminals CL1 to CL3, and positive phase output terminals Qa1 to Qa3, respectively.

The positive-phase clock signal CKa is the first T-F.
A clock terminal C1 of F101 and first to third T-F
The clock terminals CL1 to CL3 of the F201 to 203 are supplied to the output terminal TQ1 of the first T-FF101.
The second TF is connected to the output terminal Q0 of the SB
It is connected to the clock terminal C2 of F102. The output terminal TQ2 of the second T-FF 102 is connected to the first D-FF2.
01 is connected to the input terminal D1 of the third T-FF 103, and its output terminal Qa1 is connected to the output terminal Q1 of the second bit and the clock terminal C3 of the third T-FF 103.

Output terminal TQ3 of the third T-FF 103
Is connected to the input terminal D2 of the second D-FF 201,
The output terminal Qa2 is connected to the output terminal Q2 of the third bit and the clock terminal C4 of the fourth T-FF 104. The output terminal TQ4 of the fourth T-FF 104 is connected to the input terminal D3 of the third D-FF 203, and its output terminal Qa3 is connected to the output terminal Q3 of the MSB.

FIG. 2 is a timing chart of FIG.
The operation of FIG. 1 will be described with reference to this figure. In FIG. 2, t1 is the delay time of the T-FF 101, and t2 is T-F.
The delay time of F102, t3 is the delay time of T-FF103, and t is the delay time of D-FF201. Also A0
A3 is the fall timing.

All T-FFs 101-104 and D-
The FFs 201 to 203 operate at a negative edge (falling edge), for example. T-FF101 is a clock signal CK
It operates in synchronization with a, and every time two clock pulses are input, the output terminal TQ1 of the T-FF101 falls,
The LSB output terminal Q0 of the counter falls. T-FF1
02 operates in synchronization with the fall of the output terminal TQ1, and the output terminal TQ2 falls every time two falling outputs of the output terminal TQ1 are input. The output from the output terminal TQ2 becomes a signal synchronized with the clock signal CKa by the D-FF 201, and the output terminal Qa1 to the output terminal Q1.
To output the second bit output of the counter.

The T-FF 103 operates in synchronization with the fall of the output terminal Qa1 of the D-FF 201, and its output terminal Ta.
The output of Q3 is the clock signal CK by the D-FF202.
It becomes a signal synchronized with a, and the output of the third bit is obtained from the output terminal Q2 of the counter. Similarly, T-FF104 is D
The FF202 operates in synchronization with the fall of the output terminal Qa2, the output of the output terminal TQ4 becomes a signal synchronized with the clock signal CKa by the D-FF203, and the MSB output is obtained from the output terminal Q3 of the counter.

Here, the output edge of the T-FF 102 is
When the clock signal CKa falls, the T-FF101
Of the delay time t1 and the delay time t2 of the T-FF 102. The output edge of the T-FF 103 is delayed by the delay time t of the D-FF 201 and the delay time t3 of the T-FF 103 with respect to the falling edge of the clock signal.

The outputs of the T-FFs 101 to 104 are normally JK- synchronized with the clock signal CKb as shown in FIG.
Since the outputs of the FFs 10 to 13 are used, the delay with respect to the input clock is the delay time of JK-FF. Therefore,
The output of each T-FF 102 to 104 is a clock signal CK.
Since it is delayed by two FF stages compared to a, each D-FF2
01 to 203 can be used for reclocking (timing adjustment).

The outputs of the T-FFs 102 to 104 are D
Since it is synchronized with the clock signal CKa by passing through each of the FFs 201 to 203, the falling signals of the output terminals Q0 to Q3 propagate to the upper bits and become 1 clock, as at the falling timings A0 to A3 in FIG. Delay one by one. Therefore, it is natural 2 like a normal binary counter.
A value different from the base number is output. But one in a row
Since the output data obtained by inputting 6 (2 ⁴ ) clock pulses are all different, it can be used as a synchronous counter. This means that there is no problem even if a counter having an arbitrary number of bits is produced with the same configuration.

As described above, in this embodiment, T-FF1
The outputs of 02 to 104 are reclocked by the D-FFs 201 to 203, and the output data of the D-FFs 201 and 202 are input to the T-FFs 103 and 104 of the next stage. Therefore, even if the synchronous counter is composed of a large number of T-FFs 101 to 104, the output of each of the T-FFs 101 to 104 lags behind the clock signal CKa by only two stages of FFs. Therefore, it is possible to configure a synchronous counter having a T-FF having a multi-bit length that operates at high speed.

Further, when the output signals of the output terminals Q0 to Q3 reach a specific value by using a decoder (not shown), a reset signal is generated from the decoder and each of the T-FFs 101 to 101.
When the 104 and the D-FFs 201 to 203 are reset (or set), a synchronous counter with an arbitrary cycle can be realized.

The present invention is not limited to the above embodiment,
Various modifications are possible. Examples of such modifications include the following.

(A) Although the 4-bit synchronous counter has been described with reference to FIG. 1, in the case of forming a synchronous counter having another number of bits, the 1st to nth D-FFs and the 1st to (nth) are used.
-1) D-FF, the first T-FF operates in synchronization with the clock signal CKa, the second T-FF operates in synchronization with the output of the first T-FF, 2nd to nth T-
The output of the FF is synchronized with the clock signal CKa by using the first to (n-1) th D-FFs. Furthermore, the k-th
The (3 ≦ k ≦ n) T-FF may be operated by the output of the (k−1) th T-FF synchronized with the clock signal CKa.

(B) Although the T-FFs 101 to 104 and the D-FFs 201 to 203 in FIG. 1 are operated at the negative edge, they may be operated at the positive edge (rising edge). In addition, each T-FF
The outputs of 101 to 104 are inverted every time two clock pulses are input, but the number of input clock pulses can be changed to another arbitrary number. Even in this case, almost the same advantages as those of the above embodiment can be obtained.

[0029]

As described in detail above, according to the present invention, the output of the T-FF is reclocked by the D-FF and the output data is used as the input of the T-FF in the next stage. Therefore, even if a large number of T-FFs are used, the output of each T-FF lags behind the clock pulse by, for example, several stages of flip-flops, and thus reclocking is possible with the D-FF. Therefore, a high-speed and multi-bit synchronous counter can be easily constructed.

Further, when the output of the counter reaches a specific value, a reset signal is generated by using a decoder or the like to reset or set each T-FF and D-FF. A cycle counter can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a 4-bit synchronous counter showing an embodiment of the present invention.

FIG. 2 is a timing chart of FIG.

FIG. 3 is a circuit diagram of a conventional 4-bit synchronous counter.

[Explanation of symbols]

 101-104 T-FF 201-203 D-FF

Claims (1)

[Claims] 1. An n-bit (where n is a natural number) synchronous counter that operates in synchronization with a clock signal, comprising a first toggle flip-flop whose output state is inverted based on the clock signal, and a second toggle flip-flop. The n-th toggle flip-flop and the output sides of the second to n-th toggle flip-flops are connected to each other, and the outputs of the toggle flip-flops are input in synchronization with the clock signal at predetermined timing. Outputting first to (n-1) th delay flip-flops, wherein the second toggle flip-flop is operated in synchronization with the output of the first toggle flip-flop, and the third to third delay flip-flops are output. The n-th toggle flip-flop is operated in synchronization with the outputs of the first to (n-2) th delay flip-flops, and the first toggle flip-flop is operated. Synchronous counter, wherein the output of the drop between the output of the first to the delay-type flip-flop of the (n-1), and to the configuration and counter output.