JPH05136661A - Clock synchronizer circuit - Google Patents

Abstract

PURPOSE:To control a voltage controlled oscillator by detecting a half flag representing whether a memory occupancy rate written in a FIFO is more or less than half the memory capacity. CONSTITUTION:As soon as a counter 8 is reset when a half flag (h) outputted from the FIFO 11, the counter 8 is counted and a most significant bit (i) of the count result is outputted to the control circuit 9. The control circuit 9 outputs a voltage depending on a level as to whether or not the most significant bit (i) is outputted, thereby varying the oscillating frequency of a voltage controlled oscillator 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronizing circuit for generating a clock synchronized with a received clock.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional clock synchronizing circuit.
The transmission line clock a received by the input terminal 1 is the counter 2
Is input to the counter 2 and the transmission path clock a is 1 / M in the counter 2.
The frequency-divided clock b is divided into. The oscillation clock c of the voltage controlled oscillator 4 is input to the counter 5, where the divided clock d is generated by dividing the oscillation clock c by 1 / N. The divided clock b and the divided clock d are input to the phase comparator 3. The phase comparator 3 creates a control signal e for controlling the voltage controlled oscillator 4 based on the phase comparison determination result, and outputs it to the LPF (low pass filter) 6. L
The PF 6 removes a high frequency component of the control signal e to create a control voltage f, and outputs the control voltage f to the voltage controlled oscillator 4. In the voltage controlled oscillator 4, the oscillation frequency c is controlled by the control voltage f and the oscillation clock c synchronized with the transmission clock a.
And outputs the oscillation clock c to the counter 5 and the output terminal 7.

[0003]

However, in such a conventional circuit, it is necessary to use a phase comparator having a complicated circuit configuration, and in addition to this, the transmission line clock and the oscillator output of the voltage controlled oscillator are separated. In order to obtain a frequency corresponding to the greatest common divisor by dividing, a counter with a large frequency division ratio is required, and there is a drawback that the entire circuit configuration becomes very complicated.

[0004]

The clock synchronization circuit of the present invention includes a FIFO (11) for outputting a half flag (h) indicating whether the memory occupation amount of written data is above or below half the memory capacity. , When the half flag detects that the memory occupancy of the data written in the FIFO is more than half of the memory capacity, the preset value is counted after reset and the most significant bit (i) of the count result (8), a control circuit (9) that outputs a different control voltage (j) depending on whether the most significant bit is output, and a voltage control that changes the oscillation frequency according to the change in the control voltage of the control circuit. It consists of an oscillator (10).

[0005]

When the transmission line clock and the like are input to the write terminal of the FIFO and the output signal of the voltage controlled oscillator is input to the read terminal of the FIFO, if the written data of the FIFO does not exceed half the memory occupation, The controlled oscillator oscillates at a certain frequency. When the writing amount is larger than the reading amount and the accumulated data amount increases, and the memory occupation amount of the FIFO exceeds half, counting is started after the counter is reset. By resetting the counter, the output of the most significant bit is lost, and the voltage controlled oscillator oscillates at a higher frequency than it is now. Then, since the read amount of the FIFO increases, the memory occupation amount decreases. When the counter counts a fixed number, the most significant bit is output and the voltage controlled oscillator returns to a low oscillation frequency.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 shows a block diagram of an embodiment of the present invention. Transmission line clock k input from the input terminal 12
Are input to a write clock input terminal of a FIFO (first-in first-out circuit) 11. On the other hand, the oscillator output g output from the voltage controlled oscillator (VCO) 10 is input to the read clock input terminal of the FIFO 11. The FIFO 11 outputs to the counter 8 a half flag h which becomes high level when the memory occupancy of the data being read or written is half (50%) or less of the memory capacity, and becomes low level when it is more than half. The counter 8 is reset at the trailing edge of the half flag h, and after that, after counting the oscillator output g and counting a predetermined fixed number, it is stopped until the next trailing edge of the half flag. Counter 8 by counting a fixed number
The most significant bit i of is carried to a high level output signal and output to the control circuit 9. This most significant bit i
The high level of is maintained as it is and continues until it is reset at the next falling edge of the half flag.

FIG. 2 shows details of the control circuit 9. The control circuit 9 includes a ROM 91 and a digital / analog converter 92. The most significant bit i from the counter 8 is input to the ROM 91. In the ROM 91, the value output to the digital / analog converter 92 is changed depending on whether the most significant bit i is 1 or 0. The digital-analog converter 92 digital-analog converts the signal from the ROM 91 and outputs it as the control voltage j to the voltage controlled oscillator 10.

Next, FIG. 3 shows an operation waveform diagram of the embodiment shown in FIG. When the oscillation frequency of the voltage controlled oscillator 10 changes, the FI
Memory occupancy of data written in FO11 is 50%
When it exceeds, the half flag h changes from the high level to the low level. The counter 8 is reset by the fall of the half flag h. When the most significant bit i of the output of the counter 8 changes from high level to low level, the control circuit 8 causes the control voltage j of the voltage controlled oscillator 10 to make the oscillation frequency of the voltage controlled oscillator 10 higher than the frequency of the transmission path clock k. Changes to. As the oscillation frequency of the voltage controlled oscillator 10 increases, the amount of data written in the FIFO gradually decreases. Since the counter 8 stops after counting a certain number of counts, the count changes the most significant bit i from low level to high level.

When the most significant bit i of the output of the counter 8 becomes high level, the control circuit 8 outputs the control voltage j to the voltage controlled oscillator 10 so that the oscillation frequency of the voltage controlled oscillator 10 becomes lower than the frequency of the transmission line clock k. .. By repeating the above operation, the oscillation frequency of the voltage-controlled oscillator 10 changes above and below the frequency of the transmission line clock k and is kept almost constant at all times, and the output terminal 13 is synchronized with the transmission clock.
Is output from.

[0010]

As described above, according to the present invention, in order to obtain a frequency corresponding to the greatest common divisor by dividing the phase comparator having a complicated circuit structure and the transmission line clock and the oscillator output of the voltage controlled oscillator. This eliminates the need for a counter having a large frequency division ratio, and simplifies the overall circuit configuration.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is a configuration block diagram showing the contents of a control circuit in FIG.

FIG. 3 is an operation waveform diagram of each part of FIG.

FIG. 4 is a configuration block diagram of a conventional clock synchronization circuit.

[Explanation of symbols]

 8 counter 9 control circuit 10 voltage controlled oscillator (VCO) 11 FIFO 12 input terminal 13 output terminal g read clock h half flag i most significant bit j control voltage k transmission line clock

Claims (1)

[Claims] 1. A FIFO that outputs a half flag indicating whether the memory occupation amount of written data is above or below half the memory capacity, and the memory occupation amount of data written in the FIFO by the half flag is the memory capacity. When it is detected to be higher than half, a counter that counts a predetermined value after reset and outputs the most significant bit of the count result, and a control voltage that differs depending on whether the most significant bit is output or not. A clock synchronization circuit comprising a control circuit for outputting and a voltage controlled oscillator whose oscillation frequency changes according to a change in control voltage of the control circuit.