JPH05135950A - Inductance device and its manufacture - Google Patents

Abstract

PURPOSE:To realize a decrease in size and an increase in performance of an inductance device in forming it of conductor wiring on the substrate of a semiconductor integrated circuit. CONSTITUTION:A conductor wiring 2 constituting a device is arranged by repeated bending for uneven form in the vertical direction to the substrate 1 face, and the lower face of the bottom of a recess wiring is adhered on the substrate 1, so that the projecting wiring floats on the substrate to keep a spatial spread from the substrate face.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an inductance element of a semiconductor integrated circuit such as a mixed GaAs IC for communication and a method for manufacturing the same.

[0002]

2. Description of the Related Art Heretofore, an inductance element is often of a construction type in which an electric conductor wiring which constitutes the element is made uneven in a plane direction of a substrate or meandered in a wavy shape (meaning). It was The literature includes, for example, AR A. Poussel, "Considerations on Monolithic Microwave Circuit Design", I.E.E.E.
Transactions on Microwave Theory and Technics, MITI Volume 29,
No. 6, June 1981 (RA Pucel, “Design Consi
derations for Monolithic Microwave Circuits ", IEEE
Trans. On Microwave Theory and Techniques, Vol. M
IT-29, No.6, June 1981.).

FIG. 21 is a schematic view of a conventional meandering type inductance element. (A) is a plan view, (b) is a sectional view taken along line AA ', 1 is a substrate, 2 is a conductor wiring. Shows. In the conventional element, the conductor wiring 2 is formed by patterning a planar thin film, and the waveform for bending the current path to generate the inductance is provided in the plane direction of the substrate. 22A and 22B show another conventional example. FIG. 22A is a plan view of a convex pattern, and FIG. 22B is a plan view of a concave pattern. That is, the thin film pattern is not in a corrugated shape but in a rod shape having a convex portion and a concave portion.

[0004]

The above-described conventional inductance element requires a certain area in the plane of the substrate, which is an obstacle to circuit miniaturization. Further, in such a configuration, even if another wiring portion is arranged in an adjacent place and the mutual inductance between the wirings is used to improve the performance of the inductance,
Since the mutual inductance cannot be effectively increased, a sufficient effect cannot be obtained.

An object of the present invention is to realize a compact and high-performance element by arranging the conductor wiring which constitutes the element in the direction perpendicular to the substrate, and to miniaturize and improve the performance of semiconductor circuits such as hybrid ICs. An object of the present invention is to provide a possible inductance element and a manufacturing method thereof.

[0006]

In order to achieve the above object, according to claim 1 of the present invention, in an inductance element arranged on a substrate of a semiconductor integrated circuit, an electric conductor wiring constituting the element is a substrate. It is repeatedly bent and arranged so that it becomes uneven in the direction perpendicular to the surface, and the bottom surface side of the bottom of the recess wiring is adhered to the substrate.
The convex wiring is an inductance element having a structure that floats above the substrate and holds a spatial expansion region between the convex wiring and the substrate surface.

According to a second aspect of the present invention, there is provided a method of manufacturing an inductance element arranged on a substrate of a semiconductor integrated circuit,
(A) a step of forming unevenness made of the first insulator on the substrate by patterning in a striped pattern, a pine pattern, or a part or a combination of these parts;
(B) A step of depositing an electric conductor to a predetermined thickness on the side wall of the first insulator and the entire surface of the substrate by a sputtering method, and (c) a second insulator on the electric conductor film. A step of patterning and attaching the inductance element wiring to be formed so as to have the same plane pattern as seen from above, and (d) using the second insulator as a mask, A step of removing a portion not covered by the mask by etching, and then removing the remaining first and second insulators is performed.

According to a third aspect of the present invention, in the method of manufacturing an inductance element arranged on a substrate of a semiconductor integrated circuit, (a) the unevenness of the first insulator is formed on the substrate in a striped pattern or a stripe pattern. Or a step of patterning a part of these or a part of them into a pattern in which they are combined with each other, and (b) a first conductive film on the side wall of the first insulator and the entire surface of the substrate by a sputtering method. And (c) depositing a second layer of a predetermined thickness on the first conductor film.
The step of growing the above-mentioned electric conductor film by an electrolytic plating method using the first electric conductor film as an electrode, and (d) an inductance element for forming a second insulator on the second electric conductor film. A step of patterning and adhering the wiring so that it has the same plane pattern as that seen from above, and (e) a mask of the first and second conductive films using the second insulator as a mask. And a step of removing the remaining first and second insulators by etching, and then removing the portion not covered by the.

[0009]

When the inductance element is formed on the substrate of the semiconductor integrated circuit, the conductor wiring that forms the element is made uneven in the direction perpendicular to the substrate surface or wavy in a wavy manner, so that It is possible to achieve a significant reduction in size as compared with the conventional configuration having unevenness. Further, the mutual inductance can be effectively used, and the performance of the inductance is improved. Also,
Forming an inductance element having such a configuration on a substrate is achieved by appropriately combining and utilizing various techniques developed so far for manufacturing a semiconductor device.
It is easily feasible.

[0010]

1 is a plan view of an inductance element according to a first embodiment of the present invention, and FIG.
It is an A'sectional view. In the figure, 1 is a substrate, 2 is an electric conductor wiring which constitutes an inductance element, and this electric conductor wiring 2 is a pattern of a thin film so as to make unevenness in the vertical direction on the substrate 1, Inductance is generated by bending. The bottom surface of the bottom of the concave wiring is adhered to the upper surface of the substrate 1, and the convex wiring floats above the substrate and holds a spatial expansion area between the convex wiring and the substrate surface. Has become. The expanded region may have a structure for holding an insulating material or a structure for leaving it as a void, as will be described later in the embodiment of the manufacturing method. When viewed from above, the element of the present embodiment has a simple straight wiring as shown in FIG. 4A, and the area occupied by the substrate plane can be remarkably reduced as compared with the conventional example.

2A and 2B show a second embodiment of the inductance element according to the present invention, in which FIG. 2A is a plan view and FIG.
A 'sectional view, (c) shows a BB' sectional view. In this embodiment, the wiring shown in FIG. 1 is folded back in the middle, and immediately after the wiring is folded back, the concavo-convex shape of the other neighboring wiring is displaced by a half cycle. When the periods of the irregularities are not evenly spaced, the spines and antinodes of the waves or the concaves and convexes of the irregularities are arranged adjacent to each other. As a result, both wirings interfere with each other and have mutual inductance. Therefore, the inductance of the entire device is increased by this mutual inductance, and the device characteristics are improved.

FIG. 3 shows a third embodiment, (a) is a plan view, (b) is a sectional view taken along line AA ', and (c) is BB'.
FIG. This is an example with multiple turns. That is, the mutual inductance is further increased by forming the wiring so as to meander in a wavy shape even in a plan view.
This makes it possible to further improve the device performance.

FIG. 4 shows a fourth embodiment, (a) is a plan view, (b) is a sectional view taken along the line AA ', and (c) is a line BB'.
Sectional drawing, (d) is EE 'sectional drawing, (e) is FF' sectional drawing. This is an example of the case where the number of wiring turns is increased by the wiring shown in FIG. 2, and as a result, it is a kind of solenoid.

FIG. 5 shows a fifth embodiment, (a) is a plan view, (b) is a sectional view taken along line AA ', and (c) is BB'.
Sectional drawing, (d) is EE 'sectional drawing, (e) is FF' sectional drawing. This element is also an example of the case where the number of wiring turns is increased by the wiring shown in FIG. 2, which is a kind of solenoid whose basic element is not a ring but a figure-eight. As will be described later, according to the manufacturing technique of the present invention, this structure can be formed by a single wiring forming process without passing through a plurality of wiring forming processes, although it is a kind of solenoid. ..

FIG. 6 is a plan view showing a sixth embodiment, which is a spiral type inductance element formed by using the wiring structure according to the present invention. Similar to the relationship between the AA 'cross section and the BB' cross section in FIG. 2, each wiring portion of the spiral has a structure in which the wave period is shifted by a half cycle, and the normal wiring is divided by the inductance between adjacent wirings. The inductance can be made larger than that of the spiral type inductance element.

FIG. 7 shows an example of a transformer formed by using the inductance element according to the present invention, which is AA ', B in the figure.
Similar to the relationship shown in FIGS. 2B and 2C, the cross section along -B 'has a structure in which the wave period is shifted by a half period. The cross-sectional views are basically the same as those shown in FIGS.

FIG. 8 shows another example of the transformer formed by using the inductance element according to the present invention.
The cross sections along A'and BB 'are shown in FIGS. 2 (b) and 2 (c).
Similar to the relationship shown in the figure, it has a structure in which the wave cycle is shifted by a half cycle. The cross-sectional view is basically shown in FIG.
(C) It is the same as the figure, so it is omitted. 7 and 8 described above
According to the transformer described in (1), the mutual inductance between the inductance elements is large because the wave period is deviated, and a small and high-performance transformer can be realized.

Next, one embodiment of the manufacturing process of the inductance element according to the present invention will be described with reference to FIGS. Here, a manufacturing process corresponding to the device shown in FIG. 1 is shown.
In each drawing, (a) is a plan view, (b) is its AA 'sectional view, and (c) is a BB' sectional view.

FIG. 9 shows a step of forming the patterned first insulator 3 (photoresist or polyimide) on the substrate 1.

FIG. 10 shows that all the side walls including the upper surface of the patterned first insulator 3 and the entire surface of the substrate 1 are covered with the first insulating film.
This is a step of depositing the electric conductor 4 of FIG.

In FIG. 11, the second conductor 5 is grown by electrolytic plating using the first conductor 4 as an electrode to increase the wiring thickness. However, when the first conductor 4 can be formed sufficiently thick by the sputtering method, the step of FIG. 11 is not necessary.

In FIG. 12, a patterned second insulator 6 (photoresist or the like) for a mask is formed on the second conductor 5.

In FIG. 13, unnecessary portions of the second electric conductor 5 and the first electric conductor 4 are removed by ion milling or the like using the second insulator 6 as a mask to form wiring. The second insulator 6 for the mask is removed after milling. FIG. 13 shows the case where the first insulator 3 is still left under the wiring. To increase the mechanical strength of wiring,
As described above, it is preferable to leave the first insulator 3 under the wiring. However, in order to reduce the parasitic capacitance of the wiring, it is preferable that the first insulator 3 is not provided. In that case, it may be removed by oxygen plasma treatment or the like.

When formed by the above method, a three-dimensional inductance element such as a kind of solenoid can be formed substantially in one wiring step.

Further, FIGS. 14 to 18 show how the relationship with the wiring portion is based on the shape of the first insulator used in the inductance element of FIGS. 1 to 5. The wiring of the first insulator pattern has a one-to-one pattern as shown in the figure. Therefore, by arranging the first insulator pattern in a checkerboard pattern first, it is possible to form all types of elements described above. FIG. 19 illustrates the example. Further, the pattern of the first insulator pattern has an advantage that the design can be simplified if it is a checker plate pattern in which squares are repeated in the vertical and horizontal directions, but basically, the pattern period is constant as shown in FIG. Need not be

[0026]

INDUSTRIAL APPLICABILITY The present invention is effective for forming a small and high-performance inductance element, and is effective for forming a small and high-performance transformer or filter using the same and for downsizing an MMIC.

[Brief description of drawings]

1A and 1B show a first embodiment of an inductance element according to the present invention, FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line AA ′.

FIG. 2 is a second embodiment of the device according to the present invention, (a) is a plan view, (b) is a sectional view taken along line AA ′, and (c) is B-.
It is a B'sectional view.

FIG. 3 is a third embodiment of the device according to the present invention, (a) is a plan view, (b) is a sectional view taken along line AA ′, and (c) is B-.
It is a B'sectional view.

FIG. 4 is a fourth embodiment of the device according to the present invention, (a) is a plan view, (b) is a sectional view taken along line AA ′, and (c) is B-.
B'sectional view, (d) is EE 'sectional view, (e) is F-
It is a F'sectional view.

5A and 5B show a fifth embodiment of the device according to the present invention, wherein FIG. 5A is a plan view, FIG. 5B is a sectional view taken along line AA ′, and FIG.
B'sectional view, (d) is EE 'sectional view, (e) is F-
It is a F'sectional view.

FIG. 6 is a plan view of an embodiment of the spiral inductance element according to the present invention.

FIG. 7 is a plan view showing an example of a transformer formed by using the element according to the present invention.

FIG. 8 is a plan view showing another example of a transformer formed by using the element according to the present invention.

9A and 9B show a first step of a process of manufacturing an element according to the present invention, in which FIG. 9A is a plan view and FIG.
(C) is an EE 'sectional view.

FIG. 10 is a diagram showing a second step of the manufacturing process.

FIG. 11 is a diagram showing a third step of the manufacturing process.

FIG. 12 is a diagram showing a fourth step of the manufacturing process.

FIG. 13 is a diagram showing a fifth (final) process of the manufacturing process.

14 is a diagram showing the relationship between the first insulating pattern and the wiring of FIG. 1 in the process of manufacturing the device according to the present invention.

FIG. 15 is a diagram showing the relationship between the first insulator pattern and the wiring of FIG. 2 in the manufacturing process.

16 is a diagram showing the relationship between the first insulator pattern and the wiring of FIG. 3 in the manufacturing process.

FIG. 17 is a diagram showing the relationship between the first insulator pattern and the wiring of FIG. 4 in the manufacturing process.

FIG. 18 is a diagram showing the relationship between the first insulator pattern in the manufacturing process and the wiring in FIG. 5;

19 (a), (b), (c), (d), and (e) are plan views showing the relationship between the first insulator and the wiring in the manufacturing process of the element according to the present invention.

20 (a) and 20 (b) are plan views showing various first pine pattern-shaped first insulator patterns, respectively.

21A and 21B show a conventional meandering inductance element, in which FIG. 21A is a plan view and FIG. 21B is a sectional view taken along line AA ′.

22A and 22B are plan views of a conventional concave-convex inductance element, respectively.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Electrical conductor wiring 3 ... 1st insulator 4 ... 1st electrical conductor 5 ... 2nd electrical conductor 6 ... 2nd insulator

Claims (3)

[Claims] 1. In an inductance element arranged on a substrate of a semiconductor integrated circuit, electric conductor wirings constituting the element are arranged by being repeatedly bent so as to be uneven in a direction perpendicular to a substrate surface, and An inductance element characterized in that the bottom surface of the bottom of the concave wiring is adhered to the substrate, and the convex wiring floats above the substrate and holds a spatial expansion region between the convex wiring and the substrate surface. 2. A method of manufacturing an inductance element arranged on a substrate of a semiconductor integrated circuit, comprising the steps of: (a) arranging irregularities made of a first insulator on the substrate in a striped pattern or a stripe pattern; A step of patterning a part of the first insulator to form a combined pattern; and (b) a step of depositing an electric conductor to a predetermined thickness on the side wall of the first insulator and the entire surface of the substrate by a sputtering method. (C) A step of patterning and adhering the second insulator on the conductor film so that the inductance element wiring to be formed has the same plane pattern as the plane pattern seen from above. ) Using the second insulator as a mask, a portion of the conductive film that is not covered by the mask is removed by etching, and then the remaining first and second insulators are removed. Comprising Preparation of the inductance element characterized. 3. A method of manufacturing an inductance element arranged on a substrate of a semiconductor integrated circuit, comprising: (a) forming unevenness made of a first insulator on the substrate in a striped pattern, a stripe pattern or a part thereof or A step of patterning and forming a part of them into a combined pattern; (b) a step of depositing a first conductive film on the side wall of the first insulator and the entire surface of the substrate by sputtering. (C) a step of growing a second electric conductor film having a predetermined thickness on the first electric conductor film by an electrolytic plating method using the first electric conductor film as an electrode; and (d) the second electric conductor film. And (2) a step of patterning and attaching the second insulator on the electric conductor film in such a manner that the inductance element wiring to be formed has the same plane pattern as that seen from above. The first and second insulators are used as a mask. A step of etching away a portion of the conductor film that is not covered by the mask, and thereafter removing the remaining first and second insulators. Manufacturing method.