JPH05135599A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To separately output for normal and spare decoder and address data from an address buffer circuit and to supply prescribed control signals to the address buffer circuit from the spare decoder which is in a spare memory cell selection condition so that when a faulty address is inputted, normal decoder address data become the data which make it unable to select a normal memory cell. CONSTITUTION:Buffer stages 51, 52, 21 and 22 are provided for spare and normal memory cells. Between the output terminals of the buffer stages 21 and 22 and a power supply VC, control MOSFET M53 and M54 are correspondingly provided, a control signal E is provided for each gate, control MOSFETM53 and M54 are correspondingly provided between current pull in side MOSFETE4 and E5 of the buffer stages 21 and 22 and a VS power supply and each gate is given the inverse of the control signal E, (in the figure a bar is shown on the top). By each of these control signals, the outputs of the buffer stages 21 and 22 are made in phase when a faulty address is inputted and a normal memory cell is not selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device integrated into a circuit, and more particularly to a memory device having a redundancy function which can be set to a spare memory cell and repaired when a normal memory cell is defective. Regarding

[0002]

2. Description of the Related Art Recently, in a semiconductor memory device, a normal memory cell and a spare memory cell are formed in advance, and if a defect occurs in the normal memory cell at the time of manufacture, this defective memory cell Many have a redundancy function that can be set so that the cell portion is replaced with a spare memory cell for use. This is a problem for the entire memory even if there is a defective cell of only 1 bit in a regular memory cell, and such a memory device is discarded as a defective product.

However, as the memory capacity increases, the probability of defective cells is increasing, and the cost of the product is extremely high if the defective memory device is discarded. Will be. Therefore, in order to improve the overall yield, a spare memory cell is formed, and if a part of the normal memory cell is defective, it is set to be used by switching to the spare memory cell. The method has been adopted.

FIG. 5 shows a main part of a semiconductor memory device in which the regular memory cell 1 and the spare memory cell 2 are formed as described above. 3 is address data input a
i (i = 0 to n) is applied to the address buffer 3. From the address buffer 3, a pair of address data Ai and Ai- having the same phase and opposite phase (inversion level) to the address data input ai (directly above Is output to the regular decoder 4 and the spare decoder 5.

The decode output of the normal decoder 4 is given to the normal memory cell 1, and by this decode output, one memory cell in the normal memory cell 1 (in the case of a 1-bit output type memory device) or a plurality of memory cells is provided. Memory cell (for example, in the case of an 8-bit output type memory device) is selected, and then data is stored in or read from the selected memory cell. Further, the decoding operation of the regular decoder 4 is controlled (inhibited) by the output from the spare decoder 5.

The decode output of the spare decoder 5 is applied to the spare memory cell 2, the memory cell in the spare memory cell 2 is selected by this decode output, and then the data is stored in the selected memory cell. Or read. The output of the spare decoder 5 is given as a signal for controlling the decoding operation of the regular decoder 4 as described above.

That is, in the semiconductor memory device having the above-mentioned structure, if the normal memory cell 1 has no defective bit, only the normal decoder 4 operates to access the memory cell in the normal memory cell 1. .. On the other hand, when there is a defective bit in the normal memory cell 1, the spare decoder 5 is programmed in advance so that the decoded output corresponding to the row address or the column address of the row including the defective bit is obtained.

Therefore, when the output corresponding to the row address or the column address including the defective bit of the normal memory cell 1 is obtained in the address buffer 3, the spare decoder 5 selects the memory cell in the spare memory cell 2. To be done. Further, the decoding output of the spare decoder 5 at this time stops the decoding operation of the normal decoder 4, and the normal memory cell 1 is not accessed. By such an operation, the defective portion in the regular memory cell 1 is replaced with the spare memory cell 2.

FIG. 6 is a circuit showing an example of the address buffer 3 of FIG. 5, and such circuits are provided as many as the number of address data inputs ai. M _{1 to} M ₅ , D _{1 to} D ₃ ,
E _{1 to} E ₆ are, for example, N-channel MOS FETs, respectively.
(Insulated gate field effect transistor), of which M _{1 to} M ₅ have a threshold voltage near 0 v,
D _{1 to} D ₃ are depletion (D) types, and E _{1 to} E ₆ are enhancement (E) types. And MOS FE
T M ₄ and E _{4 form} a buffer stage 21, and MOS FETs M ₅ and E _{5 form} a buffer stage 22.

Further, Vc and Vs are power sources, for example, + 5v, 0v, a signal CE and its inverted signal CE, respectively.
-(There is a bar right above in the figure) controls the selection of semiconductor memory chips.
When it is at “0” level, it becomes a chip selection command and “0”,
When the level is "1", the chip is not selected.

Therefore, when the chip is in the selected state, the circuit is in the operating state, and based on the address data input ai, a pair of address data Ai, Ai in-phase and in anti-phase with ai.
-Is generated, and the pair of decoders Ai and Ai- are output to the regular decoder and the spare decoder, respectively. On the other hand, when the chip is in the non-selected state, the circuit is in the non-operating state and serves to reduce the current flowing through the circuit.

FIG. 7 shows an example of the spare decoder 5 of FIG. 5, in which 30i is a defective address storage circuit for storing a defective address, 31 is a spare decoder circuit, and 32 is availability of a spare decoder (decoding operation). This is a preliminary decoder control circuit for controlling whether or not).

The memory circuit 30i is provided by the logarithm (the number of i) of a set of address data Ai, Ai-, and E ₇
~ E ₁₀ is E type, D ₄ is D type N channel MOS FET, F
Reference numeral ₁ is a polysilicon fuse (hereinafter abbreviated as poly fuse), and the output signal Ci serves as an address input of the preliminary decoder circuit 31.

When the address data input ai = "1" represents a defective address, Ai = "1", Ai- =
Regarding the memory circuit 30i (“1”) to which “0” is input, the polyfuse F ₁ is blown in advance by laser light or the like.

In this way, even if the power supply Vc is turned on during use, the gate potentials of the MOS FETs E ₈ and E ₉ do not rise, so they remain cut off, and the gate potential of the MOS FET E ₁₀ rises to Vc. Then, it is turned on and the Ai- input outputs as the signal Ci.

Therefore, when the ai input becomes a defective address, Ai = "0", that is, Ci = "0" is output. When the ai input is other than the defective address, Ai is "1" and C
i becomes "1".

On the other hand, the address data ai = "0"
Indicates a defective address, Ai = "0", Ai- =
The memory circuit 30i (“0”) to which “1” is input is left as it is without cutting the poly fuse F ₁ .

In this way, when the power supply Vc is turned on during use, the MOS FETs E ₈ and E ₉ are turned on, and the MOS F E
ETE ₁₀ is turned off and the Ai input outputs as signal Ci. Therefore, if the ai input becomes a defective address, Ai =
When "0", that is, Ci = "0" is output and the ai input is other than the defective address, Ai is "1" and Ci is "1".

In other words, if defective address data is written by determining whether or not to disconnect the poly fuse F ₁ of the memory circuit 30i as described above, all the output signals Ci when the address data input ai is a defective address. Becomes "0", and at other than the defective address, at least one of the memory circuits 30i becomes Ci = "1".

On the other hand, the preliminary decoder control circuit 32 includes N-channel E-type MOS FETs E _{11 to} E ₁₃ and D, respectively.
Type MOS FETs D ₅ and D ₆ and a poly fuse F _{2. When} there is no defective cell in the regular memory cell and the spare memory cell is not used, the poly fuse F ₂ is not cut and the defective cell is Therefore, when the spare memory cell is used, the poly fuse F ₂ is cut beforehand.

Therefore, if the poly fuse F ₂ is cut off, when the power supply Vc is turned on during use, the MOS FET E
₁₂ is turned off, and the MOS FETs E ₁₃ and E ₁₁ are turned on and "0" is output as the control signal P.

On the other hand, if the polyfuse F ₂ is not cut off, when the power source Vc is turned on during use, the MOS is turned on.
The FET E ₁₂ is turned on, the MOS FETs E ₁₃ and E ₁₁ are turned off, and the control signal P becomes "1".

On the other hand, the spare decoder circuit 31 includes N-channel E-type MOS FETs E _{14 to} E ₁₇ , Ei, D-type MOS FETs D ₇ and D _8, and a MOS near the threshold voltage 0v.
Consists FET M _6, M ₇ Prefecture, adapted to decode the signals Ci input from the memory circuit 30i to the gates of the MOS FET Ei. In this case, the control signal P is input to control the decoding operation, and the chip selection signals CE and CE- are input, and the Cis are all "0", P = "0", CE = "". 1 ", CE- =" 0 "is decoded at the time of, MOS FET M ₇ of the final output stage, E ₁₇
The output signal R of the driving circuit 33 is "1", and the output signal R is "0" at the time of input other than the above.

That is, the selected state of the memory chip (CE =
In "1", CE- = "0"), when the control signal P is "1", the output signal R becomes "0" regardless of the Ci input, and at this time, the spare memory cell is not selected. As will be described later, a regular decoder selects a regular memory cell.

On the other hand, when the control signal P is "0" in the selected state of the chip, the output signal R is determined by the combination of the signal levels of Ci, and C
The output signal R becomes "1" only when all of i are "0" (when the address data input ai is a defective address), and at this time, a spare memory cell is selected and the signal R = "1". As described later, the decoding operation of the regular decoder is prohibited and the decoded output becomes "0", so that the regular memory cell is not selected.

FIG. 8 shows a part of an example of the regular decoder 4 of FIG. 5, where E _{18 to} E ₂₁ and EAi are E.
Type, D ₉ and D ₁₀ are D type, and M ₈ and M ₉ have a threshold voltage of 0.
It is an N channel MOS FET near v. MOS FET E above
To each gate of Ai, all combinations of address data Ai and Ai-inputs are given as decode inputs, and there are as many regular decoders 4 of FIG. 8 as this combination.
The control signal R from the spare decoder is input to the gate of the MOS FET E ₁₈ for inhibiting the decoding operation for the decoding input. In addition, the final output stage MOS FET
M ₉ and E ₂₁ are circuits 41 for selectively driving regular memory cells
Is formed.

Therefore, the selected state of the chip (CE =
When "1", CE- = "0") and all of the decode inputs are "0", if the control signal R is "0", the decode operation is performed normally, and the output of the drive circuit 41 is output. Becomes "1" and a regular memory cell is selected.

On the other hand, in the above case, when the address data input ai is a defective address and the control signal R becomes "1" as described above, the decoding operation inhibition control is performed.
The MOSFET E ₁₈ is turned on and the decoding operation is stopped,
Since the output of the drive circuit 41 becomes "0", a regular memory cell cannot be selected.

By the way, in the conventional regular decoder as described above, the MOS FET for controlling the inhibition of the decoding operation by the control signal R from the spare decoder is used.
(E _{18 in} FIG. 8) is required. Since this regular decoder is required for each row or each column of regular memory cells, the number of MOS FETs E _{18 is} as many as the number of rows or columns in which regular memory cells are arranged. Become.

Further, wiring for passing the control signal R on the regular decoder is also required. Therefore, an extra area on the chip necessary to form a regular decoder is required.

Moreover, the final output stage MOS of the spare decoder is
As the load of the FETs (M ₇ and E _{17 in} FIG. 7), the MOS FETs provided in the number of rows or columns of regular memory cells are further provided on the load capacity of the spare memory cells as described above.
Load capacity of the E ₁₈ is also added. Therefore, the drive capability of the final output stage MOS FET of the spare decoder must be made larger than that of the normal decoder final output stage MOS FET, and the occupied area on the chip increases accordingly.

[0032]

As described above, the conventional technique has a drawback that the occupied area of the circuit for inhibiting the decoding operation is large.

The present invention has been made in consideration of the above circumstances, and an object thereof is to occupy a regular decoder because a decoding operation prohibition control input element of the regular decoder and its input wiring are unnecessary. It is an object of the present invention to provide a semiconductor memory device which can reduce the area, can form the drive capability of the final output stage element of the spare decoder to be equal to that of the normal decoder, and can reduce the occupied area of the spare decoder.

[0034]

A semiconductor memory device of the present invention includes a normal memory cell, a spare memory cell for relieving a defective memory cell in the normal memory cell, and the normal memory cell. A regular decoder connected to the memory cell for selecting the memory cell corresponding to the address input, and a spare decoder for selecting the spare memory cell corresponding to the address input when the spare memory cell is used. A decoder, a first signal transmission path for supplying an input signal to the regular decoder, and an input signal to the regular decoder on the first signal path, which is electrically equivalent to When a second signal transmission path supplied as an input signal and an address for selecting the spare memory cell are input, the normal data transmission path in the first signal transmission path is input. By outputting a control signal for setting at least one of the input signals supplied to the over da to a logic level which the memory cells of the normal is not selected by the regular decoder from said spare decoder,
And a control unit for preventing the normal memory cell from being selected while the spare memory cell is selected.

[0035]

According to the present invention, when the spare memory cell is not selected, the normal decoder normally selects the normal memory cell, but when the spare memory cell is not selected, the signal supplied to the normal decoder is the normal memory cell. By providing the control means for setting the logic level which cannot be selected, the element for the decoding operation prohibition control input of the regular decoder and the wiring to the element are not required, so that the occupied area of the regular decoder can be small. ..

The decoding operation prohibition control input MO is also provided.
Since the number of S FETs is the same as the number of regular decoders, that is, the number of rows or columns of memory cells, the load capacitance is very large, and a spare decoder drives the above-mentioned decoding operation inhibition control input MOS FETs. Since it does not need to be provided, its driving capability may be equivalent to that of a regular decoder, and its occupied area may be small.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

1 to 4 are address buffers formed in one embodiment of the semiconductor memory device of the present invention.
A portion of the spare and regular decoders are shown. The address buffer of FIG. 1 is different from the address buffer described above with reference to FIG. 6 in N channel E-type MO.
S FET E ₅₁ and MOS FET M ₅₁ whose threshold voltage is near 0v
And a buffer stage 52 composed of an E-type MOS FET E ₅₂ and a MOS FET M ₅₂ having a threshold voltage near 0 v are added to the buffer stage 51. 22 and one set of buffer stages 5
The output of the address data Ai ', Ai'- of 1,52 (the bar right above in the figure) is a spare memory cell (2 in FIG. 5).
To the normal memory cell (1 in FIG. 5), and the address data Ai, Ai- (the bar right above in the figure) of the remaining one set of buffer stages 21 and 22 is input to the normal memory cell. The control MOS FETs M ₅₃ and M ₅₄ having an N channel and a threshold voltage near 0 V are provided between the output terminals of the memory cell buffer stages 21 and 22 and the power supply Vc, respectively. A control signal E is applied to the gates of the FETs M ₅₃ and M ₅₄ , and an N-channel enhancement type control MOS is provided between the current-sink-side MOS FETs E ₄ and E _{5 of the} buffer stages 21 and 22 and the Vs power supply. FETs E ₅₃ and E ₅₄ are provided correspondingly, and a control signal E- (a bar right above in the figure) which is an inverted signal of the control signal E is given to each gate of the MOS FETs E ₅₃ and E ₅₄ . It is a thing. Other Figure 1
In FIG. 6, those parts which are the same as those corresponding parts in FIG. 6 are designated by the same reference numerals, and a description thereof will be omitted.

The spare decoder of FIG. 2 is different from the spare decoder described with reference to FIG. 7 in that the N-channel E-type MOS FET E ₆₁ and the MOS FET having a threshold voltage near 0 v are provided.
A buffer stage 61 made up of M ₆₁ and a buffer stage _{62 made up} of an E-type MOS FET E ₆₂ and a MOS FET M ₆₂ whose threshold voltage is near 0 v are added, and these buffer stages 61, 62 are connected.
The input signals and the output signal of the MOS FET E ₁₆ are driven in opposite phases to obtain the control signals E and E-output,
The difference is that the driving capability of the final output stage (buffer) of the MOS FETs M ₉ and E ₂₁ is made equal to that of a regular decoder, and other parts in FIG. The description is omitted.

The regular decoder, a portion of which is shown in FIG.
Compared with the regular decoder described above with reference to FIG. 8, the decoding operation inhibition control MOS FET E ₁₈ is omitted, and accordingly, its input wiring is omitted. The same parts as 8 are designated by the same reference numerals and the description thereof will be omitted.

Next, the characteristic part of the operation of the memory of the present invention based on the difference in the above configuration will be described. Normally, the control signals E and E- outputs of the spare decoder are "0" and "1", and the buffer stages 21 and 22 of the address buffer are
Since the MOS FETs E ₅₃ and E ₅₄ are turned on, the address data Ai and Ai- are output as usual, and the normal memory cell is selected by the normal decoder.

On the other hand, when the address data input ai becomes a defective address, it is decoded by the spare decoder and the control signals E, E- of its buffer stages 61, 62 are inputted.
The outputs are "1" and "0", which causes the buffer stages 21 and 22 of the address buffer to have MOS FETs E ₅₃ and E _54.
Is turned off and the MOS FETs M ₅₃ and M ₅₄ are completely turned on, so that both Ai and Ai- are in phase with "1". Therefore, the decode inputs of the regular decoders do not all satisfy the decoding satisfaction condition of "0", and the regular memory cells are not selected.

FIG. 4 shows a modification of the address buffer of FIG. 1, in which the threshold voltage is 0 in the N channel between the output terminal of the buffer stage 21 and the power supply Vc, which is similar to that of FIG.
Control MOS FETs M ₈₁ and M ₈₂ near v are provided in series, and a MOS FET is similarly provided between the output end of the buffer stage 22 and the power supply Vc.
M ₈₃ and M ₈₄ are provided in series, and the control signal E- is given to the gates of one of the MOS FETs M ₈₁ and M ₈₃ , and the control signal E is given to the gates of the other MOS FETs M ₈₂ and M _84. M ₈₁ , M
_The address data Ai and Ai- are taken out from the connection point _{82 and} the connection points M ₈₃ and M _{84. In} FIG. 4, the same parts as in FIG. Is omitted. In the address buffer of FIG. 4 as well, similar to the configuration of the address buffer described above, when the control signals E and E-inputs are "0" and "1", the normal operation is performed and the control signal E and E-inputs are input. When is "1" or "0", both Ai and Ai- outputs are in phase with "1".

That is, the semiconductor memory device described above is
When the address buffer circuit outputs the normal decoder address data Ai, Ai- and the spare decoder address data Ai ', Ai-' separately, and the defective address is input to the spare decoder in the spare memory cell selected state. , The spare decoder outputs the address buffer control signals E and E- separately from the spare memory cell drive signal so that the normal decoder address data Ai and Ai- output from the address buffer circuit are in phase with each other. It is controlled by the address buffer control signals E and E-.

Therefore, when the spare memory cell is not selected, the normal decoder normally selects the normal memory cell. However, when the spare memory cell is selected, the combination of the in-phase address data Ai and Ai- is supplied to the normal decoder. Since it is input, decoding is not performed and a regular memory cell is not selected.

As a result, the decode operation prohibition control input MOS FET of the regular decoder and the wiring to it are not required, so that the area occupied by the regular decoder can be reduced.
Moreover, the final output stage MOS FET of the spare decoder does not have to drive the above-mentioned decoding operation prohibition control input MOS FET, and its drive capability is the final output stage MOS FET of the regular decoder.
It can be similar to that of T, and it occupies a small area.

[0047]

As described above, according to the present invention,
The decoding operation prohibition control input element of the regular decoder and its input wiring are not required, and the occupied area of the regular decoder can be reduced, and the drive capacity of the final output element of the spare decoder is made equal to that of the regular decoder. It is possible to provide a semiconductor memory device in which the area occupied by the spare decoder can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an address buffer which is a main part of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a spare decoder which is a main part of the present invention.

FIG. 3 is a circuit diagram showing a partial configuration of a regular decoder which is a main part of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a modified example of FIG.

FIG. 5 is a block diagram showing a main part of a conventional semiconductor memory device having a redundancy function.

FIG. 6 is a circuit diagram showing an example of the address buffer of FIG. 5 taken out.

FIG. 7 is a circuit diagram showing an example of the spare decoder of FIG. 5 taken out.

FIG. 8 is a circuit diagram showing an example of the regular decoder of FIG. 5 taken out.

[Explanation of symbols]

1 ... Regular memory cell, 2 ... Spare memory cell, 3 ... Address buffer, 4 ... Regular decoder, 5 ... Spare decoder, 51, 52.61, 62, ... Buffer stage, M ₅₃ ,
M ₅₄ , E ₅₃ , E ₅₄ , M _{81 to} M ₈₄ ... Control MOS FET.

Claims (1)

[Claims] 1. A normal memory cell, a spare memory cell for relieving a defective memory cell in the normal memory cell, and the memory cell connected to the normal memory cell and corresponding to an address input. A normal decoder for selecting a memory cell, a spare decoder for selecting the spare memory cell corresponding to the address input when the spare memory cell is used, and an input signal to the normal decoder are provided. A first signal transmission path for supplying the first signal transmission path;
The second signal transmission path electrically equivalent to the input signal to the regular decoder on the signal path and supplied as the input signal of the spare decoder, and the address to which the spare memory cell is selected are input. A control for setting at least one of the input signals supplied to the regular decoder in the first signal transmission path to a logic level at which the regular memory cell is not selected by the regular decoder. A semiconductor memory device comprising: a control unit configured to select the spare memory cell and prevent the normal memory cell from being selected by outputting a signal from the spare decoder.