JPH05134820A - Information processor - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide an information processing apparatus in which a hard disk device can be mounted in a slot common to an IC card. [Structure] When a card (20) equipped with a hard disk device (25) is mounted on an information processing device (10), I / O
Since the O card interface is converted into the hard disk interface and accessed, data can be easily written in and read from the hard disk device (25).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an IC memory card and an I
The present invention relates to an information processing device (hereinafter referred to as a personal computer) in which any one of the / O cards can be mounted in a common IC card slot for use.

[0002]

2. Description of the Related Art Some conventional personal computers have an IC card slot. In particular, many portable notebook computers have a type that uses a lightweight IC memory card instead of a heavy floppy disk device. By the way, the IC card slot is
Since it has only a memory card interface, it was not possible to directly attach an input / output device other than an IC memory card to this slot. Part of JEIDA Ve
r3 standard IC memory card interface
There was an O-accessible interface, but this too was unsuitable for actually using an input / output device because there was no interrupt signal. So, in recent personal computers, IC
Memory card interface and JEIDA Ver4.
A product having an IC card slot having any of the I / O card interfaces of the standards 1 or later and capable of mounting an input / output device other than an IC memory card has been commercialized. When an input / output device other than an IC memory card is attached to such a personal computer, first the attribute memory provided in the card attached by the IC memory card interface is accessed, and the attached card is read from this attribute memory. When it is determined that the input / output device is other than the memory card, the subsequent access interface is switched to the I / O card interface. By this process, input / output devices other than the memory can be used. J
The EIDA Ver4.1 standard corresponds to the standard PCMCIA in the United States.

[0003]

By the way, the miniaturization of the hard disk drive has made it possible to manufacture a hard disk drive which can be directly inserted into a slot of an IC card. But,
The interface of the hard disk device is the I / O described above.
Since it is different from the card interface, even if the hard disk device is directly attached to the IC card slot, it cannot be operated. In addition, there is a problem that it cannot be mounted as it is because it is thicker than the IC card. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide an information processing apparatus capable of operating by directly mounting a hard disk device in a slot of an IC card.

[0004]

In order to solve the above-mentioned problems, the information processing apparatus of the present invention has a hard disk device mounted in an IC card slot that can be accessed by any interface of an IC memory card and an I / O card. When a card is installed, direct access is possible by matching the I / O card interface with the hard disk interface.

[0005]

According to the information processing apparatus of the present invention, when a card equipped with a hard disk device is installed, the I / O card interface is converted into a hard disk interface for access, so that data can be written in or read from the hard disk device. Can be done easily.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the information processing apparatus of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a connection state between a personal computer 10 and a hard disk card 20 in which a hard disk is mounted. As shown in the figure, the personal computer 10 has a switch 11 for switching between an IC memory card interface circuit and an I / O card interface circuit, a CE1 signal indicating that the address for accessing the I / O register is an even byte, and an odd number. A signal generation circuit 12 that generates a CE2 signal that indicates a byte and a connector unit 13 that connects to the hard disk card 20 are provided. To the hard disk card 20, a connection portion 21 for connecting to the connector portion 13 of the personal computer 10, a switch 22 for switching between an IC memory card interface circuit and an I / O card interface circuit, and a CE1 signal and a CE2 signal are input. I /
A conversion circuit 23 for converting into a CS0 signal indicating 1F0H to 1F7H and a CS1 signal indicating 3F0H to 3F7H in the O address space, and a RESET signal from the personal computer 10 is input to make the pulse width of the RESET signal constant (25 μs).
Conversion circuit 2 for converting to the extended HDRESET signal
4 and a hard disk device 25 which is a large-capacity storage medium
And an attribute memory 26 in which the attribute data of the hard disk card 20 is stored. The appearance of the personal computer 10 and the hard disk card 20 is shown in the perspective view of FIG. The figure shows a state in which the hard disk cards 20 are inserted into the vertically stacked two-stage slots 14. That is, at present, there is a limit to miniaturization of the hard disk device 25, and it is impossible to store the hard disk device 25 in the housing of the IC card. For this reason, a bulge occurs at the upper part, and this part is accommodated in the upper slot. That is, FIG.
As shown in (a), normally two IC memory cards 30,
As shown in FIG. 3B, one hard disk card 20 is inserted into the slot 14 into which 31 can be inserted.

Next, the operation of this embodiment will be described.
In the initial state of the personal computer 10 and the hard disk card 20, both the switch 11 and the switch 22 are IC memory card interfaces. PC 10
Reads the data of the attribute memory 26 and obtains the attribute data of the hard disk card 20. From this attribute data, the personal computer 10 side recognizes that the connected device is the hard disk card 20, and switches both the switch 11 and the switch 22 to the circuit side of the I / O card interface. After this switching, I /
The conversion circuit 23 converts a part of the signal of the O card interface,
The data is converted at 24, and the hard disk device 25 can be controlled by the converted signal. The access to the I / O register in the input / output device having the I / O card interface is performed by the CE1 signal, the CE2 signal, the address, and the IO.
RD signal (I / O read) or IOWR signal (I / O
Light). The CE1 signal is "L" (low level) when accessing an even byte, and the CE2 signal is "L" when accessing an odd byte. Normally, when an I / O address space is used, CE
1 signal and CE2 signal are set to "L", the address at this time is decoded, one of a plurality of I / O registers is selected, and the desired I / O register is selected by using the IORD signal and IOWR signal. Access. CE1
As for the signal and the CE2 signal, the CE1 signal must be set to "L" at an even byte of the address of the I / O register, and the CE2 signal must be set to "L" at an odd byte. Assuming that the hard disk device having the AT interface, which is one of the specifications of the hard disk device, is used as it is, the addresses of the I / O registers used in the hard disk device 25 are 1F0H to 1F7H and 3F0H to 3F7H.
Therefore, the addresses of the even bytes that set the CE1 signal to “L” are 1F0H, 1F2H, 1F4H, 1F6H,
3F0H, 3F2H, 3F4H, 3F6H, CE
The address of the odd byte that makes 2 signals "L" is 1F1
H, 1F3H, 1F5H, 1F7H, 3F1H, 3F3
H, 3F5H and 3F7H. Address (A0 to A15)
The following is a table of the relationship between and the CE1 signal and the CE2 signal.

[0008]

[Table 1]

From this table, a signal generation circuit 1 for inputting addresses (A0 to A15) and generating CE1 and CE2 signals.
2 can be configured. A circuit diagram of this signal generation circuit 12 is shown in FIG.
It shows in (a). As shown in the figure, in the signal generation circuit 12, the NOR circuit 121 with 7 inputs calculates the logical product of the inverted inputs of the input signals A3 and A10 to A15 and gives the AND to the AND circuit 122.
That is, when these input signals are all "L" (low level), the NOR circuit 121 outputs "H" (high level) signals. Also, 5 inputs AND
The circuit 123 ANDs the input signals A4 to A8
It is given to the D circuit 122. That is, when these input signals are all "H", the AND circuit 123 outputs a signal of "H". The AND circuit 122 takes the logical product of such input signals and supplies them to the NAND circuit 124 and the NAND circuit 125. Further, the input signal A0 is input to the NAND circuit 124, and the inverting input is input to the NAND circuit 125.
Give to each. Input these signals and
The circuit 125 outputs the CE1 signal, and the NAND circuit 124 outputs the CE2 signal.

On the other hand, the hard disk device 25 has a CS
0 (chip select 0) and CS1 (chip select 1)
, And these signals are different I / O
Register space 1F0H to 1F7H and 3F0H to 3F7H
Is specified. That is, the I / O register space is 1F0
The CS0 signal must be "L" when H to 1F7H, and the CS1 signal must be "L" when the I / O register space is 3F0H to 3F7H. The I / O register in the hard disk device 25 can be accessed from these signals, the address, the IORD signal, and the IOWR signal. The designation of even bytes and odd bytes of the I / O register in the hard disk device 25 is performed by the address signal A0, and the CE1 signal and the CE2 signal are not referred to. Therefore, in this embodiment, the CE1 signal,
The CE2 signal is converted by the conversion circuit 23, and the CS0 signal and the C0 signal are converted.
The S1 signal is being generated. FIG. 4 is a circuit diagram of the conversion circuit 23.
It shows in (b). From the figure, the NAND circuit 231 is CE1.
Signal and inverted input of CE2 signal
It is given to the D circuit 232 and the NAND circuit 233. Further, the input signal A9 is input to the NAND circuit 232 and the inverting input is input to NAN.
It is given to each D circuit 233. By inputting these signals, the NAND circuit 233 outputs the CS0 signal to the NAND
The circuit 232 outputs the CS1 signal, respectively. By using the CS0 signal and the CS1 signal generated by the conversion circuit 23, the personal computer 10 to the hard disk device 25
Can be accessed. In the above embodiment, A
Since this is a conversion process for a T-compatible hard disk device, since a hard disk device having an interface of other specifications has a different address, another conversion circuit is required, but the method is the same.

Since the RESET signal in the I / O card interface signal is narrower than the pulse width required by the hard disk device 25, the conversion circuit 24 converts it into an HDRESET signal having a constant pulse width (25 μs). Must. A circuit diagram of the conversion circuit 24 is shown in FIG. As shown in the figure, the RESET signal is given as an input to the delay one-shot circuit 241 and the NOR circuit 242. The one-shot circuit 241 generates a pulse of "H" for a certain period of time from the rising edge of the input signal and outputs the pulse to the NOR circuit 242. Further, the inverted output of the one-shot circuit 241 is given to the personal computer 10 as an RDY / BSY signal. While the "H" pulse width of the input signal is being widened by the one-shot circuit 241, the RDY / of "L" /
Since the BSY signal is given to the personal computer 10, the personal computer 10 recognizes that the hard disk card 20 is busy. In other words, the hard disk card 20 is in the reset state during this period, so the personal computer 10 prohibits access to the hard disk card 20. NO
The R circuit 242 calculates the logical sum of the output signal from the one-shot circuit 241 and the RESET signal,
Output as T signal. RESET signal and HDRESE
The relationship with the T signal is shown in the waveform diagram of FIG. From the figure, it can be seen that an HDRESET signal having a pulse width of about 25 μs is generated from a RESET signal having a pulse width shorter than 25 μs.

Next, the comparison between the IC memory card 30 and the hard disk card 20 will be described with reference to FIGS. 6A and 6B are cross-sectional views of the IC memory card 30 and the hard disk card 20. As shown in FIG. 6A, the IC memory card 30 has a stainless steel cover plate 30.
1, 302 and a card frame 303 are used as a housing, and a printed circuit board 304 is provided inside. Memory ICs 305 to 310 are provided on both surfaces of the printed circuit board 304. To connect the IC memory card 30 and the connector portion 13, one end of the printed board 304 is connected to the connector pin 13
It is sandwiched by 1. Further, as shown in FIG. 6B, the hard disk card 20 includes the stainless steel cover plates 201 and 202 and the card frame 203 as a housing, and the printed circuit board 20 is provided inside.
4 and further includes the hard disk main body 26 on the printed circuit board 204. Printed circuit board 20
The ROM 4 includes ROMs 205 to 207, and stores a drive controller and an I / O card interface. FIG. 7 is an exploded view of the IC memory card 30. As shown in the figure, the IC memory card includes a stainless steel cover plate 301 and a printed circuit board 3 on which the memory IC is mounted.
04, card frame 303, and cover plate 30 made of stainless steel
2 and the connector 13 can be disassembled. FIG. 8 is an exploded view of the hard disk card 20.
From the figure, the hard disk card 20 includes a stainless steel cover plate 202, a hard disk body 26, and a ROM.
The printed circuit board 204 on which the above are mounted, and the card frame 20
3, it can be disassembled into the stainless cover plate 201 and the connector 13.

Next, application examples of the present invention will be described with reference to FIGS.
4 will be described. FIG. 9 is a perspective view showing the configuration of a personal computer 50 having three slots 51. From the figure, the personal computer 50 has three vertically stacked slots 51.
Is provided. This slot usually has 3 ICs
A card can be installed, but the IC memory card 30
It is also possible to mount the hard disk card 20 by using the middle tier and the lower tier. The mounting position may be reversed. That is, the hard disk card 20 may be mounted using the upper and middle layers, and the IC memory card 30 may be mounted in the lower layer. Further, the slots may be provided in two stages, the opening of the upper stage may be widened upward to accommodate the convex portion of the hard disk card 20, and the IC memory card 30 may be mounted in the lower stage and the hard disk card 20 in the upper stage. It should be noted that the number of slots 51 formed in three stages is merely an example, and the number of slots may be four or more. In this case, the number of combinations of IC cards and hard disk cards that can be mounted is extremely large. FIG. 10 shows the sockets 52 and 5 of the three-stage slot 51.
It is sectional drawing which shows the shape of 3,54. From the figure, each socket is provided with a convex stopper 52a, 53a, 54a and a concave stopper 52b, 53b, 54b. Since these stoppers are provided, they do not shift from each other even when stacking a plurality of slots. FIG. 11 shows a three-tiered slot 51.
FIG. 27 is an external view showing the arrangement of the eject switches 55 to 57 for taking out the IC memory card 30 and the like when using. As can be seen from FIG. 11A, the interrupted eject switch 56 is replaced by the upper and lower eject switches 5.
The operability of each of the eject switches is improved by providing the eject switches at positions opposite to the positions of 5 and 57. Also,
FIG. 11B shows a mechanism for inhibiting the IC memory card 30 or the hard disk card 20 from being inserted in the slot 51 when the IC card is inserted into the slot 51. As shown in the figure, IC
A groove 30 is formed in the upper half of one side surface of the memory card 30 or the hard disk card 20 and in the center of the other side surface.
a and 39b are provided, and protrusions 51a and 51b are provided at the corresponding positions of the slot 51. Then, at the time of insertion, the groove 30a and the protrusion 51a, and the groove 30b and the protrusion 5
Since the 1b meshes with each other, only the insertion in this direction is allowed. 12 to 14 are diagrams comparing the interface of the IC memory card and the interface of the I / O card. The points in the figure are 2 to 5 in the Notes column.
The terminals marked with must be used as independent terminals, but the other terminals can be connected in parallel. That is, if the slots are vertically stacked, the connecting line becomes more complicated, but the terminals that can be connected in parallel need only be the common connecting line, and the complexity is reduced. The terminals that can be connected in parallel are 1-6, 8-15,
17, 19-32, 34, 35, 37-41
No. 43, 46-51, 53-57, 64-66
52 terminals of No. 68 and No. 68. However, it is desirable that these terminals are also independent, and whether or not they are connected in parallel is not an issue of the present invention.

In this embodiment, the hard disk card 20 equipped with the hard disk device 25 has been described, but other media other than the hard disk device 25,
For example, optical disk device, floppy disk device, R
The present invention can be similarly applied to a card equipped with an AM disk device or the like.

[0015]

According to the information processing apparatus of the present invention, it is possible to easily write data to and read data from a hard disk device even when a card equipped with the hard disk device is mounted. Therefore, even an information processing device having only a slot for an IC card can be equipped with a hard disk device which is a large-capacity external storage device.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus of this embodiment.

FIG. 2 is a perspective view showing the outer appearance of the information processing apparatus of this embodiment.

FIG. 3 is a perspective view showing insertion into the information processing apparatus of this embodiment.

FIG. 4 is a circuit diagram of a signal generation circuit.

FIG. 5 is a circuit diagram of a conversion circuit.

FIG. 6 is a cross-sectional view of an IC card and a hard disk card.

FIG. 7 is an exploded view of an IC card.

FIG. 8 is an exploded view of a hard disk card.

FIG. 9 is a perspective view showing a configuration of an information processing device.

FIG. 10 is a sectional view showing the shape of a socket.

FIG. 11 is an external view showing the arrangement of eject switches.

FIG. 12 is a comparison diagram of interfaces of an IC card and an I / O card.

FIG. 13 is a comparison diagram of interfaces of an IC card and an I / O card.

FIG. 14 is a comparison diagram of interfaces of an IC card and an I / O card.

[Explanation of symbols]

10 ... Personal computer, 11 ... Switch, 12 ... Signal generating circuit, 13 ... Connector part, 20 ... Hard disk card,
21 ... Connection part, 22 ... Switch, 23 ... Conversion circuit, 24
... conversion circuit, 25 ... hard disk device, 26 ... attribute memory

Claims (4)

[Claims] 1. An information processing apparatus having an IC card slot capable of accessing an IC memory card interface and an I / O card interface of the JEIDA Ver4.1 or later standard, the signal of the I / O card interface is converted to a hard disk interface. Thus, an information processing device, characterized in that a card having a hard disk device is mounted in the slot. 2. The information processing apparatus according to claim 1, wherein converting the signal from the I / O card interface to the hard disk interface includes a process of extending the width of the reset signal by a constant interval. 3. When converting a signal from an I / O card interface to a hard disk interface, two types of signals that respectively specify an even-byte byte space and an odd-byte address space, and two types that specify a continuous logical address space are used. The information processing apparatus according to claim 1, further comprising a process of converting the signal into the signal. 4. The information processing apparatus according to claim 1, wherein an optical disk device, a floppy disk device or a RAM disk device is used instead of the hard disk device.