JPH0513384A - Formation of fine pattern - Google Patents

Abstract

PURPOSE:To provide the title formation method capable of pattern formation not exceeding the resolution limit. CONSTITUTION:The title formation method is composed of the steps enumerated as follows, i.e., after the formation of a resistor 2 on a semiconductor substrate 1, the specific parts of the resist 2 are exposed to form a silylated layers 4a and then the resist 2 excluding the silylated layers 4a is halfway etched away and after depositing a CVD film on the resist 2 and the silylated layers 4a, the CVD film is etched back and then the resist 2 is etched away until the semiconductor substrate 1 is exposed using the residual CVD film on the silylated layer side wall as a mask 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine pattern in an LSI manufacturing process.

[0002]

2. Description of the Related Art Conventionally, photolithography technology has been positioned as an important basic technology for advancing the miniaturization of patterns required for devices in response to the progress of higher integration of VLSI. The higher resolution in photolithography is due to the progress of both the reduction optical system of the optical stepper and the higher resolution of the positive resist material and process.

However, in the prior art, it was not possible to form a pattern below the resolution limit of the exposure apparatus.

[0004]

As described above, according to the conventional technique, it is not possible to form a pattern below the resolution limit of the exposure apparatus, and further miniaturization cannot be achieved.
In view of the above points, an object of the present invention is to provide a method capable of forming a pattern below the resolution limit toward the miniaturization of a pattern in a device.

[0005]

Means for Solving the Problems A method for forming a fine pattern according to the present invention comprises: forming a resist on a semiconductor substrate;
A predetermined portion of the resist is exposed, and then a silylated layer is formed on the exposed resist portion, and then the resist excluding the silylated layer is partially etched, and then CVD is performed on the resist and the silylated layer. The method is characterized in that after the film is deposited, the CVD film is etched back, and then the resist is etched until the semiconductor substrate is exposed using the CVD film remaining on the side wall of the silylated layer as a mask. .

[0006]

The silylated resist, that is, the silylated layer has high heat resistance and its heat resistance limit is 300 ° C. On the other hand, since etching is performed using CVD whose heat resistance limit is lower than 300 ° C. Due to the difference, a deposit is formed on the sidewall of the silylated layer. Further, since the resist is etched using this deposit as a mask, a fine pattern below the resolution limit can be formed.

[0007]

Embodiments FIGS. 1 and 2 are schematic sectional views showing an embodiment of the present invention over time. A description will be given below with reference to these drawings. First, a resist 2 is formed on the surface of the semiconductor substrate 1.
After applying, pre-baking is performed. The film thickness of this resist 2 is about 2 μm. The film thickness changes due to subsequent processing of the underlying film and the like [FIG. 1 (a)].

Next, the pattern on the mask 3 is transferred onto the semiconductor substrate 1 by exposing it to light [FIG. 1 (b)],
After that, HDMS [Hexamethyldisilazane 4 <(CH ₃ ) ₃ S
i-NH-Si (CH ₃ ) ₃ >] etc.
A rich silylated layer 4a is formed. This silylated layer 4
a has a high heat resistance, and its heat resistance limit temperature is 300 ° C. The heating temperature of the baking for silylation performed in this step is about 150 to 200 ° C. [FIG.
(C)].

Next, the resist 2 is etched in plasma such as O ₂ . In this step, the resist 2
Etching is stopped in the middle of the resist 2 because the side wall of is used. The etching amount at this time is about 0.5 μm [FIG. 1 (d)]. Then, a low temperature plasma SiN film 5 is deposited on the surface of the substrate [FIG. 2 (a)]. Then C
Etch back in plasma such as F ₄ + O ₂ [Fig. 2
(B)].

Finally, the resist 2 is etched by using the SiN film 5 remaining on the side wall of the resist 2 as a mask. In this case, a gas such as CF ₄ + O ₂ is used so that the selection ratio of the silylated layer and the unsilylated resist 2 to the SiN film 5 can be selected.

[0011]

As described above, according to the present invention, since it is possible to form a fine pattern below the resolution limit, high integration of VLSI can be promoted and mass production for submicron devices can be achieved. It greatly contributes to the achievement of the process and the construction of the pattern forming technology in the half micron region.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an embodiment of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

[Explanation of symbols]

 1 ... Semiconductor substrate 2 ... Resist 3 ... Mask 4 ... HDMS 4a ... Silylation layer 5 ... SiN

Claims (1)

Claims: 1. After forming a resist on a semiconductor substrate,
A predetermined portion of the resist is exposed, and then a silylated layer is formed on the exposed resist portion, and then the resist excluding the silylated layer is partially etched, and then CVD is performed on the resist and the silylated layer. A method for forming a fine pattern, which comprises a step of etching back the CVD film after the film is deposited, and then etching the resist until the semiconductor substrate is exposed, using the CVD film remaining on the side wall of the silylated layer as a mask.