JPH0513379A - Dry etching method - Google Patents

Abstract

PURPOSE:To attain to the rapidity, high selectivity, low pollution level and low damage degree to an underneath silicon base material in the anisotropical dry etching step of a SiO2 base material layer. CONSTITUTION:The title etching method is divided into two phases, i.e., in the first step, about 90% of the layer thickness of a SiO2 interlayer insulating film 3 is removed using a non-carbon base non-deposit fluorine compound such as SF6 or NF3 and then in the second step, the residual about 10% is removed using S2F2/H2 mixed gas. Furthermore, in the first step, the rapid etching work is made feasible using SFx<+>, NFx<+>, etc., in large mass capable of mass production. At this time, the etching step is stopped before the underneath material layer is exposed neither causing any damage nor any carbon pollution at all to an impurity diffused region 2. On the other hand, in the second step, the high selectivity to said material layer meeting the requirements for the high S/F ratio can be attained. Furthermore, the deposited S can be sublimated to be removed by heating step causing no pollution at all.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied in the field of manufacturing semiconductor devices, and in particular, it suppresses the occurrence of contamination and damage to the underlying silicon-based material layer, and also has high speed and high selectivity. On how to achieve.

[0002]

In recent years the VLSI, with the progress of high integration and performance of semiconductor devices, as seen in ULSI or the like, the dry etching method of the silicon compound layer represented by silicon oxide (SiO ₂₎ The technical requirements are becoming more and more severe. First, the area of device / chip is increasing due to high integration, the diameter of the wafer is increasing, the pattern to be formed is highly miniaturized, and uniform processing within the wafer surface is required.
The mainstream of the dry etching apparatus is shifting from the conventional batch type to the single-wafer type because of the demand for high-mix low-volume production represented by IC. At this time, in order to maintain the same productivity as in the past, it is essential to greatly improve the etching rate. In addition, in order to speed up and miniaturize the device, the junction depth of the impurity diffusion region becomes shallow, and various material layers are thinned. Etching technology with less energy consumption is required. For example, an impurity diffusion region formed in a semiconductor substrate, a source of a PMOS transistor used as a resistance load element of SRAM,
An example is etching of a SiO ₂ interlayer insulating film, which is performed using a silicon substrate or a polycrystalline silicon layer as a base when a contact is to be formed in a drain region or the like. However, requirements such as high speed, high selectivity, low contamination, low damage, etc. are in a relationship of being neglected, and it is extremely difficult to establish an etching process that can satisfy all of them.

Conventionally, CHF ₃ , CF ₄ / H has been used to dry-etch a silicon compound layer typified by a SiO ₂ layer while maintaining a high selection ratio with respect to a silicon-based material layer.
₂ mixed systems, CF ₄ / O ₂ mixed systems, C ₂ F ₆ / CHF ₃ mixed systems, etc. have typically been used as etching gases. All of these are mainly composed of fluorocarbon-based gas having a C / F ratio (ratio of the number of C atoms in the molecule to the number of F atoms) of 0.25 or more. These gas systems are used because (a) the C contained in the fluorocarbon gas is Si.
O ₂ layer surface to produce a C-O bond, there is work to weaken or cleave SiO bond, CF _x ⁺ (especially x = 3 which is the main etching species (b) SiO ₂ layer, 4) can be produced, and (c) a relatively carbon-rich state is created in the plasma, so that oxygen in SiO ₂ is removed in the form of CO or CO ₂ , while C, which is contained in the gas system, Due to the contribution of H, F, etc., the carbon-based polymer is deposited on the surface of the silicon-based material layer, and the etching rate decreases,
It is based on the reason that a high selection ratio with respect to the silicon-based material layer can be obtained. The concept of C / F ratio and the above etching mechanism are described in J. Vac. Sci. Tech. , 16
(2), 1979, p391 for details. The above H
Additive gases such as ₂ , O _{2 and the} like are used for the purpose of controlling the selection ratio, and can reduce or increase the F ^* generation amount, respectively. That is, it has the effect of controlling the apparent C / F ratio of the etching reaction system.

On the other hand, the inventor of the present invention makes sulfur play the role of carbon in the conventional etching of the SiO ₂ -based material layer, and performs low-temperature etching to obtain high selectivity, low contamination and high anisotropy. Japanese Patent Application No. 2-19804
No. 5 specification. This is because the substrate to be etched (wafer) is cooled to 0 ° C. or below, and S ₂ F ₂ , SF
_This is a method of etching a SiO ₂ based material layer using an etching gas containing sulfur fluoride such as ₂ , SF ₄ , S ₂ F ₁₀ . The sulfur fluoride has a mechanism that assists the radical reaction by F ^* to ions such as SF _x ^+.
The iO ₂ based material layer is etched. Also, these sulfur fluorides have a large S / F ratio (ratio of the number of S atoms in the molecule to the number of F atoms), which is different from SF ₆ which is the best known so far even with the same sulfur fluoride. Free S can be generated in the plasma. This S is SiO
_On the surface of the ₂ type material layer, O atoms are extracted and removed in the form of SO _x , but on the Si type material layer, they are deposited and the etching rate is significantly reduced, so that a high selection ratio is achieved. Further, S deposited on the side wall portion of the pattern in which vertical incidence of ions does not occur in principle plays a role of protecting the side wall and contributes to anisotropic processing. Deposited S can either sublimed by heating the wafer after etching, or O ₂
It can be burnt at the same time when the resist mask is removed by plasma ashing and does not cause any particle contamination.

[0005]

As described above, the SiO ₂
Etching of the system material layer is performed based on a mechanism mainly composed of ion-assisted reaction, and a process using a fluorocarbon system gas has already been introduced into a mass production line. However, as is clear from the above mechanism, in the conventional process, the constituent elements of the etching gas are accelerated in the form of ions and implanted into the underlying silicon substrate,
There is an inherent escape from problems such as pollution and damage. For contamination or damage when a fluorocarbon-based gas is used as an etching gas, see IEDM.
Digest Paper, p336 (1979). That is, residual carbon-based polymer and C
Contamination with C atoms occurs on the surface or inside of the Si substrate due to the implantation of F _x ⁺ ions, and the C atoms serve as nuclei to cause lattice defects. Also,
Physical damage is also caused by the ion bombardment itself. In this way, the surface layer of the silicon substrate is contaminated /
A damaged layer is formed. Jpn. J. Appl. Phy
s. , 20, p803 (1981).
It has been reported that the removal of the damaged layer minimizes adverse effects on the electrical characteristics of the device. Therefore,
In the conventional process, so-called light etching is generally performed after the etching of the SiO ₂ -based material layer is completed to remove the surface layer portion of the Si substrate.

However, as the junction depth of the impurity diffusion region becomes shallower as in recent years, the amount of Si substrate removed by the above-mentioned light etching reaches a non-negligible level, and in some cases, the range of contamination and damage is affected. There is also a concern that the junction depth will be exceeded. On the other hand, in the process using sulfur fluoride that the present inventor previously proposed, the deposited S
Can be easily and completely removed by sublimation by heating the wafer.
In other words, the fact that no contamination is left on the surface of the silicon substrate is a great advantage over the process using the conventional carbon-based polymer. Moreover, it is an extremely excellent measure against CFCs. However, on the other hand, since the above-mentioned sulfur fluoride has a low generation efficiency of the etching species of the SiO ₂ based material layer, there is a concern that it may be disadvantageous from the viewpoint of the etching rate. this is,
Since sulfur fluoride having a large S / F ratio naturally has a small number of F atoms in the molecule, even if ions of the SF _x ⁺ form are generated by discharge dissociation, only ions with a small x value can be obtained. Because. For example, in the case of S ₂ F ₂ which is considered to be the most practical among the above-mentioned sulfur fluoride, the ions that can be generated are almost only SF ⁺ (x = 1). Moreover, all of the above four types of sulfur fluoride are relatively unstable as compared with SF _6, and easily dissociate into S and F ^* in the plasma, so the amount of SF _x ⁺ produced is much smaller. Become. Considering that single-wafer processing for large-diameter wafers will become the mainstream in the future, the shortage of etching rate is a problem that must be solved by all means. Therefore, it is an object of the present invention to provide a method capable of suppressing the occurrence of contamination or damage to a base in etching a SiO ₂ -based material layer and achieving high speed and high selectivity.

[0007]

A dry etching method according to the present invention is proposed to achieve the above object. That is, the dry etching method according to the first invention of the present application uses an etching gas containing a non-depositing fluorine-based compound containing no carbon as a constituent element while controlling the temperature of the substrate to be etched to be room temperature or lower. The first step of etching the SiO ₂ -based material layer in a range that does not substantially exceed the layer thickness, and S ₂ F ₂ , SF ₂ , SF while controlling the temperature of the substrate to be etched below room temperature.
_The SiO ₂ -based material layer using an etching gas containing at least one sulfur fluoride selected from ₄ , S ₂ F ₁₀ and at least one compound selected from H ₂ , H ₂ S and silane compounds Second etching the rest of the
And the steps of.

Further, the dry etching method according to the second invention of the present application is characterized in that at least one of SF ₆ and NF ₃ is used as the non-depositing fluorine-based compound.

[0009]

In the present invention, the etching of the SiO ₂ -based material layer is performed in two stages, and in the first step, an etching gas containing a non-depositable fluorine-based compound containing no carbon as a constituent element is used. The non-depositing fluorine compound is generally 1
It is a highly volatile compound having a relatively large number of F atoms in the molecule. This compound produces polyatomic ions in plasma when dissociated by discharge, and many polyatomic ions are contained in the polyatomic ions. For example, ions such as SF ₃ ⁺ , SF ₄ ⁺ , and SF ₅ ⁺ are generated from SF ₆ by discharge dissociation. Since these ions have a larger mass than SF ⁺ generated from S ₂ F ₂ , for example, the sputtering effect is large. Moreover, since SF ₆ does not dissociate into 6 F ^{* s} and free S in a one-step reaction, it is also excellent in the generation efficiency of the above ions. Therefore, high speed etching becomes possible. When NF ₃ is used, mainly NF ₂ ⁺ can be efficiently produced. Also,
The non-depositable fluorine-based compound does not generate CF _x ⁺ because it does not contain carbon as a constituent element. Therefore, the present invention can essentially avoid contamination and damage due to C atoms, which has been a problem in conventional processes. Further, in the first step, the SiO ₂ -based material layer is etched within a range that does not substantially exceed the layer thickness.
In other words, the etching is temporarily stopped when the underlayer is slightly exposed or when a part of the underlayer starts to be exposed. This makes it possible to protect the base from the irradiation of a large amount of ions having a large mass existing in the plasma.

In the subsequent second step, S ₂ F ₂ , SF ₂ ,
An etching gas containing at least one kind of sulfur fluoride selected from SF ₄ and S ₂ F ₁₀ and at least one kind of compound selected from H ₂ , H ₂ S and silane compounds is used. In this mixed gas system, SF _x ⁺ generated from sulfur fluoride by discharge dissociation serves as an etching species for the SiO ₂ -based material layer. However, the production efficiency is lower than in the first step, and the value of x is also generally low.
At this time, free S simultaneously generated in the plasma forms a side wall protective film to contribute to the improvement of anisotropy, and is deposited on the surface of the silicon-based material layer to improve the selectivity to the silicon underlayer. Will also contribute. Further, H ₂ , H ₂ S, and the silane-based compound added to this sulfur fluoride have a function of increasing the apparent S / F ratio of the etching reaction system. Here, H ₂ and H ₂ S generate H ^* by discharge dissociation. Excess F ^* is captured by this H ^* to generate HF, and is removed to the outside of the system through the exhaust system of the etching apparatus, so that the S / F ratio of the etching reaction system increases. In particular, H ₂ S is also the source of S, so
The effect of increasing the S / F ratio is great. The silane compound is
Discharge dissociation produces Si ^* in addition to H ^* . Both of these radicals contribute to the trapping of F ^* and are removed to the outside of the system in the form of HF, SiF _x, etc., so that the S / F ratio can also be effectively increased. If the S / F ratio is increased in this way, it becomes a condition that S is relatively easily deposited, the side wall protection effect is enhanced, and anisotropic processing is facilitated. Further, since F ^* is relatively small, the selectivity with respect to the underlying layer made of a silicon material is improved.

In the second step, however, high speed cannot be expected because the amount of SF _x ⁺ produced from S ₂ F ₂ is small for the reasons described above. But the second
Only the remaining portion of the SiO ₂ -based material layer is etched or over-etched in the step of (1), and most of the layer thickness direction has already been removed at high speed by the high density and large mass ions in the first step. There is. Therefore,
According to the present invention, the etching can be completed in a much shorter time than the case where S ₂ F ₂ or the like is used throughout the process, and the throughput can be improved.

[0012]

EXAMPLES Specific examples of the present invention will be described below.

[0013] Example 1 This example, a second aspect of the present invention is applied to a contact hole processing, the SiO ₂ interlayer insulation film by using the SF ₆ in a first step by about 90% of a thickness After etching, the remaining about 10 using S ₂ F ₂ / H ₂ mixed gas in the _second step.
This is an example of etching%. This process will be described with reference to FIG. In this example, etching
Etching substrate (wafer) used as a sample
As shown in FIG. 1A, a SiO ₂ interlayer insulating film 3 is formed on a single crystal silicon substrate 1 in which an impurity diffusion region 2 is formed in advance, and an etching mask for the SiO ₂ interlayer insulating film is further formed. With the opening 4a as
The pattern 4 is formed. Here, the SiO ₂ interlayer insulating film 3 is formed to a thickness of about 1.0 μm by CVD, for example. The resist pattern 4 is, for example, a novolac-based positive photoresist (manufactured by Tokyo Ohka Kogyo; trade name TSMR-V).
It was formed by g-ray exposure and alkali development using 3).

This wafer was set on the wafer mounting electrode of an RF bias application type magnetic field microwave plasma etching apparatus. The wafer mounting electrode has a built-in cooling pipe, and a cooling medium such as a chiller installed outside the apparatus supplies and circulates an appropriate coolant to the cooling pipe to maintain the wafer being etched at a predetermined temperature. It is made possible. Here, ethanol was used as the coolant, and the wafer was kept at -60 ° C. In this state, as an example, SF ₆ flow rate 100 SCCM, gas pressure 1.3 Pa (10 mTorr), microwave power 8
50W, RF bias power 300W (400kHz
Under the condition of z), the SiO ₂ interlayer insulating film 3 was etched to a depth of about 0.9 μm. In this first step, the radical reaction due to F ^* generated in large quantity in the plasma by the discharge dissociation of SF ₆ is etched by a mechanism assisted by ions such as SF _x ⁺ accelerated by high RF bias power. Progressed. At this time, the decomposition product generated by sputtering the resist pattern 4 with ions formed a carbon-based polymer and deposited on the pattern side wall portion, and the first side wall protective film 5 was formed. As a result, as shown in FIG. 1B, a contact hole 3a having a vertical wall was formed halfway. The etching rate in the first step is about 0.3 μm / min, and the etching time is about 3
It was a minute, which was a sufficient value for practical use.

Next, as an example of etching conditions, S ₂ F
₂ flow rate 20 SCCM, H ₂ flow rate 50 SCCM, gas pressure 1.3 Pa (10 mTorr), microwave power 85
0W, RF bias power 50W (400kHz),
The wafer temperature was changed to −60 ° C. and about 0.1 μm of the remaining portion of the SiO ₂ interlayer insulating film 3 was etched. In this second step, the etching progressed mainly by SF ⁺ generated from S ₂ F ₂ . However, the amount of SF ⁺ produced is small. Here, since H ₂ was added to the etching gas, F ^* was captured by H ^* , and the S / F ratio of etching reactivity was increased. As a result, the etching reaction system becomes a condition in which the radical property is weakened and S is rich,
As shown in FIG. 1C, a second side wall protective film 2 mainly containing S was formed on the side wall of the pattern. Further, when the underlying impurity diffusion region 2 is exposed, S
The deposition layer 7 was formed, the etching rate was lowered, and high underlayer selectivity was obtained. Moreover, since the RF bias power is reduced, the generation of decomposition products due to the sputtering of the resist pattern 4 is extremely small, and the SF ⁺ ion incident energy is also reduced. Therefore, the impurity diffusion region 2 or the silicon substrate 1 was not contaminated or damaged due to C atoms or S atoms. The etching rate in the second step is about 0.
The time required for etching was about 2 minutes. The overall process of this example is about 0.2 μm /
A minute etch rate has been achieved.

After the etching was completed, the above wafer was transferred to a plasma ashing apparatus, and the resist pattern 4 was removed under the usual O ₂ plasma ashing conditions.
At this time, the first side wall protective film 5, the second side wall protective film 6,
The S deposition layer 7 was also removed at the same time. The mechanism of this removal is mainly based on combustion for carbon-based polymers and sublimation by burning and heating for S. Finally, as shown in FIG. 1D, it was possible to form the contact hole 3a having a good anisotropic shape without generating any particle contamination. Further, neither contamination nor damage to the impurity diffusion region 2 was observed, and therefore, light etching was unnecessary.

Embodiment 2 In this embodiment, the second invention of the present application is also applied to the processing of contact holes, and NF _{3 is used} in the first step and S ₂ F ₂ / H ₂ mixed gas is used in the second step. This is the example used. The etching sample in this embodiment is the same as that shown in FIG.
Is the same as that shown in. By setting this wafer on the wafer mounting electrode of the magnetron type RIE (reactive ion etching) device and supplying the ethanol refrigerant to the cooling pipe built in the wafer mounting electrode, the wafer temperature during etching is controlled. The temperature was maintained at -60 ° C. In this state, as an example, the NF ₃ flow rate is 100 SCC
M, gas pressure 1.3 Pa (10 mTorr), self-bias potential (V _dc ) -200 V, RF bias power 1 k
SiO ₂ interlayer insulating film 3 under the condition of W (13.56 MHz)
Was etched to a depth of about 0.9 μm. In the first step, the etching proceeds by a mechanism in which radicals of F ^* generated in a large amount from NF ₃ are assisted by ions such as NF _x ⁺ and N ⁺ , and as shown in FIG. The contact hole 3a having a square shape was formed partway. The etching rate in the first step was about 0.4 μm / minute, and the time required for etching was about 2.5 minutes.

Next, as an example, an S ₂ F ₂ flow rate of 20 SCC
M, H ₂ flow rate 50 SCCM, gas pressure 1.3 Pa (10 m
Torr), self-bias potential (V _dc ) -30V, RF
About 0.1 μm of the remaining portion of the SiO ₂ interlayer insulating film 3 was etched under the conditions of a bias power of 400 W (13.56 MHz) and a wafer temperature of −60 ° C. The etching mechanism in this second step is almost as described above in Example 1, and the contact hole 3a as shown in FIG. 1C was formed. The etching rate in the second step was about 0.05 μm / minute, and the time required for etching was about 2 minutes. An etching rate of about 0.22 μm / min was achieved in the entire process of this example. Finally, O ₂ plasma ashing is performed in the same manner as in Example 1 to remove the resist pattern 4, the first side wall protective film 5 and the second side wall protective film 6 as shown in FIG. did.

Although the present invention has been described based on the two types of embodiments, the present invention is not limited to these embodiments. For example, S other than S ₂ F ₂ described above may be used.
Almost the same result can be obtained by using F ₂ , SF ₄ , and S ₂ F ₁₀ . In addition, the etching gas used in all the steps of the present invention, sputtering effect, dilution effect,
A rare gas such as He or Ar may be appropriately added to expect a cooling effect or the like. Further, the material layer to be etched is not limited to the above-mentioned SiO ₂ , but PSG, BSG,
It may be BPSG, AsSG, AsPSG, AsBSG, or the like. Note that BF ₃ , PF _5, etc. may be considered as non-depositing fluorine-based compounds that do not contain carbon as a constituent element, but since B and P contained in these compounds serve as dopants for the silicon substrate, Not suitable for the purpose of the invention.

[0020]

As is clear from the above description, in the present invention, the dry etching of the SiO ₂ -based material layer is performed in two stages, and most of the layer thickness direction is removed by the first step which emphasizes high speed. After that, high substrate selectivity, high anisotropy, low contamination,
The residual part is removed in the second step which attaches importance to low damage. By the combination of these two steps, various requirements that were difficult to meet in the conventional dry etching method are simultaneously satisfied. Therefore, the present invention is extremely suitable for manufacturing a semiconductor device which is designed based on a fine design rule and has high integration and high performance.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to a contact hole in the order of steps, (a) showing a state where a resist pattern is formed on a SiO ₂ interlayer insulating film, (b) 6A is a state in which the SiO ₂ interlayer insulating film is etched halfway, FIG. 8C is a state in which an S deposition layer is formed on the surface of the base exposed by etching the SiO ₂ interlayer insulating film, and FIG. , The side wall protective film, and the S deposit layer are removed to complete the contact hole.

[Explanation of symbols]

1 ... Single-crystal silicon substrate 2 ... Impurity diffusion region 3 ... SiO ₂ interlayer insulating film 3a ... Contact hole 4 ... Resist pattern 4a ... Opening 5 ... First Side wall protective film 6 ... Second side wall protective film 7 ... S deposited layer

Claims (2)

[Claims] 1. A silicon oxide based material layer is substantially formed by using an etching gas containing a non-depositing fluorine-based compound containing no carbon as a constituent element while controlling the temperature of a substrate to be etched below room temperature. The first step of etching within a range not exceeding the layer thickness, and the temperature of the substrate to be etched is controlled to room temperature or below, and S
_An etching gas containing at least one kind of sulfur fluoride selected from ₂ F ₂ , SF ₂ , SF ₄ and S ₂ F ₁₀ and at least one kind of compound selected from H ₂ , H ₂ S and silane compounds is used. And a second step of etching the remaining portion of the silicon oxide based material layer using the dry etching method. 2. The non-depositing fluorine-based compound is S
The dry etching method according to claim 1, wherein at least one of F ₆ and NF ₃ is used.