JPH05127870A - Data processor - Google Patents

Abstract

PURPOSE:To suppress the increase of the data processing time and also the increase of the program size by setting a register at the specific value and switching the register used for execution of an instruction after the specific value is set for the register. CONSTITUTION:A flag register 1 is usueally set at 0, and a 1st gate 21 and a 2nd gate 22 are turned off and on with the outputs (a) and (b) set at 0 and 1 respectively. At the same time, an accumulator A 3 is selected. This state is kept as it is until the set value of the register 1 is changed. Meanwhile the register 1 is set at 1 when the accumulator A 3 is switched. Then the gates 21 and 22 are turned on and off with the outputs (a) and (b) set at 1 and 0 respectively together with selection of an accumulator B 4. This state is kept as it is until the set value of the register 1 is changed. Under such conditions, a single step is provided to set the flag value end a register can be designated for execution of the instructions after the step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device which selectively uses a plurality of registers by switching them.

[0002]

2. Description of the Related Art An instruction to a data processing device is composed of an operation code (hereinafter abbreviated as an operation code) indicating the type of instruction and an operand indicating an address or the like in a memory to be processed.

For example, the instruction format of an operation using an accumulator which is a register for operation is a one-address instruction format having one operand, and the data is stored between the data and the operand of the accumulator which has been moved from the memory in advance. The operation is performed and the result is placed in the accumulator.

Therefore, as a method of selecting an accumulator used for an operation in a data processing device having a plurality of accumulators, a method of newly providing an instruction having two or more operands can be considered. To avoid an increase in the number of sets, a program is created in which an accumulator switching instruction made up of already-provided instructions is placed before an arithmetic instruction, and the accumulator is switched as necessary.

FIG. 1 is a conceptual diagram of accumulator switching in a conventional data processor having two accumulators, and in the case of only operation instructions consisting of an opcode and one operand as shown in FIG. 1 (a). 1 uses the accumulator A, and as shown in FIG. 1B, when the accumulator switching instruction (1) and the operation instruction (2) are set, the accumulator A is switched to the accumulator B.

[0006]

As described above, in the conventional data processor, every time the accumulator B is used,
Since the switching instruction must be executed before the arithmetic instruction, there is a problem that the data processing time increases and the program size increases.

The present invention has been made to solve such a problem, and sets a value for specifying a register to be used, and automatically switches a register after setting to a register specified by the value. Thus, an object of the present invention is to provide a data processing device that suppresses an increase in data processing time and an increase in program size due to register switching.

[0008]

A data processing apparatus according to the present invention selectively uses a plurality of registers by switching to a register specified by a set value when executing an instruction after setting a value specifying the register once. It is characterized by doing.

[0009]

In the data processing apparatus according to the present invention, when a value specifying a register is set in the storage section, the register specified by the value set in the storage section is selected and used in the subsequent data processing.

[0010]

The present invention will be described below with reference to the drawings showing the embodiments thereof. FIG. 2 is a block diagram showing the configuration of the data processing device according to the present invention. In the figure, 1 is a flag register for storing a value that specifies the accumulator, and holds the current value until the value is set next time. The switching circuit 2 switches the accumulator used for the calculation between the two accumulators (A) 3 and (B) 4 according to the value stored in the flag register 1.

The flag register 1 has a first MO of the switching circuit 2.
The S-FET21 and the second MOS-FET22 via an inverting circuit are connected in parallel, and the first MOS-FET21 has an accumulator.
(A) 3 and accumulator (B) on the second MOS-FET 22
4 is connected.

A register switching operation in the data processing apparatus having the above configuration will be described. Normally, "0" is set in the flag register 1, the output "a" is "0", the first gate 21 is turned off, and the output "b" is "1".
Then, the second gate 22 is turned on, the accumulator (A) 3 is selected, and this state is held until the set value of the flag register 1 changes.

When switching the accumulator,
The flag register 1 is set to "1", the output "a" is "1" and the first gate 21 is turned on, the output "b" is "0" and the second gate 22 is turned off and the accumulator (B) 4 Is selected, and this state is held until the set value of the flag register 1 changes.

As described above, in the program of the data processing apparatus according to the present invention, the step of setting the flag value is 1
The registers used for executing the instructions after this step can be specified only by providing the steps, so that the enlargement of the program size and the increase of the data processing time can be suppressed.

In this embodiment, 2 is set depending on the value of the flag.
The configuration for switching individual registers has been described, but 2
It is also possible to adopt a configuration in which one register is selected from three or more registers by using a value of bits or more, and the same effect as this embodiment can be obtained.

Further, in this embodiment, one register is selected from a plurality of registers.
Although the configuration for selecting one register has been described, the configuration may be such that a predetermined combination of register groups is selected from a plurality of registers, and the same effect as that of the present embodiment can be obtained.

Needless to say, in the case of these other embodiments, the switching circuit must have a circuit configuration corresponding to each of them.

[0018]

As described above, the data processing apparatus according to the present invention switches the register used for executing the instruction after the setting by setting the value specifying the register, so that the plurality of registers are selectively used. This has an excellent effect of suppressing an increase in data processing time and an increase in program size in the configuration.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of accumulator switching in a conventional data processing device.

FIG. 2 is a block diagram showing a configuration of a data processing device according to the present invention.

[Explanation of symbols]

 1 Flag register 2 Switching circuit 3 Accumulator A 4 Accumulator B

Claims (1)

[Claims] 1. A device for processing data by selectively using a plurality of registers, a storage unit for storing a value for specifying a predetermined register, a unit for storing the value of the predetermined register in the storage unit, And a means for processing data using a register whose value stored in the storage section is specified.