JPH05126906A - Storing medium analyzing device - Google Patents

Abstract

PURPOSE:To obtain an inexpensive semiconductor storage element analyzing device which uses an inexpensive low-speed displaying means, can arbitrarily change its analyzing speed and analyzing interval, and can perform analyses in real time. CONSTITUTION:When a coincidence comparator 11 discriminates that an address signal 2a generated by means of an adder 16 which adds the contents of an offset address register 14 and ring counter 15 to each other in a repeated stage while an address to be analyzed is successively changed coincides with the address to be analyzed, a register 13 obtains information required for analysis. Then, when the number of coincident times is frequency-divided by means of a frequency-divider 12, sufficient processing time can be secured and the processing interval can be changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a semiconductor memory element analyzing apparatus for analyzing a distribution state of memory element defects of a semiconductor memory element.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a general semiconductor memory element analyzing apparatus. In the figure, reference numeral 1 is a semiconductor test device having a function capable of performing a functional test of a semiconductor memory device, and 2 is one function of the configuration of the semiconductor test device, and is an algorithmic pattern of addresses and data to be input to the semiconductor memory device. Generated by the algorithmic pattern generator, 3 is the device under test whose function is to be tested, 4 is the pass / fail judgment by comparing the output from the device under test 3 with the expected value output from the algorithmic pattern generator 2. 5 is a computer for controlling each component of the semiconductor test device, 6 is a display device for displaying the test result and the defective distribution state of the semiconductor memory device, and 7 is a storage space of the device under test 3. A block selector having a function of selecting an address line for selecting an arbitrary space, and 8 indicates whether the pass / fail information output from the comparison / determination unit 4 is the address information. FIG. 4 is a timing chart showing a method for fetching a defective signal in the conventional configuration, and a defective information storage unit for storing the defective signal in the case where the block selector 7 selects addresses 0 to N. FIG.

Next, the operation will be described. The address and data generated from the algorithmic pattern generator 2 are input to the device under test 3 and the data is stored corresponding to each address. Subsequently, the address generated from the algorithmic pattern generator 2 is input to the device under test 3, and the output data and the expected value of the algorithmic pattern generator 2 are judged by the comparison and judgment device 4. The pass / fail information is stored in the defect information storage unit 8, but at this time, only the defect information of the block selected by the block selector 7 is stored within the range of addresses input to the device under test 3. That is, the defect information is stored in the storage position of the defect information storage device 8 in correspondence with the change of the address in the selected block.
Next, the information stored in the defect information storage 8 is stored in the computer 5
The program running above reads through the data bus and displays on the display device 6.

[0004]

Since the conventional semiconductor memory element analysis apparatus is configured as described above, it is possible to analyze each part of a large capacity semiconductor memory element by repeating the state setting, information collection, and display. It requires a lot of time to set conditions and accumulate information, and it takes a lot of time for analysis. Also, it takes time for the computer to read and display the memory data at the time of display. If an attempt is made to increase the available analysis space, there is a problem in that a high-speed memory for accumulating pass / fail judgment information also becomes large and the apparatus itself becomes expensive.

The present invention has been made to solve the above-mentioned problems, and it is possible to change the analysis space and the display speed easily in real time, and increase the number of expensive storage devices. It is an object of the present invention to obtain a storage medium analysis device that can analyze a large-capacity storage medium.

[0006]

A storage medium analysis apparatus according to the present invention applies, for example, a series of address signals generated from an algorithmic pattern generator of a semiconductor test apparatus to an element under test in an infinite loop state. With the access continued, the coincidence comparing means of the generated address and the analysis target address and the frequency dividing means for counting down the input of the coincidence signal by the set number of times and then outputting the coincidence signal as a capture signal It has a specifying means for sequentially specifying the addresses to be analyzed.

[0007]

In the present invention, the address generated by the algorithmic pattern generator in the test apparatus is compared with the arbitrary address designated by the designating means,
The pass / fail information is fetched only when the addresses are matched by the match / comparison means, and the frequency dividing means generates a fetch signal for permitting the reading of the information, and the reading / display is performed within the time until the next matching address is generated. Outputs for processing etc.

[0008]

【Example】

Example 1. 1 is a block diagram showing a first embodiment of the present invention. 1 to 6 are the same as those described above. Reference numeral 9 is a semiconductor memory element analyzing apparatus which is one of the configurations of the present invention, 10 is a display means for displaying the distribution state of defective elements, and 11 is an address generated by the semiconductor test apparatus 1 and the semiconductor memory element analyzing apparatus 9
A match comparator that compares a target address within the match detector to detect a match, and a match comparator 12 performs an output once when the match signal from the match comparator 11 is input a set number of times. A frequency divider that changes the interval at which signals are generated, 13 is a register (holding means) that holds pass / fail information from the comparison / determination unit 4 in the semiconductor test apparatus 1 and an address corresponding to the pass / fail information, and 14 is an analysis unit. Offset address register that holds the initial address of the range of interest, 1
5 is a ring counter which sequentially increments by 1 count up to a predetermined value and repeats the addition again from the first value when the above value is reached, 16 is the value of the offset address register 14 and the ring counter 15 Adder,
Reference numeral 17 is a register read permission signal generator for notifying that the information in the register 13 can be read on the display means 10 and permission thereof, and 18 is one of the elements constituting the display means 10 and executes an arbitrary program. A computer that can perform setting and reading of information for each functional portion of the semiconductor memory element analysis device 9, and 19 is a display means 10.
1 is a display device for displaying the distribution state of defective elements, 20 is addressing means, and 21 is output means.
FIG. 2 is a timing chart showing how the semiconductor memory element analyzing apparatus according to the present invention fetches information of cyclically generated addresses 0 to N. 2
a is an input address generated by the algorithmic pattern generator, 4a is a determination output output by the comparison / determination unit, 12a is a defect information fetch signal generated by the frequency divider 12, and 17a is a register read permission signal generator 17. Register read permission signal.

In the semiconductor memory element analyzing apparatus configured as described above, it is assumed that the algorithmic pattern generator 2 in the semiconductor testing apparatus 1 cyclically generates input addresses 0 to N beforehand, and the address signal 2a And the pass / fail signal 4a generated by the comparison / determination unit 4 are input to the semiconductor memory element analysis device 9. The semiconductor memory element analysis device 9 reads and displays the information contained therein by the display means 10, and the display means 10 can be realized by an inexpensive personal computer or the like. continue,
The semiconductor memory element analysis device 9 receives the address signal 2a generated infinitely repeatedly from the algorithmic pattern generator 2, and the offset address register 14, ring counter 15 and adder in the semiconductor memory element analysis device 9 are received. Compare with the address generated by 16. For example, when zero is written in the offset address register 14 and the ring counter 15 is at zero in the initial state, the adder 16 adds the zero and outputs zero. This zero is compared with the address signal from the algorithmic pattern generator 2 to generate a coincidence signal. Since the algorithmic pattern generator 2 infinitely repeats the scanning of the entire target memory area to generate the address signal, the same address appears with a certain interval. Next, the coincidence comparator 1
The coincidence signal generated from 1 is input to the frequency divider 12. The frequency divider 12 controls the output of the input coincidence signal to the output side, and when there is a preset number of inputs,
The match signal input to the output side is the defect information read signal 1
I will put it out as 2a. Therefore, by changing the setting of the number of times, the output interval of the coincidence signal input from the frequency divider 12 can be changed by an integral multiple of the fixed interval. The defect information fetch signal 12a obtained by dividing the input of the coincidence comparator 11 by the frequency divider 12 is input to the register 13, the ring counter 15, and the register read permission signal generator 17. When the defective information fetch signal 12a from the frequency divider 12 is generated, the register 13 holds the address generated by the algorithmic pattern generator 2 which performed the coincidence comparison and the pass / fail signal generated by the comparison / determination unit 4. The ring counter 15 increments the present numerical value by one. The register read permission signal generator 17 is the frequency divider 12
When the defect information acquisition signal 12a from
A register read permission signal 17a that prompts the display means 10 to read information is generated. When an input from the register read permission signal generator 17 is generated in the computer 18, the computer 18 reads the information held in the register 13 by the program operating in the computer 18 and displays it on the display device 19. By repeating such a series of operations, the ring counter 15 is sequentially incremented by one, so that the information held in the register 13 has the pass / fail information at that address while changing the address of interest.

In the above embodiment, an attempt is made to analyze in a semiconductor memory element analyzing apparatus having a function of displaying a distribution state of defective cells of the semiconductor memory element, which is connected to a semiconductor test apparatus for performing a functional test of the semiconductor memory element. A circuit for detecting a match between the address to be analyzed and the address of the cell being tested by the test device, a circuit for fetching the judgment information when the match is detected, and a circuit for changing the data transfer time interval to the display device. A state in which a match signal frequency divider circuit that counts match signals and creates a fetch signal and an adder circuit that changes the analysis target address are used, and the algorithmic pattern generator of the semiconductor test equipment is infinitely looped and tested repeatedly multiple times. In the above, the semiconductor memory element analysis apparatus characterized by displaying the target cells one by one has been described. Further, according to this embodiment, there is provided an inexpensive semiconductor memory element analysis device capable of analyzing a semiconductor memory element in real time, which is characterized by using a low-speed display means and capable of arbitrarily changing an analysis speed. You can get it. Further, with respect to the address signal generated in the repeated state, the coincidence comparator 11 and the ring counter 15 obtain the information necessary for the analysis while sequentially changing the address to be processed,
The configuration and the frequency divider 12 are characterized in that the display means can be notified of a sufficient processing time and the processing interval can be changed, and an inexpensive display means can be used at a low speed and an interval for obtaining analysis information. There is an effect that it is possible to obtain a semiconductor memory element analysis device that can freely change

Embodiment 2. In the first embodiment, the case where the semiconductor memory element is analyzed is shown, but any other storage medium such as a main memory, an IC card, a magnetic disk, an optical disk, a CDROM, etc. may be used as long as the storage medium has a predetermined address space. I don't care.

Embodiment 3. In the above-described first embodiment, the case where the algorithmic pattern generator is looped infinitely has been described, but it may be executed only once to make a pass / fail judgment for one address.

Embodiment 4. Although the ring counter counts up the analysis target address one by one in the first embodiment, the analysis target address to be analyzed may be input from the outside and only that address may be analyzed. It suffices if there is a specifying means for specifying.

Example 5. In the first embodiment, the register 1
3 shows the case where the defect information is held at the time when the defect information fetching signal 12a is generated, the register 13 is made to hold the defect information at the time when the coincidence signal of the coincidence comparator 11 is generated, and the defect information fetching is performed. The output means 21 may output the defect information held in the register 13 at the time when the signal 12a is generated.

[0015]

As described above, according to the present invention, since the holding of information is configured to be operated by the frequency dividing means and the coincidence comparing means, a defective information storage device is not required, the cost is low and the display speed is high. There is an effect that a device that can change the space for change and analysis in real time can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operating state of the first embodiment of the present invention.

FIG. 3 is a configuration diagram showing a conventional semiconductor memory element analysis apparatus.

FIG. 4 is a timing chart showing an operating state in the conventional semiconductor memory element analysis apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor test apparatus 2 Algorithmic pattern generator 3 Element to be measured 4 Comparison judgment device 9 Semiconductor memory element analysis device 10 Display means 11 Matching comparator (matching comparing means) 12 Divider (dividing means) 13 Register (hold) Means) 14 offset address register 15 ring counter 16 adder 17 register read permission signal generator 18 computer 19 display device 20 addressing means

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical display location G06F 11/22 310 K 9290-5B 330 B 9290-5B 350 F 9290-5B G11C 29/00 303 A 9288-5L

Claims (1)

[Claims] 1. A storage medium analysis device having the following elements: (a) a designation means for designating an analysis target address of a storage medium to be analyzed; (b) inputting analysis information obtained by analyzing the storage medium and its address; A coincidence comparison unit that detects whether the address matches the analysis target address designated by the designation unit and outputs a coincidence signal, and (c) a capture signal obtained by dividing the coincidence signal output by the coincidence comparison unit at a predetermined ratio. (D) an object to be analyzed in the storage medium from among the input analysis information based on either the coincidence signal output by at least the coincidence comparing means or the capture signal output by the frequency dividing means. Holding means for holding the analysis information of the address.