JPH0512182A - Direct memory access controller - Google Patents

Abstract

PURPOSE:To shorten the direct memory access time. CONSTITUTION:In a read mode the read address outputted from a read address counter 21 is supplied to a memory R/W control circuit 25 via a selector 30. The circuit 25 has an access to a memory 16 and reads successively plural data out of the memory 16. These read data are stored in a bidirectional register 27 via a bidirectional buffer 32. In a write mode the write address outputted from a write address counter 22 is supplied to the circuit 25 via the selector 30. The circuit 25 has an access to a memory 17 and writes the data read out of the register 27 into the memory 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller for controlling memory-to-memory direct memory access (hereinafter abbreviated as DMA) having a common address and data bus.

[0002]

2. Description of the Related Art A conventional DMA control device performs DMA as follows. That is, one data (data of a predetermined bit length) is read from one memory (transfer source), the read data is held, and the held data is written to the other memory (transfer destination). There is. This is one cycle. Therefore, when there is a plurality of data to be transferred, the DMA is performed by repeating the number of cycles equal to the required number of transfers.

[0003]

Therefore, the conventional DMA is used.
In the control device, if there are a plurality of data to be transferred, D
There is a drawback that the time required for MA becomes long.

An object of the present invention is to reduce the time required for DMA even when there are a plurality of data to be transferred.
It is to provide an A control device.

[0005]

According to the present invention, at least the address bus and the data bus are commonly connected to the transfer source and the transfer destination, and from the transfer source to the transfer destination without going through the central processing unit. DMA to transfer data
In the control device, when the central processing unit is in the hold state, a unit that sequentially reads a plurality of data from the transfer source, a unit that holds the read plurality of data, and a unit that stores the held data. A means for sequentially writing to the transfer destination is provided, and a DMA control device is obtained. Means may be included for causing the central processing unit to wait if the transfer address is accessed by the central processing unit during operation of the central processing unit. It may also include means for sequentially varying the number of data.

[0006]

A plurality of data is sequentially read from a transfer source, a plurality of read data are held, and a plurality of held data are sequentially written to a transfer destination.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a DMA controller according to an embodiment of the present invention. In the illustrated DMA control device 11, at least a first address bus AB1 and a first data bus DB1 are commonly connected to a transfer source and a transfer destination, and a central processing unit (hereinafter referred to as CPU Abbreviated) 1
Transfer data without going through 2. In this embodiment,
First and second memories 16 as a transfer source and a transfer destination
And 17. That is, one of the first and second memories 16 and 17 is the transfer source, and the other is the transfer destination. In this embodiment, the first and second memories 16 and 17 are also commonly connected to the first control bus CB1.

In this embodiment, each of the first and second memories 16 and 17 is a random access memory (RAM). Both the first and second memories 16 and 17 are dynamic RAM (DRAM), or one is DRAM and the other is static RA
M (SRAM). However, the first and second
If both of the memories 16 and 17 are SRAMs, the DMA control device 11 of this embodiment cannot be applied.

The DMA controller 11 of this embodiment has an input / output (I / O) controller 18. The I / O control unit 18
A second address bus AB2, a second data bus DB2,
And is connected to the CPU 12 via the second control bus CB2. The I / O control unit 18 is connected to the I / O device 19 and controls the I / O device 19. I / O control unit 18
Outputs a bus request signal and a ready signal to the CPU 12,
A bus confirmation signal is received from the CPU 12.

The DMA controller 11 of this embodiment has a read address counter 21 and a write address counter 22. The read address counter 21 and the write address counter 22 are connected to the CPU 12 via the second data bus DB2. The count operation of each of the read address counter 21 and the write address counter 22 is controlled by the I / O control unit 18, as described later. The read address counter 21 outputs a read address, and the write address counter 22 outputs a write address.

The DMA controller 11 can operate in either the read mode or the write mode. Whether the read mode or the write mode is used is determined by the second control bus C.
It is set by a mode control signal sent from the CPU 12 via B2.

The DMA controller 11 includes a clock generation circuit 2
Have three. The clock signal generated from the clock generation circuit 23 is supplied to the CPU 12, and the count clock control circuit 24 and the memory read / write (R /
W) It is also supplied to the control circuit 25.

The operation of the count clock control circuit 24 is controlled by the I / O control unit 18 and the memory R / W control circuit 25, as will be described later. The count clock control circuit 24 outputs the read control clock signal and the write control clock signal to the read address counter 21 and the write address counter 22, respectively. The count clock control circuit 24 also outputs a terminal control clock signal to the terminal counter 26. The terminal counter 26 counts the clock of the terminal control clock signal under the control of the I / O control unit 18. The terminal counter 26 outputs the count value.

The count clock control circuit 24 sends a shift clock signal to the bidirectional register 27. The bidirectional register 27 is an N-stage shift register. The number of register stages n used by the bidirectional register 27 (n is an integer equal to or less than N) is set in the register stage number register 28. That is, under the control of the I / O control unit 18, the register stage number register 28 is set to the register stage number n via the second data bus DB2.

The register stage number n held in the register stage number register 28 is supplied to one input of the comparator 29.
The count value of the terminal counter 26 is supplied to the other input of the comparator 29. When the register number n and the count value match, the comparator 29 outputs a match signal to the bidirectional register 27.

The memory R / W control circuit 25 is controlled by the I / O control unit 18 as described later. The memory R / W control circuit 25 is connected to the first and second memories 16 and 17 via the first address bus AB1 and the first control bus CB1. The memory R / W control circuit 25 is connected to the CPU 12 via the second address bus AB2 and the second control bus CB2.

The output (read address) of the read address counter 21 and the output (write address) of the write address counter 22 are supplied to the selector 30.
The selector 30 selects one of the read address and the write address in response to the selection signal from the memory R / W control circuit 25 and outputs the selected address. More specifically, when the I / O control unit 18 reports that the read mode is set, the memory R / W control circuit 25 causes the selector 30 to select a read address. On the contrary, when the I / O control unit 18 informs that the write mode is set, the memory R / W control circuit 25 causes the selector 30 to operate.
Select the write address for. The address selected by the selector 30 is supplied to the memory R / W control circuit 25. The memory R / W control circuit 25 uses the supplied selected address as a column address, as will be described later, via the second address bus AD2 to generate the first and second signals.
To the memories 16 and 17 of the.

The first data bus DB1 and the second data bus DB2 are connected to the first bidirectional bus 31. The first data bus DB1 is connected to the second bidirectional bus 32. The second bidirectional bus 32 is connected to the bidirectional register 26 via the internal data bus DB3.

The DMA controller of the present embodiment utilizes the page mode (nibble mode) of DRAM, which is well known in the art, to perform DMA transfer of data as will be described in detail later. By using this page mode, DMA is performed with a plurality of data reads, a plurality of data retentions, and a plurality of data writes as one cycle.

Next, the page mode will be briefly described. As is well known, in DRAM, a storage location (memory cell) is designated by a row address and a column address. In the page mode, once a row address is designated, memory cells in the same row can be successively accessed by repeatedly inputting a column address.
Therefore, the input of the row address can be omitted except at the beginning, and high-speed access is possible.

The operation of the DMA controller shown in FIG. 1 will be described below. First, I. The read mode will be explained, and then II. The write mode will be described.
In the following description, the first memory 16 is the transfer source and the second memory 17 is the transfer destination.

I. In order to set the number of data n to be transferred in the read mode, the CPU 12 outputs the number of register stages n to the second data bus DB2 and the hold control signal to the second control bus CB2. In response to this hold control signal, the register stage number register 28 holds the register stage number n. Subsequently, the CPU 12 outputs an access instruction signal instructing to read the data from the first memory 16 to the second control bus CB2. In response to this access instruction signal, the memory R / W control circuit 25
Sets the first memory 16 in a readable state via the first control bus CB1. As a result, the first memory 16
Is designated as the transfer source.

Next, the CPU 12 uses the second control bus CB2.
A mode control signal for instructing a read mode via the second data bus DB2, and an initial value of the column address via the second data bus DB2.
The row address is output via the second address bus AB2. In response to this mode control signal, the I / O controller 18
Sets an initial value to the read address counter 21, count clock control circuit 24, memory R / W control circuit 2
5 and the so-called bidirectional register 27.

As a result, the count clock control circuit 24 supplies the read control clock signal and the terminal control clock signal to the read address counter 2 respectively.
1 and output to the terminal counter 26. Further, the memory R / W control circuit 25 causes the selector 30 to select the read address as the selected address. The bidirectional register 27 is in a mode for writing data on the internal data bus DB3. Further, the memory R / W control circuit 25 sets the first bidirectional buffer 31 to the second data bus D.
The second bidirectional buffer 32 is connected to the first data bus DB so as to cut off the connection between B2 and the first data bus DB1.
1 and the internal data bus DB3 are controlled to be connected. As a result, the CPU 12 enters the hold state.

In response to the read control clock signal, the read address counter 21 counts up from the initial value and outputs the read address. This read address is supplied to the memory R / W control circuit 25 as an address selected via the selector 30. The memory R / W control circuit 25 uses the selected address as a column address, and outputs the column address and the row address supplied from the CPU 12 to the first address bus AB1 in a time division manner. As a result, the data is sequentially read from the first memory 16. Therefore, the I / O control unit 18, the read address counter 21, the count clock control circuit 24, the memory R / W
The control circuit 25 and the selector 30 constitute a unit for sequentially reading a plurality of data from the transfer source.

The plurality of read data are supplied to the bidirectional register 27 via the bidirectional buffer 32. The bidirectional register 27 holds the supplied plurality of data in response to the shift clock signal from the count clock control circuit 24. Therefore, the bidirectional register 27 functions as a means for holding a plurality of read data.

On the other hand, in response to the terminal control clock signal, the terminal counter 26 counts up and outputs the count value. This count value is equal to the number of data transferred from the first memory 16 to the bidirectional register 27. The comparator 29 compares the register stage number n set in the register stage number register 28 with the count value, and when they match, outputs a coincidence signal to the bidirectional register 27. In response to this match signal, the bidirectional register 27
Ends the writing of data. Therefore, the number of data can be sequentially changed by changing the number of register stages n set in the register stage number register 28. In other words, the combination of the terminal counter 26, the register stage number register 28, and the comparator 29 works as a means for sequentially varying the number of data.

II. The write mode CPU 12 outputs an access instruction signal for instructing writing of data to the second memory to the second control bus CB2. In response to this access instruction signal, the memory R /
The W control circuit 25 receives the second control signal via the first control bus CB1.
The memory 17 is set to the writable state. As a result, the second memory 17 is designated as the transfer destination.

Next, the CPU 12 uses the second control bus CB2.
A mode control signal for instructing the write mode via the second data bus DB2, and an initial value of the column address via the second data bus DB2.
The row address is output via the second address bus AB2. In response to this mode control signal, the I / O controller 18
Sets an initial value to the write address counter 22, and count clock control circuit 24 and memory R / W control circuit 2
5 and the so-called bidirectional register 27.

As a result, the count clock control circuit 24 supplies the write control clock signal and the terminal control clock signal to the write address counter 2 respectively.
2 and the terminal counter 26. Further, the memory R / W control circuit 25 causes the selector 30 to select the write address as the selected address. In addition, the bidirectional register 27 is in a mode for reading data onto the internal data bus DB3. Further, the memory R / W control circuit 25 sets the first bidirectional buffer 31 to the second data bus D.
The second bidirectional buffer 32 is connected to the first data bus DB so as to cut off the connection between B2 and the first data bus DB1.
1 and the internal data bus DB3 are controlled to be connected. As a result, the CPU 12 enters the hold state.

In response to the write control clock signal, the write address counter 22 counts up from the initial value and outputs the write address. This write address is supplied to the memory R / W control circuit 25 as an address selected via the selector 30. The memory R / W control circuit 25 uses the selected address as a column address, and outputs the column address and the row address supplied from the CPU 12 to the first address bus AB1 in a time division manner. On the other hand, in synchronization with this, the plurality of data held therein are read from the bidirectional register 27 in response to the shift clock signal from the count clock control circuit 24, and the second bidirectional buffer 32 is read. Via the first data bus DB1. As a result, the data on the first data bus DB1 is sequentially written to the second memory 17. Therefore, the I / O controller 18 and the write address counter 2
2, the count clock control circuit 24, the memory R / W control circuit 25, and the selector 30 constitute a unit for sequentially writing a plurality of data to the transfer destination.

With the above, one cycle of DMA is completed. Therefore, a plurality of data can be DMA-transferred from the transfer source to the transfer destination at one time. As a result, the time required for DMA can be shortened.

It is assumed that the CPU accesses the transfer address during the DMA transfer. In this case, the I / O controller 18 does not send the ready signal to the CPU 12 until the DMA transfer is completed. Therefore, the CPU 12 is in a wait state.

[0034]

As described above, according to the present invention, a plurality of data can be DMA-transferred at one time, so that the time required for DMA can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a DMA controller according to an embodiment of the present invention.

[Explanation of symbols] 11 DMA controller 12 CPU 16,17 memory 18 I / O controller 19 I / O device 21 Read address counter 22 Write address counter 23 Clock generation circuit 24 count clock control circuit 25 Memory R / W control circuit 26 Terminal Counter 27 Bidirectional register 28-register stage number register 29 comparator 30 selector 31,32 bidirectional buffer

Claims (3)

[Claims] 1. A direct memory access control device, wherein at least an address bus and a data bus are commonly connected to a transfer source and a transfer destination, and data is transferred from the transfer source to the transfer destination without going through a central processing unit. , A means for sequentially reading a plurality of data from the transfer source when the central processing unit is in a hold state, a means for holding the plurality of read data, and a means for holding the plurality of held data And a means for sequentially writing to the direct memory access control device. 2. The direct memory access control device according to claim 1, further comprising means for waiting said central processing unit if said transfer address is accessed by said central processing unit during operation of said central processing unit. 3. The direct memory access control device according to claim 1, further comprising means for varying the number of data sequentially.