JPH0512110A - Information processing equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize high-speed parallel execution of instructions in an information processing device having a two-level cache between a central processing unit and a main memory. A central processing unit (CPU) 1 for sending a logical address for memory access to two address buses 6 and 8 in parallel, and a cache (L) of the first and second layers
1, L2-CACHE) 4, 5 are provided with address translators (MMUa, MMUb) 2, 3 for translation from logical addresses to physical addresses. L1
-When access to CACHE4 is missed, the address to L1-CACHE4 is transferred to L2-CACHE5 through bus selector 10. High-speed parallel execution of two consecutive load instructions becomes possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a central processing unit capable of executing a plurality of instructions in parallel and a plurality of hierarchical caches.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an example of a conventional information processing apparatus having a two-level cache between a central processing unit and a main memory (not shown). In the figure, 1
01 is a central processing unit (C which can execute two instructions in parallel).
PU), 103 is a first-level cache (L1-CACHE) located near the CPU 101 and in an upper level, and 104 is L
It is a second layer cache (L2-CACHE) located below 1-CACHE 103. However, the access speed is higher in L1-CACHE 103, and the storage capacity is larger in L2-CACHE 104. Also, 102
Is an address translation unit (MMU) for passing a physical address to L1-CACHE 103, 105 and 107 are address buses, 106 and 108 are data buses, and 109 is L.
1-A miss hit signal line for notifying the CPU 101 when the access to the 1-CACHE 103 is missed.

The L1-CACHE 103 employs a write-through type coherency protocol. The write-through method is a coherency protocol for guaranteeing the consistency of data between caches in multiple layers. That is, in the case of this example, L1-
When the data in CACHE 103 is updated by a store instruction or the like, the data in L2-CACHE 104 having the same address as the data updated in L1-CACHE 103 is also updated at the same time.

In the information processing apparatus of FIG. 7, when the CPU 101 executes a load instruction requiring memory access, the memory address of the data to be loaded is sent from the CPU 101 to the address bus 105 as a logical address, A part of the logical address on the address bus 105 is converted into a physical address by the MMU 102, and L1-CAC is combined with the remaining part of the logical address.
HE 103 is accessed. When the access hits, data is fetched from the L1-CACHE 103 to the CPU 101 through the data bus 106. Further, when a mistake is made in accessing L1-CACHE 103, the same address as the address of the data accessing L1-CACHE 103 is L1, L2.
-L2-C through the address bus 107 between CACHE
Passed to ACHE104, and its L2-CACHE104
From the data bus 108, 106, desired data is fetched into the CPU 101. In addition, L2-CACHE
If 104 also makes a mistake, the data is fetched from the main memory, but the structure for that is not shown.

FIG. 8 is a block diagram showing the internal structure of the CPU 101 in FIG. In FIG. 8, 111 is an instruction buffer (IB) for holding a plurality of instructions to be sequentially executed, 112 is a first instruction decoder (DECa) for decoding the instruction fetched from the IB 111, 11
3 is a second instruction decoder (DECb) for decoding the next instruction also fetched from the IB 111, and 114 is D
First for executing instructions decoded by ECa112
Of the second arithmetic unit (ALUa) 115 for executing the instruction decoded by the DECb 113.
b), 116 is a register file (RF) including 32 registers r0 to r31, 117 is an address selector, and 118 is a control circuit (CTRL) for switching the address selector 117. 119 and 120 are fetch signal lines, 121 and 122 are decode signal lines, 123 and 124 are signal lines for address or data transmission, 125 is a selection signal line from the CTRL 118 to the address selector 117, and 126 and 127 are A signal line for transmitting data from the RF 116 to the ALUa 114 and the ALUb 115. The address bus 105 is at the output side of the address selector 117, the data bus 106 is at RF 116, and the mishit signal line 109 is at C.
Each is connected to the TRL 118. Even when the address selector 117 is switched to the ALUb 115 side, when the CTRL 118 receives a signal indicating that the access to the L1-CACHE 103 is missed through the mishit signal line 109, the CTRL 11
8 is switched to the ALUa 114 side.

Next, the operation of the conventional information processing apparatus having the above configuration will be described with reference to FIGS. 9 and 10.

FIG. 9 is a timing chart when a program consisting of four consecutive instructions, one load instruction S1 requiring memory access and three arithmetic operation instructions S2 to S4 not requiring memory access, is executed. And L1-CACHE10 for the load instruction S1
3 shows a case where the access to 3 is hit. A load (ld) instruction S1 shown in the figure stores the data of the memory address indicated by the register r0 in the RF 116 in the register r10.
Is an instruction that requires loading. The add (add) instruction S2 stores the result of adding the immediate value 8 to the content of the register r1 to the register r2, and the subtract (sub) instruction S3 stores the result of subtracting the immediate value 8 from the content of the register r3 to the register r3. That is, the add instruction S4 is an instruction requesting that the result of adding the content of the register r5 to the content of the register r4 be stored in the register r4.
Further, D is a decode stage (D stage) for fetching and decoding an instruction code and fetching operand data, E is an execution stage (E stage), and M is a memory stage (M stage for accessing a cache. Stage) and S represents a store stage (S stage) for storing data in a register.

The CPU 101 has a function of executing a load (ld) instruction S1 and an add (add) instruction S2 in parallel.

Describing this operation in detail, first, the cycle 1 is the D stage for each of the instructions S1 and S2. That is, IB111 to DECa112
The load (ld) instruction S1 to the DECb 113 and the addition (add) instruction S2 from the IB 111 to the DECb 113 are fetched and decoded at the same time. For the load (ld) instruction S1, the operand data for calculating the memory address to be loaded is IB11.
Further fetched from 1.

Cycle 2 is the E stage for each of the instructions S1 and S2. First, for the load (ld) instruction S1, the operand data is DECa112.
To ALUa 114 for address calculation. In parallel with this, the ALUb115
The decoding result of the add instruction S2 is received from 3 and RF
116 is accessed to perform addition. On the other hand, DECa
The decoding results in 112 and DECb113 are CT
It is also sent to the RL 118 and is an ALU for memory access.
The address selector 117 is switched so that the signal line 123 on the side of a114 is connected to the address bus 105. As a result, the result of the address calculation by the ALUa 114 passes through the address selector 117 and the address bus 1
05. The MMU 102 translates the logical address on the address bus 105 into a physical address.
Also, a tag for retrieval is read from L1-CACHE 103.

Cycle 3 is the M stage for the load (ld) instruction S1. In this M stage, the L1
-Tag read from CACHE 103 and the MMU1
After being compared with the tag of the physical address obtained in 02, the data to be loaded is read out from the L1-CACHE 103 onto the data bus 106. Figure 9 shows the load (l
d) Shows a case where L1-CACHE 103 hits the instruction S1 and immediately shifts from this M stage to the next S stage. On the other hand, for the add instruction S2, one cycle as the M stage for the load (ld) instruction S1 described above is performed from the E stage (cycle 2), and the next instruction is executed together with the load (ld) instruction S1. No. S stage (cycle 4).

In cycle 4, data on the data bus 106 corresponding to the load (ld) instruction S1 is stored in the RF 116, and at the same time, AL corresponding to the add (add) instruction S2 is stored.
The addition result by Ub115 is also stored in RF116 (S stage).

The following two instructions, subtraction (sub)
Instruction S3 and addition (add) instruction S4 are the above load (ld)
In parallel with the execution of the instruction S1 and the add instruction S2, in cycles 2-5, ALUa114 and ALUb1
Simultaneous execution using both of 15.

FIG. 10 shows the same four instructions as in the case of FIG. 9 described above, that is, a load (ld) instruction S1 and an add (add) instruction S.
2. When executing a program consisting of a subtraction (sub) instruction S3 and an addition (add) instruction S4, a load (ld) instruction S1
Against L1-CACHE1 in the M stage of cycle 3
It is a timing chart when access to 03 is missed. E, E1 and E2 in the figure all represent execution stages. D, M and S have the same meanings as in the case of FIG.

If the access to L1-CACHE 103 is missed in the M stage for the load (ld) instruction S1 in cycle 3, cycle 4 becomes the E1 stage for this load (ld) instruction S1. In this E1 stage, a tag for retrieval is read from the L2-CACHE 104. In the next E2 stage (cycle 5), the tag read from the L2-CACHE 104 is compared with the tag of the physical address obtained in the MMU 102. After comparing the tags, the data to be loaded is L2- in the next M stage (cycle 6).
The data is read from the CACHE 104 onto the data buses 108 and 106. At this time, the address selector 117 in the CPU 101 remains switched to the ALUa 114 side in response to the signal on the mishit signal line 109, and its C
L1-CA from PU 101 through address bus 105
The same address given to CHE103 is
It is given to L2-CACHE 104 through an address bus 107 between L1, L2-CACHE 103 and 104. However, L2-CACHE 104 is L1-CACH
Since the access speed is slower and the capacity is larger than that of the E103, it is possible to access the L1-CACHE 103 in two cycles (E and M stages).
Accessing E104 requires three cycles (E1, E2 and M stages). Then, in the S stage of cycle 7, the CPU 101 stores the read data on the data bus 106 in the RF 116.

If the instruction fetched to the DECa 112 is an arithmetic operation instruction that does not require memory access and the instruction fetched to the DECb 113 is a load instruction that requires memory access at the same time, the CPU 101 determines that the ALUb 115 has an address. The address is sent to the address bus 105 through the selector 117.

[0017]

In the above conventional information processing apparatus, the CPU 101 can send only one address through the address selector 117, and the L1-CA
L2 only when access to CHE103 is missed
-Because the configuration is such that CACHE 104 is accessed, there has been a problem that two instructions that require memory access cannot be executed in parallel at high speed. This point will be described with reference to FIGS. 11 and 12.

FIG. 11 is a timing chart showing an operation when a program consisting of four consecutive load instructions S1 to S4 is executed in the above-mentioned conventional information processing apparatus, and L1-CACHE1 for all load instructions.
This shows a case where access to 03 is hit.
A first load (ld) instruction S1 in the figure is an instruction requesting that the data at the memory address indicated by the register r0 be loaded into the register r10. Similarly, the second load
The (ld) instruction S2 loads the data at the memory address indicated by the register r1 into the register r11, and the third load (ld) instruction S3 loads the data at the memory address indicated by the register r2 into the register r12. The fourth load (ld) instruction S4 is an instruction requesting that the data at the memory address indicated by the register r3 be loaded into the register r13.

The CPU 101 has two load (ld) instructions S
1 and S2 also have a function of executing these in parallel.

Explaining this operation in detail, the cycle 1 is the D stage for each of the instructions S1 and S2. That is, IB111 to DECa112
The first load (ld) instruction S1 to the DECb 113 and the second load (ld) instruction S2 from the IB 111 to the DECb 113 are simultaneously fetched and decoded. Further, for each of the load (ld) instructions S1 and S2, operand data for calculating the memory address is further fetched from the IB 111.

In cycle 2, both load (ld) instructions S1 and S
It is a cycle in which each of the two cases should be in the E stage. However, regarding the first load (ld) instruction S1, A
The address calculation is executed by the LUa 114, and the calculation result is sent to the address bus 105 through the address selector 117.
While being sent to the upper side, the MMU 102 is converting the logical address to the physical address, and the tag is read from the L1-CACHE 103, the ALUb 115 is
An address cannot be sent out on the address bus 105 through the address selector 117. Therefore, although the cycle 2 is in the E stage for the first load (ld) instruction S1, the second load (ld) instruction S2 is in the waiting state as indicated by "hold" in the figure.

In cycle 3, the CPU 101 shifts to the M stage for the first load (ld) instruction S1 and changes to L1.
-About CACHE103 Tag comparison and data bus 1
At the stage of reading data onto 06, the exclusive use of the address selector 117, the address bus 105 and the MMU 102 for the first load (ld) instruction S1 is released, so that the CPU 101 determines that the address selector 117 can be switched to the ALUb 115 side to shift to the E stage for the second load (ld) instruction S2. That is, in cycle 3, the first load (ld) instruction S
1 is in the M stage, and the second load (ld) instruction S2 is in the E stage. That is, the second load (l
d) The E stage of the instruction S2 is the first load (ld) instruction S1.
It is one cycle later than the E stage.

The relationship that the E stage of one load instruction is delayed with respect to the E stage of the other load instruction when two load instructions are executed in parallel is related to the second load (ld) instruction S2. Between the third load (ld) instruction S3, and between the third load (ld) instruction S3 and the fourth load (l
d) The same applies to the command S4. Therefore,
For each of the second to fourth load (ld) instructions S2 to S4, at least one cycle of "hold" is entered. As a result, it takes at least 7 cycles to execute a program composed of four consecutive load (ld) instructions S1 to S4, as shown in FIG.

The above situation is that a load instruction has L
If 1-CACHE 103 misses, it will give worse results.

FIG. 12 shows the L for the first load (ld) instruction S1 when executing the same program consisting of four consecutive load (ld) instructions S1 to S4 as in the case of FIG.
FIG. 9 is a timing diagram when only the access to 1-CACHE 103 is missed.

When the access to L1-CACHE 103 is missed in the M stage for the first load (ld) instruction S1 of cycle 3, the CTR in CPU 101
The L118 receives a signal indicating that the access to the L1-CACHE 103 has missed through the mishit signal line 109, and is temporarily switched to the ALUb115 side for the E stage of the second load (ld) instruction S2. 117 is switched back to the ALUa 114 side for the first load (ld) instruction S1. As a result, the memory address corresponding to the first load (ld) instruction S1 is transmitted to the address bus 105 as in the E stage of cycle 2. Therefore, as in the case of FIG. 10, the first load (ld) instruction S1 of FIG.
Cycle 4 in 2 is the E1 stage for conversion of logical address to physical address by MMU 102 and reading of tag from L2-CACHE 104, cycle 5
Is the tag and MMU read from L2-CACHE104
E2 stage for comparison of the physical address obtained in 102 with the tag, cycle 6 is L2-CACHE1
04 is an M stage for reading data onto the data buses 108 and 106, and cycle 7 is an S stage for storing data to the RF 116.

During this time, L1 of the second load (ld) instruction S2
The M stage for tag comparison and data read for CACHE 103 is the first load (ld) instruction S
Wait until cycle 7 after completion of M stage 1
In other words, the second load (ld) instruction S2 is in a waiting state during cycles 4 to 6 as indicated by "hold" in the figure. Also, the third load (ld) instruction S3
L1 for access to CACHE 103 and L1-for fourth load (ld) instruction S4
The E stage related to access to the CACHE 103 waits until cycle 7 and cycle 8, respectively. As a result, as shown in Figure 12, four consecutive loads (l
d) L1-CACHE10 for the first load (ld) instruction S1 when executing the program including the instructions S1 to S4
If the access to 3 is missed, it takes 10 cycles to execute the program.

It is an object of the present invention to speed up parallel execution of instructions in an information processing apparatus having a cache of a plurality of layers between a central processing unit capable of executing a plurality of instructions in parallel and a main memory. .

[0029]

Means for Solving the Problems The means taken by the present invention to achieve the above object is to provide an access means for simultaneously accessing a plurality of layers of caches when a plurality of instructions are executed in parallel. is there.

More specifically, the invention of claim 1 is as follows.
Execution means for executing a plurality of instructions in parallel, a cache of a plurality of layers from the highest hierarchy closest to the execution means to the lowest hierarchy farthest from the execution means, and at the time of parallel execution of the plurality of instructions by the execution means A configuration including an access unit for simultaneously accessing the caches of a plurality of layers is adopted.

Further, in order to realize a high speed parallel execution of a plurality of load instructions, in the invention of claim 2, the access means executes a plurality of instructions each requiring a memory access in parallel by the execution means. Has a function of simultaneously starting access to each of the caches of the plurality of layers by different addresses based on each of the plurality of instructions.

Further, in order to guarantee high-speed parallel execution of a plurality of load instructions even when a cache access miss occurs, the access means of the invention according to claim 3 is one of a plurality of instructions requiring memory access. When the access to the cache of the upper layer for a certain instruction is hit, the access to the cache of the upper layer is enabled, while the access to the cache of the upper layer is missed, It has a function of starting the access to the cache in the lower layer than the cache in the upper layer for the instruction in which the access miss occurs in parallel with the execution of the cache access for other instructions requiring memory access. I decided.

Further, in order to realize high-speed parallel execution of a load instruction and an instruction other than the load instruction even when a cache access miss occurs, in the invention of claim 4, the access means requires a memory access. When the execution means executes in parallel an instruction to be executed and another instruction which does not require memory access, the access to the caches of the plurality of layers is simultaneously started by the same address based on the instruction requiring the memory access. In addition, when the access to the cache of the upper layer for the instruction requiring the memory access is hit, the access to the cache of the upper layer is enabled, while the access to the cache of the upper layer is enabled. If the access was missed, the instruction was started at the same time as the access to the cache in the upper hierarchy. It was to have a function to enable access to the cache's place in the hierarchy.

Further, in order to perform a convenient conversion from a logical address to a physical address, in the invention of claim 5, the access means provides a plurality of logical addresses for simultaneous access to the caches of the plurality of layers. An address translation device for translating into a physical address suitable for each of the hierarchical caches is provided.

In order to realize an information processing apparatus having a two-level cache, the invention of claim 6 is a two-level cache including an upper first-level cache and a lower second-level cache. And an address bus between the caches for transferring an address for accessing the cache of the first layer to the cache of the second layer is provided between the caches of the second layer. In addition, the following execution means and access means are provided. That is, the execution means includes an instruction buffer for holding a plurality of instructions to be sequentially executed, two instruction decoders for decoding two instructions fetched simultaneously from the instruction buffer, and the two instruction decoders. It has two arithmetic units for executing the instructions decoded by the instruction decoder and a register file for storing the execution results of the instructions by the two arithmetic units, respectively. Each of the two arithmetic units has a function of calculating a logical address for the memory access for an instruction requiring the memory access and outputting the logical address. The access means includes first and second address selectors for guiding a logical address output from each of the two arithmetic units to each of the two-level caches, and an output side of the first address selector. A first address bus connected to the first address bus, a second address bus connected to the output side of the second address selector, and the first address bus for accessing the first level cache.
First address translation device for translating a logical address on the second address bus into a physical address, and a logical address on the second address bus for accessing the second-level cache And a bus for selecting one of the address bus between the caches and the second address bus and connecting the selected address bus to the cache of the second hierarchy. A selector and a control circuit for controlling switching of each of the first and second address selectors and the bus selector are provided.

Further, in order to achieve cooperation between the caches,
According to the invention of claim 7, the cache of the upper layer of the caches of the plurality of layers has a smaller storage capacity and can be accessed in a shorter cycle than each of the caches of the layer lower than the cache of the upper layer. I decided to complete it.

Further, in order to ensure the uniformity of data between the caches, in the invention of claim 8, the caches of a plurality of layers are set in the case where data at an address in a cache of an upper layer is rewritten. By having the function of rewriting the data of the same address in each of the caches of the lower layer than the cache of the upper layer with the same data as the cache of the upper layer,
A write-through type coherency protocol is implemented for the caches in the upper layers.

[0038]

According to the first aspect of the present invention, since caches of a plurality of layers are simultaneously accessed when a plurality of instructions are executed in parallel, caches of a lower layer are cached only when an access to a cache of an upper layer is missed. Unlike the conventional configuration for accessing the cache, the wait for access to the cache can be eliminated, and the instruction execution speed is improved.

Further, according to the second aspect of the present invention, when a plurality of instructions each requiring a memory access are executed in parallel, access to the caches of a plurality of hierarchies based on mutually different addresses is started at the same time. High-speed parallel execution of the load instruction of can be realized.

According to the third aspect of the present invention, even when an access miss occurs in a cache in an upper hierarchy when a plurality of instructions each requiring a memory access are executed in parallel, the instruction in which the access miss occurs Since the access to the cache in the lower hierarchy of is started in parallel with the execution of the cache access for other instructions that require memory access, high-speed parallel execution of multiple load instructions can be guaranteed. In other words, in the past, when the access to the cache is missed in the execution of the first load instruction, the penalty of the subsequent load instruction was significantly increased, but the penalty can be greatly reduced.

According to the invention of claim 4, in parallel execution of an instruction requiring memory access and another instruction not requiring memory access, a cache in a lower hierarchy for the instruction requiring memory access. Since the access to the cache of the upper layer is started in advance at the same time as the access to the cache of the upper layer, even if an access miss of the cache of the upper layer occurs, the cache of the lower layer that was started earlier is accessed. By making the access valid, the access to the cache in the lower hierarchy can be completed quickly. In other words, when a cache access miss occurs, the penalty for an access miss is reduced compared to when the access to the cache of the upper layer is confirmed and then the access to the cache of the lower layer is started. However, high-speed parallel execution of load instructions and instructions other than load instructions can be realized.

According to the invention of claim 5, the address translation device translates a plurality of logical addresses into physical addresses for the caches of a plurality of layers in parallel, so that the physical addresses of a plurality of layers to be accessed are accessed. Simultaneous access to the cache is possible.

According to the concrete configuration of the information processing apparatus of the sixth aspect of the present invention, since the caches of the two layers are simultaneously accessed when the two instructions are executed in parallel, the waiting for access to the cache can be eliminated. Execution speed is improved. Further, the penalty for access miss is reduced.

Further, according to the invention of claim 7, since the cache of the upper layer, which has a smaller storage capacity than the cache of the lower layer, is accessed in a short cycle,
It is possible to achieve cooperation among caches of multiple layers having different access speeds.

Further, according to the invention of claim 8, when the data of a certain address in the cache of the upper layer is rewritten, the data of the same address of the cache of the lower layer is the same as the cache of the upper layer. Since the data is rewritten with the data of, it is possible to guarantee the consistency of the data between the caches of multiple layers.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention, which is provided with a two-level cache between a central processing unit (CPU) and a main memory (not shown). In the figure, 1 is a CPU capable of executing two instructions in parallel,
Reference numeral 4 is a first layer cache (L1-CACHE), and 5 is a second layer cache (L2-CACHE). However, the access speed of L1-CACHE4 is faster,
The storage capacity of L2-CACHE5 is larger. Also, 2
Is the first to pass the physical address to L1-CACHE4
Address translator (MMUa), 3 is L2-CACH
A second address translation unit (MMUb) for passing a physical address to E5, 6, 8 and 12 are address buses, 7,
Reference numerals 9 and 11 are data buses. 10 is L1-CAC
L1, L2-CA carrying the same address as the address on the first address bus 6 for accessing HE4
Address bus 12 between CHE 4 and 5 and CPU 1 to L
It is a bus selector for selecting either of the second address bus 8 for directly accessing L2-CACHE5 without passing through 1-CACHE4. Also,
Reference numeral 13 is a mishit signal line for notifying the CPU 1 when the access to L1-CACHE 4 is missed,
Reference numeral 14 is a bus selection signal line from the CPU 1 to the bus selector 10.

The access to L1-CACHE4 is a pipeline operation of a total of two cycles, in which tag reading, tag comparison and data reading are executed in one cycle each, and access to L2-CACHE5 is performed. The pipeline operation is a total of 3 cycles in which tag reading, tag comparison, and data reading are each performed in one cycle. That is, L2-CACHE5 is L
Since the access speed is slower and the capacity is larger than that of 1-CACHE4, as in the case of FIG. 7, L1-CACHE is used.
Accessing 4 requires only 2 cycles (E and M stages), while accessing L2-CACHE5 requires 3 cycles (E1, E2 and M stages). L1-CACHE4 is a write-through type coherency protocol.
-When the data in CACHE4 is updated by a store instruction or the like, the data in L2-CACHE5 at the same address as the data updated in L1-CACHE4 is also updated at the same time.

In the information processing apparatus of FIG. 1, when the CPU 1 executes two load instructions requiring memory access in parallel, different logical addresses from the CPU 1 on the two independent address buses 6 and 8, respectively. Sent out. Then, a part of one logical address issued from the CPU 1 through the first address bus 6 is MMUa.
It is converted to a physical address by 2 and L1-CACHE4 is accessed together with the remaining part. When the access hits, the data is fetched from the L1-CACHE 4 to the CPU 1 through the first data bus 7. At the same time, a part of the other logical address issued from the CPU 1 through the second address bus 8 is MMUb.
3 is converted into a physical address, and L2-CACHE5 is accessed through the bus selector 10 together with the remaining part. When the access hits, the data is fetched from the L2-CACHE 5 to the CPU 1 through the second data bus 9. Also, L1-CA
When a miss occurs in the access of CHE4, the selector 10 causes the address bus 12 between L1, L2-CACHE.
, The same address as the address of the data that accessed L1-CACHE4 is switched to the L2-CACH
The data is transferred to E5, and the data is fetched from the L2-CACHE 5 to the CPU 1 through the data buses 11 and 7. If L2-CACHE5 also makes a mistake, data is fetched from the main memory, but the configuration for that is omitted in the figure.

FIG. 2 is a block diagram showing the internal structure of the CPU 1 in FIG. In FIG. 2, reference numeral 21 denotes an instruction buffer (I) for holding a plurality of instructions to be sequentially executed.
B), 22 is a first instruction decoder (DECa) for decoding the instruction fetched from the IB 21, and 23 is also I
Second to decode the next instruction fetched from B21
Instruction decoder (DECb), 24 is a first arithmetic unit (ALU) for executing the instruction decoded by the DECa 22.
a), 25 is a second arithmetic unit (ALUb) for executing the instruction decoded by the DECb 23, and 26 is, for example, r0
Register file (RF) including 32 registers of r31 to r31, 27 and 28 are address selectors, 29 is a data selector, and 30 is two address selectors 27 and 2.
8 and data selector 29 and the bus selector 10
Is a control circuit (CTRL) for switching each of the above.
Further, 31 and 32 are fetch signal lines, 33 and 34 are decode signal lines, 35 and 36 are signal lines for transmitting addresses or data, and 37 is an address selection signal line from the CTRL 30 to the two address selectors 27 and 28. Three
8 is a data selection signal line from the CTRL 30 to the data selector 29, 39 is a signal line for transmitting data from the data selector 29 to RF 26, and 40 and 41 are RF 26
From ALUa24 and ALUb25. The first address bus 6 is the first
To the output side of the address selector 27, the second address bus 8 to the output side of the second address selector 28, and the first and second data buses 7 and 9 to the input side of the data selector 29. The line 13 and the bus selection signal line 14 are connected to the CTRL 30, respectively.

Next, the operation of the information processing apparatus according to this embodiment having the above configuration will be described with reference to FIGS.

FIG. 3 shows that when a program consisting of four consecutive load (ld) instructions S1 to S4, which is the same as in the case of FIGS. 11 and 12, is executed, L1 and L2- are applied to any of the load (ld) instructions. FIG. 11 is a timing diagram when neither CACHE 4 nor 5 causes an access miss. In the figure, D is a decode stage for fetching and decoding an instruction code and fetching operand data,
E, E1 and E2 represent execution stages, M represents a memory stage for accessing a cache, and S represents a store stage for storing data in a register.

First, the parallel execution of the first load (ld) instruction S1 and the second load (ld) instruction S2 by the CPU 1 will be described.

In cycle 1 in FIG. 3, both instructions S1 and S2 are executed.
It is the D stage for each of. That is, I
First load (ld) instruction S1 from B21 to DECa22
Fetching and decoding it, and also from IB21 to DEC
Fetching and decoding of the second load (ld) instruction S2 to b23 are performed at the same time. Both load (ld) instructions S
For each of S1 and S2, operand data for calculating the memory address is further fetched from IB21.

In cycle 2, the first load (ld) instruction S1
And the E1 stage for the second load (ld) instruction S2. First, for the first load (ld) instruction S1, the operand data is DEC.
The address calculation is executed by passing the data from a22 to the ALU a24, and the operand data of the second load (ld) instruction S2 is transferred from the DECb23 to the ALUb25 and the address calculation is executed. On the other hand, DECa22 and DEC
The decoding result in b23 is also sent to the CTRL 30, respectively, and the first address selector 27 is switched so as to connect the signal line 35 on the ALUa 24 side to the first address bus 6 and the signal line 36 on the ALU b25 side.
The second address selector 28 is switched so that the second address selector 28 is connected to the second address bus 8. Further, the bus selector 10 is switched to the second address bus 8 side.
As a result, the result of the address calculation by the ALUa 24 is transmitted to the first address bus 6 via the first address selector 27, and at the same time, the result of the address calculation by the ALUb 25 is transmitted via the second address selector 28 to the second address selector 28.
On the address bus 8 of L.sub.2, and the L2-CACHE 5 can be directly accessed from the CPU 1. And M
The MUa 2 translates a logical address on the first address bus 6 into a physical address, while the MMUb 3 translates a logical address on the second address bus 8 into a physical address.
Also, a tag for retrieval is read from each of L1, L2-CACHE 4, 5.

In cycle 3, the first load (ld) instruction S1
, And the E2 stage for the second load (ld) instruction S2. First, regarding the first load (ld) instruction S1, the L1-CACHE4
After comparing the tag read from the tag with the tag of the physical address obtained in the MMUa2, L1-CACHE
The data to be loaded from 4 is read onto the first data bus 7. On the other hand, for the second load (ld) instruction S2, only the comparison between the tag read from the L2-CACHE5 and the tag of the physical address obtained in the MMUb3 is executed. L2-CACHE5 is L1-CA
Since the access speed is slower and the capacity is larger than that of CHE4, tag comparison and data reading can be completed in one cycle for L1-CACHE4, whereas tag access is possible for L2-CACHE5. Only one comparison requires one cycle.

In cycle 4, the first load (ld) instruction S1
, And the M stage for the second load (ld) instruction S2. FIG. 3 shows a case where L1-CACHE4 is hit with respect to the first load (ld) instruction S1, and the stage immediately shifts from the M stage to the S stage to respond to the first load (ld) instruction S1. The data on the first data bus 7 is stored in the RF 26 via the data selector 29. On the other hand, the second load (l
d) For the instruction S2, data is read from the L2-CACHE 5 onto the second data bus 9.

Then, in cycle 5, the data selector 29 moves from the first data bus 7 side to the second data bus 9 side.
, And the data on the second data bus 9 in response to the second load (ld) instruction S2 is stored in the RF 26.

Third and fourth load (ld) instructions S3 and S4
Is executed by executing the above first and second load (ld) instructions S1,
Similar to the execution of S2, it is performed from cycle 2 to cycle 6. At this time, the third load (ld) instruction S3
Is accessed, and L2-CACHE5 is accessed for the fourth load (ld) instruction S4. Here, in cycle 3, L2-CAC
Regarding HE5, tag comparison at the E2 stage of the second load (ld) instruction S2 and E of the fourth load (ld) instruction S4
Although the reading of the tag in the first stage overlaps, there is no problem in the access of L2-CACHE5 because the reading of the tag, the comparison of the tag, and the reading of the data are performed in the pipeline operation of 3 cycles.

As described above, as shown in FIG. 11, four consecutive loads (ld) that conventionally required 7 cycles even though there was no access miss in any cache.
In the present embodiment, the execution of the program consisting of the instructions S1 to S4 is L1, L2-CACHE for each load instruction.
By adopting a configuration of accessing 4, 5 in parallel, it is completed in 6 cycles as shown in FIG.

FIG. 4 shows a case where the same load (ld) instruction S1 to S4 as in FIG.
It is a timing diagram when only access to 1-CACHE4 misses.

If the access to L1-CACHE4 in the M stage for the first load (ld) instruction S1 in cycle 3 is missed, CTRL30 in CPU1
Receives a signal indicating that the access to L1-CACHE4 is missed through the mishit signal line 13, and in response to the signal, the bus selector 10 which has been switched to the address bus 8 side is loaded into the first load (ld ) Address bus 12 between L1, L2-CACHE 4, 5 for instruction S1
Switch to the side. As a result, the first load (ld) instruction S1
, Cycle 4 is an E1 stage for reading a tag from L2-CACHE 5, cycle 5 is an L2-stage.
E2 stage for comparing the tag read from CACHE5 with the tag of the physical address obtained in cycle 4 in MMUa2, cycle 6 is the M stage for reading data from L2-CACHE5 onto the data buses 11 and 7. , Cycle 7 is the S stage for storing data in RF 26.

In the meantime, with respect to the second load (ld) instruction S2, the data is read from the L2-CACHE 5 to the second data bus 9 in the cycle 4 (M stage).
Then, the storage of data in the RF 26 (S stage) is completed in cycle 5.

Third and fourth load (ld) instructions S3 and S4
Is executed from cycle 2 to cycle 6 in parallel with the execution of the first and second load (ld) instructions S1 and S2 as in the case of FIG. At this time, L1-CACHE4 is accessed for the third load (ld) instruction S3, and L2- is accessed for the fourth load (ld) instruction S4.
Try to access CACHE5. However, the CTRL 30, which has received the signal indicating that the access to the L1-CACHE 4 is missed in the cycle 3 through the mishit signal line 13, immediately invalidates the E2 stage of the fourth load (ld) instruction S4 and After setting cycle 3 to “hold”, in cycle 4, the two address selectors 27 and 28 are switched so as to output the address calculation result of the ALUb 25 through the first address bus 6. As a result, both the third and fourth load (ld) instructions S3 and S4 are L1-C.
ACHE4 will be accessed. That is, for the third load (ld) instruction S3, cycle 3 is ALUa2.
E stage for reading the tag from L1-CACHE4 based on the address calculation result of 4, the M stage for comparing the tag and reading the data from L1-CACHE4, cycle 5 for storing the data It will be the S stage. For the fourth load (ld) instruction S4, cycle 4 is the E stage for reading the tag from L1-CACHE4 based on the address calculation result of the ALUb 25, and cycle 5 is the tag comparison and L stage.
The M stage for reading data from 1-CACHE 4 and the S stage for storing data in cycle 6 are provided.

As described above, the conventional four load (ld) instructions S1 to S4 required 10 cycles when there is a cache access miss as shown in FIG.
Is completed in 7 cycles in this embodiment as shown in FIG.

Next, a case will be described in which a program consisting of four consecutive instructions, one load instruction S1 requiring memory access and three arithmetic operation instructions S2 to S4 not requiring memory access, is executed.

FIG. 5 is the same as the case of FIG. 9 and FIG.
When executing a program consisting of one instruction, that is, a load (ld) instruction S1, an addition (add) instruction S2, a subtraction (sub) instruction S3, and an addition (add) instruction S4, L1-CACHE4 is hit to the load instruction S1. FIG.

In FIG. 5, in cycle 1, both instructions S
It is the D stage for each of S1 and S2. That is, the load (ld) instruction S from IB21 to DECa22
Fetch 1 and decode it, also from IB21 to DE
The addition (add) instruction S2 to Cb23 is fetched and decoded at the same time. For the load (ld) instruction S1, the operand data for calculating the memory address to be loaded is further fetched from the IB21.

Cycle 2 is the E stage for each of the instructions S1 and S2. However, load (ld)
The instruction S1 is also the E1 stage. That is, when the decoding results in the DECa 22 and the DECb 23 are sent to the CTRL 30, respectively, and when one instruction requires the memory access and the other instruction does not require the memory access, the CTRL 30 sets the first and second instructions. The two address selectors 27 and 28 are switched so that the same logical address is transmitted to the address buses 6 and 8. In this example, two instruction decoders DECa22, D
Since the instruction decoded by DECa22 of ECb23 is an instruction that requires memory access, ALUa2
The first address selector 27 is switched to connect the signal line 35 on the No. 4 side to the first address bus 6, and the signal line 35 on the ALUa 24 side is also connected to the second address bus 8. The second address selector 28 is switched to. In addition, the bus selector 10
Are switched to the second address bus 8 side. As a result, the result of the address calculation regarding the load (ld) instruction S1 in the ALUa 24 is L1, L2-CACHE4,5.
Will be used to access both simultaneously. In other words, cycle 2 is the E stage and the E1 stage for the load (ld) instruction S1.
Ua2 translates a logical address on the first address bus 6 into a physical address, while MMUb3 translates the same logical address on the second address bus 8 into a physical address. Also, from each of L1, L2-CACHE4,5
The tag for retrieval is read. On the other hand, ALUb25
Receives the decoding result of the add instruction S2 from the DECb23 in parallel with the processing of the E and E1 stages for the load (ld) instruction S1, and accesses the RF26 to execute the addition. The data selector 2 in the CPU 1
9 is switched to the first data bus 7 side.

Cycle 3 is the M stage and E2 stage for the load (ld) instruction S1. That is, L1
-Comparison between the tag read from CACHE4 and the tag of the physical address obtained in MMUa2, and L1-CA
L2-CACHE operation of the M stage, which includes reading data from the CHE 4 onto the first data bus 7.
The operation of the E2 stage, which includes only the comparison between the tag read from step 5 and the tag of the physical address obtained in MMUb3, proceeds in parallel. FIG. 5 shows a case where L1-CACHE4 is hit with respect to the load (ld) instruction S1. In this case, the result obtained in the E2 stage is invalidated and the M stage immediately shifts to the next S stage. To do. On the other hand, with respect to the add (add) instruction S2, one cycle as the M and E2 stages for the load (ld) instruction S1 described above is placed after the load (ld) instruction S1 from the E stage (cycle 2). At the same time, the process proceeds to the next S stage (cycle 4).

In cycle 4, the data on the first data bus 7 corresponding to the load (ld) instruction S1 is stored in the RF 26 through the data selector 29, and at the same time, the ALUb 25 corresponding to the add (add) instruction S2 is stored. The addition result of is also stored in the RF 26 (S stage).

In addition, the following two instructions, that is, subtraction (sub)
Instruction S3 and addition (add) instruction S4 are the above load (ld)
In parallel with the execution of the instruction S1 and the addition (add) instruction S2, in cycles 2-5, ALUa24 and ALUb25
Both are executed simultaneously. Therefore, in the same five cycles as in the case of FIG. 9, the above four instructions S1 to S4 are executed.
The execution of the program consisting of is completed.

FIG. 6 shows the same four instructions as in the case of FIG. 5, namely, a load (ld) instruction S1 and an add (add) instruction S.
2. When executing a program consisting of a subtraction (sub) instruction S3 and an addition (add) instruction S4, a load (ld) instruction S1
Against L1-CACHE4 in the M stage of cycle 3
FIG. 8 is a timing diagram when access to the memory is missed.

In this case, access to L2-CACHE5 as the E2 stage in cycle 3 becomes valid, and cycle 4 becomes the M stage for the load (ld) instruction S1. That is, L2-CA in cycle 3
In the cycle 4, the data to be loaded is read from the L2-CACHE 5 onto the second data bus 9 in response to the result of the comparison of the tags relating to CHE 5. The data selector 29 in the CPU 1 is switched to the second data bus 9 side by the CTRL 30 which receives the signal notifying the access miss from the L1-CACHE 4 through the mishit signal line 13, and in the cycle 5, the load (ld) instruction S1 is sent.
The data on the second data bus 9 in response to is stored in the RF 26 through the data selector 29 (S stage).

As for the other three arithmetic operation instructions S2 to S4, parallel execution is advanced so that the processing is completed by cycle 5, as in the case of FIG.

As described above, one load instruction S1 and three arithmetic operation instructions S2 to S4, which conventionally took 7 cycles when there is an L1-CACHE4 access miss as shown in FIG. 10, are consecutive. In the present embodiment, the execution of the program consisting of four instructions is performed in five cycles as shown in FIG. 6 by adopting a configuration in which L1, L2-CACHE4,5 are accessed in parallel for one load (ld) instruction S1. Complete with. That is, it is possible to reduce the penalty caused by the access error of L1-CACHE4.

The above description is based on the two address translation devices (MMU) for translating each logical address into a physical address.
a2, MMUb3), the information processing device having the same function by using one address conversion device having a plurality of read ports and capable of simultaneously converting a plurality of logical addresses into physical addresses. It goes without saying that the device can be configured. Also, CPU1
L1, L2-CACHE using the logical addresses on the first and second address buses 6 and 8 output from
If four and five can be accessed in parallel, it is not necessary to provide MMUa2 and MMUb3.

[0078]

As described above, according to the first aspect of the present invention, since the caches of a plurality of layers are simultaneously accessed in parallel execution of a plurality of instructions,
Unlike the conventional configuration in which the cache of the lower layer is accessed only when the access to the cache of the upper layer is missed, the wait for access to the cache can be eliminated, and the instruction execution speed is improved.

According to the second aspect of the present invention, a configuration is adopted in which, when a plurality of instructions each requiring a memory access are executed in parallel, access to caches of a plurality of layers based on mutually different addresses is simultaneously started. Therefore, for example, when executing a program having a plurality of consecutive load instructions, the execution speed is increased.

According to the third aspect of the present invention, when a plurality of instructions each requiring a memory access are executed in parallel, when an access miss occurs in the cache in the upper hierarchy, the instruction causing the access miss occurs. Since a structure is adopted in which the access to the cache in the lower hierarchy of is started in parallel with the execution of the cache access for other instructions that require memory access, multiple load instructions are executed even if there is a cache access miss. High-speed parallel execution of can be guaranteed.

According to the fourth aspect of the invention, in parallel execution of an instruction requiring memory access and another instruction not requiring memory access, a lower hierarchy of the instruction requiring memory access Since a structure is adopted in which access to the cache is started in advance at the same time as access to the cache in the upper layer, the penalty in the case of an access miss in the cache in the upper layer is reduced, and other than load and load instructions. High-speed parallel execution with the instruction of can be realized.

Further, according to the invention of claim 5, since an address translation device for translating a plurality of logical addresses into a physical address for each of a plurality of layers of caches in parallel is provided, a physical address is provided. It is possible to realize simultaneous access to multiple levels of cache to be accessed.

Further, according to the invention of claim 6, in the information processing apparatus having the two-level cache, two instruction decoders and two arithmetic units are provided between the instruction buffer and the register file. An execution means for executing two instructions in parallel, and the execution means and the above-mentioned 2
By providing two address buses and two address translation devices that are used for switching between the two-tier caches as necessary, an access means for simultaneously accessing the two-tier caches is constructed. The waiting can be eliminated, and the instruction execution speed can be improved and the penalty for access miss can be reduced.

Further, according to the invention of claim 7, the cache of the upper layer, which has a smaller storage capacity than the cache of the lower layer, adopts a configuration in which the access is completed in a short cycle. Coordination between caches in the hierarchy can be achieved.

Further, according to the invention of claim 8, when the data of a certain address in the cache of the upper layer is rewritten, the data of the same address of the cache of the lower layer is the same as the cache of the upper layer. Since a write-through coherency protocol in which the data is rewritten with the above data is adopted, it is possible to guarantee the consistency of the data between the caches of multiple layers.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a CPU in FIG.

FIG. 3 is a timing chart showing an operation when a program consisting of four consecutive load instructions is executed in the information processing apparatus of FIG. It shows the case where no occurs.

FIG. 4 is a view similar to FIG. 3, showing a case where only a first-level cache access for a first load instruction is missed.

5 is a timing chart showing an operation in the case where a program consisting of four consecutive instructions of one load instruction and three arithmetic operation instructions is executed in the information processing apparatus of FIG. 1, and FIG. This shows a case where an access to the cache of one layer is hit.

FIG. 6 is a diagram similar to FIG. 5 and shows a case where an access to the first level cache for a load instruction is missed.

FIG. 7 is a block diagram showing an example of a conventional information processing device.

8 is a block diagram showing an internal configuration of a CPU in FIG.

9 is a timing chart corresponding to FIG. 5 in the information processing apparatus of FIG.

10 is a timing chart corresponding to FIG. 6 in the information processing apparatus of FIG.

11 is a timing chart showing an operation when a program consisting of four consecutive load instructions is executed in the information processing apparatus of FIG. 7, and an access to the cache of the first layer is hit for any of the load instructions. This shows the case where

FIG. 12 is a diagram similar to FIG. 11 and shows a case where an access to the cache of the first layer misses only for the first load instruction.

[Explanation of symbols]

1 Central processing unit (CPU) 2 First address translation unit (MMUa) 3 Second Address Translation Unit (MMUb) 4 First level cache (L1-CACHE) 5 Second level cache (L2-CACHE) 6 First address bus 7 First data bus 8 Second address bus 9 Second data bus 10 bus selector 11 Data bus between L1, L2-CACHE 12 Address bus between L1, L2-CACHE 13 Miss hit signal line 14 Bus selection signal line 21 Instruction buffer (IB) 22 First Instruction Decoder (DECa) 23 Second Instruction Decoder (DECb) 24 First arithmetic unit (ALUa) 25 Second arithmetic unit (ALUb) 26 register file (RF) 27 First Address Selector 28 Second address selector 29 Data selector 30 Control circuit (CTRL)

Claims (8)

[Claims] 1. An execution means for executing a plurality of instructions in parallel, a plurality of layers of caches from the highest hierarchy closest to the execution means to the lowest hierarchy farthest from the execution means, and a plurality of caches by the execution means. An information processing apparatus comprising: an access unit for simultaneously accessing the caches of a plurality of layers when instructions are executed in parallel. 2. The information processing apparatus according to claim 1, wherein the access unit is based on each of the plurality of instructions when the execution unit executes a plurality of instructions each requiring a memory access in parallel. An information processing apparatus having a function of simultaneously starting access to each of the caches of a plurality of layers by different addresses. 3. The information processing apparatus according to claim 2, wherein the access unit, when an access to a cache in a higher hierarchy regarding an instruction of a plurality of instructions requiring memory access hits, When the access to the cache in the upper layer is enabled, but the access to the cache in the upper layer is missed, the access to the cache in the upper layer is lower than that of the cache in the upper layer. An information processing apparatus having a function of starting access to a cache of a hierarchy in parallel with execution of cache access relating to another instruction requiring memory access. 4. The information processing apparatus according to claim 1, wherein the access unit, when the execution unit executes in parallel an instruction that requires memory access and another instruction that does not require memory access, When access to the caches of the plurality of layers is started at the same time by the same address based on the instruction requiring the memory access, and an access to the cache of an upper layer related to the instruction requiring the memory access is hit. Enables the access to the cache of the upper layer, while the access to the cache of the upper layer is missed, the instruction is started simultaneously with the access to the cache of the upper layer. An information processing apparatus having a function of validating access to a cache in a lower hierarchy. 5. The information processing apparatus according to claim 1, wherein the access unit sets a plurality of logical addresses for simultaneous access to the caches of a plurality of layers to a physical address suitable for each of the caches of a plurality of layers. An information processing apparatus comprising an address translation device for translation. 6. The information processing apparatus according to claim 1, wherein the caches of a plurality of layers include a two-layer cache including an upper first-layer cache and a lower second-layer cache, and the two-layer cache. Between the caches, an address bus between the caches for transferring an address for accessing the cache of the first layer to the cache of the second layer is provided. Buffer for holding the instructions of the above, two instruction decoders for decoding the two instructions fetched simultaneously from the instruction buffer, and the instructions decoded by the two instruction decoders, respectively. And two register files for respectively storing execution results of instructions by the two arithmetic units, each of the two arithmetic units being , Has a function of calculating a logical address for the memory access for an instruction requiring the memory access and outputting the logical address, wherein the access means outputs from each of the two arithmetic units. First and second address selectors for directing a logical address to be stored to each of the two-level caches, and the first and second address selectors.
A first address bus connected to the output side of the second address selector, a second address bus connected to the output side of the second address selector, and the first address bus for accessing the first level cache. A first address translation device for translating a logical address on a first address bus into a physical address, and a logical address on the second address bus for accessing a cache of the second layer. A second address translation device for translating data into a cache, and selecting one of the address bus between the caches and the second address bus and connecting the selected address bus to the cache of the second hierarchy. Bus selector, and a control circuit for controlling switching of each of the first and second address selectors and the bus selector. The information processing apparatus according to claim and. 7. The information processing apparatus according to claim 1, wherein a cache of an upper layer of the caches of the plurality of layers has a storage capacity higher than that of a cache of a lower layer than the cache of the upper layer. An information processing apparatus characterized in that access is completed in a short cycle with a small size. 8. The information processing apparatus according to claim 1, wherein the caches of the plurality of layers are lower than the cache of the upper layer when data at an address in the cache of the upper layer is rewritten. An information processing apparatus having a function of rewriting data of the same address in each of the caches of the same cache with the same data as the cache of the upper hierarchy.