JPH05120075A - Runaway detecting method for cpu - Google Patents

Abstract

PURPOSE:To detect the runaway of a CPU while complicated check being made possible and in addition, without imposing a burden upon a CPU by supplying forcedly a reset signal to the CPU when it is detected that transmission routine is not finished even after a lapse of prescribed time. CONSTITUTION:A timer in an abnormality detection circuit 20 is started by detecting that the transmission routine is started after it is initialized by an initializing signal EE from the CPU 10. When this abnormality detection circuit 20 detects that the transmission routine is not finished even after the time based on the measurement of the timer elapses over a prescribed time, it supplies forcedly the reset signal (abnormality detection signal UDOUT) to the CPU 10. In this case, the abnormality detection circuit 20 monitors the address bus and the data bus of the CPU 10 or a control signal BCPU like the reset signal, etc. Accordingly, there is no work the CPU 10 executes for the abnormality detection circuit 20 excepting the work for initialization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CP for controlling a packet data communication circuit in which data transmission is performed irregularly.
The present invention relates to a U runaway detection method.

[0002]

2. Description of the Related Art As a conventional runaway detecting circuit of a CPU for controlling a packet data communication circuit in which data transmission is performed irregularly, for example, a runaway of a CPU is detected and a reset or interrupt is issued to this CPU. There is a calling circuit. In this way, CPU runaway is detected and this CP
As a circuit for resetting or interrupting U, specifically, there is, for example, a so-called watchdog timer 140 as shown in FIG.

The watchdog timer 140 is a simple timer and is initialized by the CPU 100 (initialized by an initialization signal EE from the CPU 100). Further, the CPU 100 resets the timer 140 (reset by the clear signal CR from the CPU 100) when there is a portion in the program to be executed within a certain time without fail.

Here, the watchdog timer 140
The time-out time (time-out signal T _OUT ) of the CPU 100 when this CPU 100 operates normally.
If the U100 is set to be larger than the maximum interval for resetting the timer 140 (clear signal CR), the timer 140 normally does not time out.

Therefore, for example, if the CPU 100 goes out of control and the timer 140 is no longer reset,
The timer 140 times out. In the conventional runaway detection circuit, the time-out signal T _OUT from the timer 140 is sent to the reset or interrupt terminal of the CPU 100 to restore the CPU 100 to a normal state.

[0006]

By the way, for example, if the timer 140 is reset in the main routine of the program, for example, when an abnormality of the CPU 100 occurs that interrupts are not taken, 1 like watchdog timer 140
This means that one timer cannot detect this abnormality. Therefore, to deal with such anomalies,
It is necessary to increase the number of checkpoints for detecting abnormalities by providing one timer.

In other words, as the number of checkpoints increases as described above, the number of timers must be increased accordingly, and as a result, it becomes necessary to arrange a routine for resetting the timers everywhere in the program, and the CPU 100 Will result in slower execution speed.

Therefore, the present invention has been proposed in view of the above situation, and provides a runaway detection method for a CPU, which allows a complicated check and does not burden the CPU at all. The purpose is.

[0009]

A method of detecting runaway of a CPU according to the present invention is proposed to achieve the above-mentioned object, and is for controlling a packet data communication circuit in which data transmission is performed irregularly. In the CPU runaway detection method described above, a timer is started by detecting the start of the transmission routine, and if the transmission routine does not end even if a predetermined time has elapsed, the CPU is detected by the CPU. The reset signal is forcibly supplied.

That is, a CPU runaway detection circuit for implementing the CPU runaway detection method of the present invention includes, for example, a trigger circuit for generating a pulse when the address bus, data bus, control line, etc. of the CPU are in a designated state, It is composed of a timer and a circuit for controlling the timer and a circuit for generating an abnormality detection signal. The runaway detection circuit detects an abnormal (runaway) state of the CPU by monitoring the bus state of the CPU. , C based on this detection result
The PU is reset or interrupted.

[0011]

According to the CPU runaway detection method of the present invention, if the transmission routine does not end within a predetermined time after the transmission routine is started, it is highly possible that the CPU is out of control. By forcibly resetting the CPU, runaway of the CPU is prevented.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

The CPU runaway detection method of this embodiment is a CPU runaway detection method for controlling a packet data communication circuit in which data transmission is performed irregularly.
As shown in FIG. 1, the initial setting signal EE from the CPU 10
After the initialization is started, the timer in the abnormality detection circuit 20 is started by detecting that the transmission routine has started, and even if the time based on the measurement of the timer in the abnormality detection circuit 20 exceeds a predetermined time. When it is detected that the transmission routine is not completed, the reset signal (abnormality detection signal UD _OUT ) is forcibly supplied to the CPU.

Here, in the watchdog timer 140 of the conventional example shown in FIG. 10 described above, the CPU 100 performs an operation of clearing the timer 140. However, in the embodiment of the present invention, the abnormality detection circuit 20 is used for the bus of the CPU 10 or the like. Signal B
_{I am trying} to monitor the _CPU . Therefore, in the present embodiment, the CPU 10 does not perform any work on the abnormality detection circuit 20 except for the initial setting work.

Three specific configurations (abnormality detection circuit 2) for specifically implementing the CPU runaway detection method of this embodiment
A specific configuration of 0) is shown below.

First, of the three specific configurations, the first
FIG. 2 shows the configuration of a concrete example of the above. The configuration of the first specific example is a configuration in which abnormality detection of the CPU 10 is executed by the monitor circuit of the CPU 10 alone.

In the structure of FIG. 2, the signal B _CPU of the bus of the CPU 10 shown in FIG. 1 is supplied to the terminal 21. The signal B _CPU supplied to this terminal 21 is CP
It is sent to the U monitor circuit 22. The CPU monitor circuit 2
2 is supplied with the output of the register 23. Also, this C
The output of the PU monitor circuit 22 is a 2-input AND (logical product)
It is supplied to one input terminal of the gate 25. The other input terminal of the 2-input AND gate 25 has a register 24
The output of is supplied. This 2-input AN
The output terminal of the D gate 25 is connected to the output terminal 26 of the first specific example.

The CPU monitor circuit 22 includes the CPU
This is a circuit for monitoring control signals (the above signal B _CPU ) such as 10 address buses, data buses and reset signals, and for generating a pulse when the specified conditions are met. That is, the CPU monitor circuit 22 is specifically a circuit corresponding to the trigger function of the so-called emulator of the CPU 10 or the logic analyzer.

The register 23 is a register for designating the trigger condition (a specific example of the trigger condition will be described later), and the register 24 is a register for controlling the output of the first specific example.

Here, when the output of the register 24 is, for example, "H", the condition specified by the register 23 and the state of the signal monitored by the CPU monitor circuit 22 match (for example, the CPU monitor circuit 22). To "H"
Is output), a pulse (abnormality detection signal UD _OUT ) is output from the output terminal of the AND gate 25, that is, the output terminal 26. The output terminal 26 from which this pulse (abnormality detection signal UD _OUT ) is output is connected to the reset or interrupt signal input terminal of the CPU 10. This prevents the CPU 10 from running out of control.

In the first specific example, the CPU 10 corresponding to the output terminal 26 is active "H". However, for example, an active "L" specification C is used.
When connecting to the input of PU, it is necessary to insert and connect an inverter after the AND gate 25 to invert the logic.

FIG. 3 shows the configuration of the second specific example. The second specific example is a combination of the CPU monitor circuit 22 and the timer 33. In FIG. 3, the same components as those in FIG. 2 are designated by the same reference numerals.

In the structure of FIG. 3, the signal B _CPU of the bus of the CPU 10 shown in FIG. 1 is supplied to the terminal 21. The signal B _CPU supplied to this terminal 21 is CP
It is sent to the U monitor circuit 22. The CPU monitor circuit 2
2 is supplied with the output of the register 23. Also, this C
The output of the PU monitor circuit 22 is supplied to one input terminal of a 2-input OR (logical sum) gate 32. 2 inputs O
The output of the register 24 is supplied to the other input terminal of the R gate 32. The output terminal of the 2-input OR gate 32 is connected to the reset input terminal of the timer 33. The output of the register 34 is also supplied to the timer 33. Further, the output of the timer 33 (timeout signal T _OUT ) is sent to the pulse generator 35, and the output terminal of the pulse generator 35 is connected to the output terminal 36 of the configuration of the second specific example.

Here, the register 34 and the OR gate 3 are
2 is a configuration for determining whether to enable the operation of the abnormality detection circuit of the second specific example. The pulse generator 35 generates a pulse when the supplied signal is, for example, "H". Therefore, for example, when the output of the register 24 is "H" (the reset signal is active "H"), the timer 33 is always in the reset state. Therefore, the pulse generator 3 at this time is
No pulse is generated from 5 and the abnormality detection signal UD _OUT is not output from the output terminal 36.

FIG. 4 shows a timing chart of the operation of the second specific example circuit.

In FIG. 4, the CPU monitor circuit 22 detects a trigger condition and a monitor result within a fixed time (here, a time shorter than the time until the count check TM in the timer 33 reaches the value T). If a pulse is generated (a pulse is generated at the output M _OUT of the CPU monitor circuit 22) on the assumption that the two match, the timer 33 is reset before the time-out (before the time-out signal T _OUT becomes “H”). However, within the above fixed time (count value C
When the pulse of the output M _OUT is not output before T reaches the value T), the timer 33 times out (timeout signal T _OUT is “H”). At this time,
From the pulse generator 35, the time-out signal T _{OUT is output.}
A pulse is output as the abnormality detection signal UD _OUT on the basis of "H".

Specifically, a certain address is assigned to the CP
If the execution condition of the U10 is set as the trigger condition, the pulse of the abnormality detection signal UD _OUT is not output from the specific example configuration if the CPU 10 always executes the certain address within a certain time. However, when the CPU 10 runs out of control and does not execute the address within a fixed time, the pulse of the abnormality detection signal UD _OUT is output.

This has the same function as the watchdog timer described above. However, in the second specific example of the present embodiment, since there are various trigger conditions, the abnormality detection function is higher than the watchdog timer.

FIG. 5 shows the configuration of the third specific example. The configuration of the third specific example is a configuration in which two CPU monitor circuits (monitor circuits 42, 42) and a timer 50 are combined, and one of the CPU monitor circuits (for example, the circuit 42) starts the timer 50. The other CPU monitor circuit (for example, the circuit 43) stops the timer 50.

In the structure of FIG. 5, the signal B _CPU of the bus of the CPU 10 shown in FIG. 1 is supplied to the terminal 41. The signal B _CPU supplied to the terminal 41 is sent to the two CPU monitor circuits 42 and 43. C above
The output of the register 44 is supplied to the PU monitor circuit 42, and the output of the register 45 is supplied to the CPU monitor circuit 43. The output MA of the CPU monitor circuit 42 is supplied to the set input terminal of the flip-flop 46, and the output MB of the CPU monitor circuit 43 is supplied to the reset input terminal of the flip-flop 46. It has become so. Further, the output MA of the CPU monitor circuit 42 is the check circuit 4 when the timer is activated.
8 and the output MB of the CPU monitor circuit 43 is also supplied to the check circuit 51 when the timer is stopped. The output FF _OUT of the flip-flop 46 and the enable signals B0 and B1 from the register 47 are also supplied to these check circuits 48 and 51.

The output MA of the CPU monitor circuit 42 is supplied to the reset input terminal of the timer 50, and the output FF _{OUT of the} flip-flop 46 is supplied to the enable input terminal. It is like this. Further, the output of the register 49 is also supplied to the timer 50.

The check circuit 48 at the time of starting the timer is flip-flop 46 when the register 47 is enabled (enable signal B0).
When the pulse is supplied from the CPU monitor circuit 42 in the state of "H" (the state where the timer 50 is operating), the output DE
Set T1 to "H".

A check circuit 51 for stopping the timer is also provided.
Is the flip-flop 46 when it is enabled by the register 47 (enable signal B1).
Is “L” (timer 50 is stopped) and a pulse is supplied from the CPU monitor circuit 43, output DET
Set 2 to "H".

The output DET1 of the check circuit 48,
The output DET2 of the check circuit 51 and the timer 5
The output DET3 from the timeout output terminal of 0 is supplied to the pulse generator 52, respectively.
The output terminal of the pulse generator 52 is connected to the output terminal 53 of the configuration of the third specific example, and the pulse as the abnormality detection signal UD _OUT is output from the pulse generator 52.

In the structure of the third embodiment shown in FIG. 5, the output FF of the flip-flop 46 is initially set.
_OUT is "L", and the timer 50 at this time is in a stopped state.

The registers 44 and 45 are the above-mentioned C
The register 49 is a register for giving the trigger conditions of the PU monitor circuits 42 and 43, and the register 49 is for setting the timeout value of the timer 50. Further, the register 47 is provided with the outputs DET1,
This is a register for controlling DET2. Further, the pulse generator 52 outputs the outputs DET1 and DET2 from the check circuits 48 and 51 and the output DE from the timer 50.
It is a circuit that generates a pulse (that is, an abnormality detection signal UD _OUT ) at the rising edge of each of the three types of signals T3.

FIG. 6 shows a timing chart of the operation of the configuration of the third specific example shown in FIG.

In the timing chart of FIG. 6,
The timer 5 is activated by the pulse (pulse of the output MA) output from the CPU monitor circuit 42 when the monitor result of the CPU monitor circuit 42 matches the trigger condition.
0 is reset. At this time, the flip-flop 46 is set. As a result, the timer 50 is enabled and the count value CT is incremented from 0.

Count value C of the counter of the timer 50
Within the time-out period until T reaches the value T, the CP
In the U monitor circuit 43, the monitor result coincides with the trigger condition, and the CPU monitor circuit 43 outputs a pulse (output MB
Pulse) of the flip-flop 46
Are reset, which disables the timer 50.

That is, when the timer 50 is started by the pulse of the output MA from the CPU monitor circuit 42 and no pulse is generated in the output MB from the CPU monitor circuit 43 within the time-out period, the timer 50 times out. (Time-out signal T _OUT becomes “H”), and a pulse (abnormality detection signal UD _OUT ) indicating that the abnormality has been detected is generated from the pulse generator 52.

Here, in the circuit of the third specific example, it is possible to detect two kinds of abnormal states other than the timeout of the timer 50.

These two types of abnormal states are the case where the timer 50 is operating when a pulse is generated at the output MA of the CPU monitor circuit 42 and the CPU monitor circuit 4 described above.
3 is a case where the timer 50 is stopped when a pulse is generated in the output MB, and these two types of abnormal states are detected by the check circuits 48 and 51. When these two types of abnormal states are detected by these check circuits 48 and 51, the outputs DET1 and DET2 from these check circuits 48 and 51 become "H".

In other words, in the circuit of the third specific example, the pulse of the output MA of the CPU monitor circuit 42,
The case where the pulse of the output MB of the CPU monitor circuit 43 does not occur alternately is detected as an abnormal state.

Since the outputs DET1 and DET2 from the check circuits 48 and 51 are not always necessary, the timer 5 is set by setting the register 47.
Check circuit 4 when 0 is started and when timer 50 is stopped
It is also possible to disable the pulse output at 8,51.

As described above, in the abnormality detecting circuit of the third specific example, the time from the trigger condition of the CPU monitor circuit 42 to the trigger condition of the CPU monitor circuit 43 is monitored and the order of the two trigger conditions is set. It can be monitored.

Furthermore, it is also possible to realize the three functions shown in the configurations of the above-mentioned first, second and third concrete examples with one configuration. The configuration of the fourth specific example is shown in FIG.
In FIG. 7, the same components as those in FIG. 5 described above are designated by the same reference numerals, and detailed description thereof will be omitted.

In the configuration of the fourth specific example shown in FIG. 7, the register 55 outputs the output B2 together with the enable signals B0 and B1 of the register 47,
This output B2 is the output FF of the flip-flop 46.
_OUT is supplied to the other input terminal of the OR gate 56, which is supplied to one input terminal. This OR
The output of the gate 56 is supplied to the enable input terminal of the timer 50.

Here, in the fourth specific example circuit, when the output B2 of the register 55 is, for example, "L", the two CPU monitor circuits 42 and 43 as in the third specific example configuration described above. And the timer 50 described above operate as an abnormality detection circuit. Further, the circuit of the fourth specific example is
When the output B2 is, for example, "H", the CPU monitor circuit 42 and, for example, the timer 50 are used to operate as an abnormality detection circuit by the combination of the CPU monitor circuit and the timer as in the second specific example configuration described above. .. Furthermore, this 4th
The specific example circuit also realizes an abnormality detection circuit by the monitor circuit of the CPU 10 alone using only the CPU monitor circuit 43 as in the configuration of the first specific example described above.

Further, the abnormality detecting circuits of the respective concrete examples as described above can be used independently, but by monitoring the CPU 10 by combining them as shown in the configuration of the fifth concrete example of FIG. Functions can be very powerful.

In FIG. 8, the terminal 61 is connected to the terminal shown in FIG.
The signal B _CPU of the bus of the CPU 10 shown in FIG. The signal B _CPU supplied to this terminal 61 is used for the N abnormality detection circuits 62 ₁ and 62 _{1 as} in the above-described specific examples.
₂ , ..., 62 _N respectively. Each of the abnormality detecting circuit 62 _1, 62 _2, ..., an output of 62 _N, N
By using the OR gate 65 of the input,
The abnormality detection signal UD _OUT, which is a very strong monitoring result, is output from the output terminal 66 of the configuration of the specific example.

That is, in the fifth specific configuration, for example, it is possible to monitor the operation in which the trigger condition B is generated next to the certain trigger condition A and the trigger condition C is generated next. ..

The CPU abnormality detecting method of this embodiment can be used, for example, in the following cases.

That is, as an example of this use, for example, in the case of transmitting data in packet data communication, the CPU will runaway (or malfunction due to a bug or the like) after the data transmission is started, and the transmission will not end. Things must be avoided.

In such a case, when the present invention is used, the address of the routine executed at the start of transmission is detected by, for example, the CPU monitor circuit 42 of FIG.
And the address of the routine executed at the end of transmission is detected by the CPU monitor circuit 43 and the timer 5
If 0 is set to stop, even if there is an error in the software and the transmission does not stop (this will be detected by the timer 50 timing out if the transmission stop routine is not executed within a certain time). Will be able to.

Since the packet transmission is performed irregularly, it cannot be detected by the conventional watchdog timer described above.

FIG. 9 shows the flow of a program when this usage example is applied to, for example, the specific configuration of FIG. 5 described above.

In FIG. 9, in the transmission start routine, the timer 50 is started by triggering the execution address. After that, the timer 50 operates, and in the transmission stop routine, the execution address is triggered to stop the timer 50.

In the case of the example of FIG. 9, the trigger conditions of the CPU monitor circuit are as follows.
That is, when a specific routine is executed, the CPU
Trigger on the execution address of the instruction. Further, when data is read from the memory of a specific address (not only 1 byte but a range can be specified) or data is written in the memory of a specific address, a trigger is applied. It is also possible to use the contents of the data at that time as a condition. Furthermore, data can be read from the I / O port of a specific address (not only 1 byte but also the range can be specified) or I / O of a specific address
When writing data to the port, trigger it. It is also possible to use the contents of the data at that time as a condition. In addition, a trigger is applied when an interrupt occurs.

From the above, the CP of this embodiment is
According to the runaway detection method of U and each specific example circuit thereof, CP
By combining the U bus, the circuit for monitoring the control signal, and the timer, a complicated check which cannot be performed by the above-described conventional watchdog timer becomes possible. In addition, the hardware monitors the CPU bus and control signals to determine
Unlike the conventional watchdog timer, there is no work for the CPU to clear the timer, so the CPU is not burdened at all.

[0060]

As described above, in the CPU runaway detection method of the present invention, the timer is started by detecting that the transmission routine has started, and the transmission routine does not end even if the timer elapses for a predetermined time. If this is detected, a reset signal is forcibly supplied to the CPU, so that a complicated check can be performed and CPU runaway can be detected without imposing any burden on the CPU. Become.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic runaway detection circuit for explaining a CPU runaway detection method according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a configuration of a first specific example for implementing the method of the embodiment of the present invention.

FIG. 3 is a block circuit diagram showing the configuration of a second specific example for implementing the method of the embodiment of the present invention.

FIG. 4 is a timing chart of the operation of the second specific example configuration.

FIG. 5 is a block circuit diagram showing a configuration of a third specific example for implementing the method of the embodiment of the present invention.

FIG. 6 is a timing chart of the operation of the third specific example configuration.

FIG. 7: First, second, third for realizing a method according to an embodiment of the present invention
It is a block circuit diagram which shows the 4th specific example structure which combined the specific example structure of this.

FIG. 8 is a block circuit diagram showing a fifth specific example configuration in which a plurality of specific example circuits of the embodiment of the present invention are combined.

FIG. 9 is a diagram for explaining the flow of a program in the third specific example configuration for implementing the method of the embodiment of the present invention.

FIG. 10 is a block diagram showing an abnormality detection circuit of a conventional CPU.

[Explanation of symbols]

 10 ... CPU 20 ... Abnormality detection circuit

Claims (1)

[Claims] 1. A method for detecting runaway of a CPU for controlling a packet data communication circuit in which data transmission is performed irregularly, wherein a timer is started by detecting the start of a transmission routine, and the timer is activated. If it is detected that the transmission routine does not end even after the lapse of a predetermined time, the above CP
A method for detecting runaway of a CPU, characterized in that a reset signal is forcibly supplied to U.