JPH05110002A - Complementary type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize a complementary type semiconductor integrated circuit device which is hardly subjected to latch up by a method wherein a guard ring region is provided between the internal region and the external region and also outside the external region, carrier is absorbed from the external region and the leakage to the internal region is reduced. CONSTITUTION:In the cross-sectional diagram separately mentioned, a guard ring region 11 is provided between the internal region 10, where an inner circuit is formed, and the external region 12 where an input-output circuit and the like are formed on a P-type silicon substrate 20. Also, a guard ring region 13 is provided on the outside of the external region 11. These guard ring regions are composed of the P<+> type region 28 or 29 which is connected to the earthing wire and the N-type well region 21 or 22 which is connected to a VDD or the earthing wire.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a complementary semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Complementary semiconductor integrated circuit devices (hereinafter referred to as CMOs)
S-IC) is a CMOS-IC shown in FIG. 4, for example.
As in the example of the sectional view, the N well region 40 is formed on the P type semiconductor substrate 20, and the P channel M is formed in the N well region 40.
A CMOS inverter circuit is provided by providing an OS transistor and an N-channel MOS transistor on the P-type semiconductor substrate 20.

This structure is represented by Q1, Q2, R1 and R in FIG.
It can be represented by an equivalent circuit shown by 2. In other words, it is the same as the thyristor, and it is well known that it causes latch-up. In the example of FIG. 4, when carriers (electrons) are injected from the external region 12 where an input / output circuit is formed, the carriers reach the N well 40 and flow from the N ⁺ region 41 to the V _DD terminal. At this time, a potential drop occurs in the resistance R1 of the N-well, and this potential gives a bias between the base and emitter of the transistor Q1, and when the transistor Q1 becomes conductive, the transistor Q2 also becomes conductive and latches up.

Therefore, in JP-A-61-280648,
As shown in FIG. 3, a guard ring region including a high-concentration impurity region of one conductivity type and a well region of the opposite conductivity type was provided between the outer region and the inner region. That is, as shown in FIG.
In (b), the guard ring region 11 is provided between the inner region 10 and the outer region 12 on the P-type silicon substrate. The guard ring region 11 is composed of a P ⁺ type region 29 connected to the ground and an N type well region 21 connected to V _DD or the ground. Since this guard ring absorbs the carriers injected from the outer region, the number of carriers reaching the inner region is reduced and it is difficult to latch up in the inner region. FIG. 3A shows the case where holes are injected from the external region, and the holes are absorbed in the P ⁺ region 29. FIG. 3B shows the case where electrons are injected from the external region, and the electrons are absorbed in the N-type well region 21.

[0005]

However, the injection amount of carriers from the external region increases, and, for example, the external region 1
When the injection amount is 100 mA or more from a location, the guard ring alone cannot absorb the amount, and latch-up easily occurs. Therefore, there is a problem that it is necessary to pay sufficient attention to how to take the N well and the substrate potential in the internal region.

[0006]

According to the present invention, a complementary semiconductor integrated circuit having, on a semiconductor substrate of one conductivity type, an internal region in which an internal circuit is formed and an external region in which an input / output circuit and the like are formed. In the device, a complementary semiconductor having a guard ring region composed of a high-concentration impurity region of one conductivity type and a well region of the opposite conductivity type between the inner region and the outer region and outside the outer region. Obtain an integrated circuit device.

[0007]

EXAMPLES Next, examples of the present invention will be described.

FIG. 2 is a plan view of the complementary semiconductor integrated circuit device of the present invention. Internal region 10 in which internal circuit is formed
And a guard ring region 11 having a width of about 20 μm is formed between the outer region 12 and the external region 12 in which the input / output circuit is formed, and the guard ring region 13 is also formed outside the outer region 12. 2 (a) and 2 (b) are sectional views showing the vicinity of these guard rings.

In FIG. 2A, a P type silicon substrate 2 is provided.
0, there is a guard ring region 11 between the inner region 10 and the outer region 12. The guard ring region 11 is composed of a P ⁺ type region 29 connected to ground and an N type well region 21 connected to V _DD or ground. A guard ring 13 having the same structure as the guard ring region 11 is also arranged outside the outer region 12.

In such a structure, when holes are injected from the external region 12, the injected holes are absorbed by both the P ⁺ regions 28 and 29 of the guard ring region. Therefore,
The number of holes flowing in the direction of the internal region is about half that in the conventional example of FIG. The number of holes reaching the internal region is also reduced by that amount, which makes latch-up difficult.

FIG. 2B also has the same structure as that of FIG. This figure shows the case where electrons are injected from the external region 12. The injected electrons are the N-type region 2 of the guard ring region.
It is absorbed by both 1 and 22. Therefore, the number of electrons flowing in the direction of the internal region is about half that in the conventional example. The number of electrons reaching the internal region is also reduced by that amount, which makes latch-up difficult.

[0012]

As described above, by providing the guard ring region between the inner region and the outer region and outside the outer region, both guard rings absorb the carriers from the outer region and reach the inner region. Since the leakage of is reduced, it is possible to realize a complementary semiconductor integrated circuit device which is extremely unlikely to latch up. Also, since the layout work of the guard ring can be performed regardless of the internal area, especially,
There is a great merit in workability in the layout using a computer.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

2 (a) and 2 (b) are enlarged views in the vicinity of the guard ring region of FIG. 1, and are cross-sectional views showing different application examples.

FIG. 3A and FIG. 3B are enlarged views of the vicinity of a guard ring region of a conventional example, and are cross-sectional views showing different examples.

FIG. 4 is a sectional view of a conventional CMOS-IC.

[Explanation of symbols]

10 internal region 11, 13 guard ring region 12 external region 20 P type silicon substrate 12, 22, 23 N type well region 25, 26, 30 N ⁺ type region 27, 28, 29 P ⁺ type region

Claims (1)

[Claims] 1. A complementary semiconductor integrated circuit device having an internal region in which an internal circuit is formed and an external region in which an input / output circuit or the like is formed on a semiconductor substrate of one conductivity type. A complementary semiconductor integrated circuit device, characterized in that a guard ring region consisting of a high-concentration impurity region of one conductivity type and a well region of opposite conductivity type is provided between the external region and outside the external region.