JPH05109274A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce power current consumption and a pattern occupancy area by connecting the substrate of a memory cell to zero potential. CONSTITUTION:The drain electrode D of (n) channel and a source electrode S are formed on the P type substrate P, and a gate electrode G is formed upwards of the electrodes D, S and the substrate P is grounded. Coupling capacitance Cjs are formed between the electrode D and the substrate P and between the electrode S and the substrate P. Since the substrate P is made a grounded potential in the DRAM, the write potential VS of (0) restore higher than the grounded potential is applied to the electrode S, and by lowering a back gate potential VSUb than the potential VSN of the electrode S, data is written to a capacitor C1 at the higher potential than the grounded potential. Then, since a condition is similar as an occasion connecting a substrate bias generating circuit to the substrate P, the capacitance Cj is reduced and leakage current is suppressed by heightening a threshold value voltage by a back gate effect. Thus, the power current consumption and the pattern occupancy area are reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
More specifically, the present invention proposes a semiconductor memory device that consumes less current and occupies less pattern area.

[0002]

2. Description of the Related Art DR which is a dynamic semiconductor memory device
The AM is configured as shown in FIG. 1, for example. n-channel MOS transistor (hereinafter referred to as transistor)
The gates of Q ₁ , Q ₂ ... Q ₆ are individually connected to word lines WL ₁ , WL.
₂ ... WL ₆ , and the transistor Q ₁ is connected via a capacitor C ₁ to a cell plate CPL which gives a cell plate potential. Capacitor C ₂ (C ₄ )
, Each end of the series circuit of the transistors Q ₂ (Q ₄ ), Q ₃ (Q ₅ ) and the capacitor C ₃ (C ₅ ) is connected to the cell plate CPL.

Transistor Q ₆ is connected to cell plate CPL via capacitor C ₆ . Transistor Q
The common connection between ₂ (Q ₄ ) and Q ₃ (Q ₅ ) is the bit line
It is connected to BL. The bit line BL is set to "0" via the n-channel transistor Q ₇ which is a part of the sense amplifier.
The restore write potential V _S is applied. When the power supply potential is V _CC , the cell plate CPL is supplied with a reference potential of 1/2 V _CC , which is a half of the reference potential.

[0004] The DRAM, for example, the word line WL ₂ raised by applying the gate potential V _G to the gate of the transistor Q ₂ is turned on by selecting a transistor Q _2. Further, the transistor Q _{7 of the} sense amplifier is turned on to give the write potential V _S of “0” restoration to the bit line BL, and the bit line BL
To the bit line potential V _BL . Then, the bit line potential V _{BL is applied} to the storage node of the capacitor C ₂ which is connected in series with the turned-on transistor Q ₂ to set the storage node of the capacitor C ₂ to the storage node potential V _SN and 0 V is applied to the capacitor C ₂ . Write the data of.

FIG. 2 is a schematic enlarged sectional view of a memory cell. An n-channel drain electrode D and an n-channel source electrode S are formed on a P-type substrate (P well) P, and the drain electrode D and the source electrode are between the drain electrode D and the source electrode S. Gate electrode G above S
Are formed. Junction capacitors C _j and C _j are formed between the drain electrode D and the P-type substrate P and between the source electrode S and the P-type substrate P.

In the memory cell, it is necessary to reduce the junction capacitance C _j in order to speed up data transfer, and in order to suppress the leak current flowing between the drain electrode D and the source electrode S, the back gate effect is required. The threshold voltage V _t
Is required to be higher, and therefore the potential of the P-type substrate P is made lower than the potential of the source electrode S. Therefore, the P-type substrate P is connected to the substrate bias generation circuit BI that lowers the back gate potential V _SUb of the P-type substrate P. And P
The potential difference V _BS between the mold substrate P and the source electrode S is V _BS = V _SUb −V _BL = V _SUb −V _SN (1)

The structure of such a substrate bias generating circuit BI is described in, for example, "Bifukan" published by Baifukan on April 25, 1989.
LSI Design "Supervised by Takuo Sugano, edited by Tetsuya Iizuka, No.189-190
Shown on the page.

On the other hand, page 55 of the March 1989 issue of the NIKKEI MICRODEVICES magazine states that 16M DRAM, which has an extremely large storage capacity.
The cross-sectional structure of the triple well is shown. This 16M DRAM
Separates the well of the memory cell from the well of the peripheral circuit in order to prevent a phenomenon similar to latch-up that occurs when the well of the memory cell is in a floating state at power-on. The substrate bias is applied, and the well of the peripheral circuit is applied with the ground potential.

[0009]

[SUMMARY OF THE INVENTION With the employment, the back gate potential V _SUb must be lower than the constantly source potential regardless of the operating of the memory cell and the back gate potential V _SUb by the substrate current flowing into the substrate Since the substrate bias generating circuit BI is always operated in order not to raise the voltage, the standby current continues to flow and the current consumption is large. Further, since the substrate bias generating circuit BI is provided, the pattern occupying area becomes large.

On the other hand, even in the case of the triple well structure, there is a problem that the substrate bias generating circuit is required, and moreover, the process steps of the memory cell are increased and the cost is inevitably increased. In view of such a problem, it is an object of the present invention to provide a semiconductor memory device that consumes less current and occupies a smaller pattern area.

[0011]

In a semiconductor memory device according to the present invention, a potential difference is applied between a substrate of a memory cell and a source electrode of a transistor forming the memory cell to reduce the junction capacitance. In such a semiconductor memory device, the substrate of the memory cell should be connected to zero potential.

[0012]

The substrate of the memory cell is set to the zero potential, and the source electrode of the transistor forming the memory cell is given a write potential of "0" restore higher than the zero potential so that the substrate potential is the potential of the source electrode. Lower. This reduces the junction capacitance. Therefore, the substrate bias generating circuit for lowering the substrate potential is not required, and the current consumption and the pattern occupation area are reduced.

[0013]

The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. FIG. 3 is a configuration diagram showing a main part of a DRAM which is a semiconductor memory device according to the present invention. Capacitor C ₂ and n channel
Each end of the series circuit of the MOS transistor Q ₂ , the n-channel MOS transistor Q _3, and the capacitor C ₃ is connected to the cell plate CPL. The n-channel MOS transistor Q ₄ is connected to the cell plate CPL via the capacitor C ₄ . The common connection between the transistors Q ₂ and Q ₃ is connected to the bit line BL. Transistor Q ₂ ,
The back gate of Q ₃ is grounded. The bit line BL is an n-channel MOS transistor Q which is a part of the sense amplifier.
_It is connected via ₇ to the write potential line V SL to which the write potential V _S for “0” restoration is applied. Transistor Q
The gates of ₂ , Q ₃ and Q ₄ are connected to the word lines WL ₂ , WL ₃ and WL ₄ , respectively.

[0014] The DRAM, for example, the word line WL ₂ raised by applying the gate potential V _G to the gate of the transistor Q _2, is turned on by selecting a transistor Q _2. Also, the transistor Q _{7 of the} sense amplifier is turned on to turn on the bit line BL.
A write potential V _S for "0" restoration higher than the ground potential is applied to the bit line BL to set the bit line BL to the bit line potential V _BL . Then, the bit line potential V _{BL is applied} to the storage node of the capacitor C ₂ which is connected in series with the turned-on transistor Q ₂ to set the storage node of the capacitor C ₂ to the storage node potential V _SN ,
₂ , write potential V of "0" restore higher than ground potential
_{Write the} data by _S.

FIG. 4 is a schematic enlarged sectional view of the memory cell. An n-channel drain electrode D and an n-channel source electrode S are formed on a P-type substrate (P well) P, and the drain electrode D and the source electrode are between the drain electrode D and the source electrode S. Gate electrode G above S
Are formed. The P-type substrate P is grounded. Junction capacitors C _j and C _j are formed between the drain electrode D and the P-type substrate P, and between the source electrode S and the P-type substrate P. Since this DRAM has the P-type substrate P at the ground potential, the source electrode S has "0" higher than the ground potential.
The write potential V _S for restore is _applied to lower the back gate potential V _SUb from the potential V _SN of the source electrode S, and data is written in the capacitor C ₂ at a potential higher than the ground potential.

Therefore, the same state as when the substrate bias generating circuit is connected to the P-type substrate P can be obtained, the junction capacitance C _j can be reduced, and the threshold voltage can be increased by the back gate effect to suppress the leak current. ..

FIG. 5 shows a conventional DRAM and a DRAM according to the present invention.
It is explanatory drawing which compared the capacitor electric potential change with and. The left side shows the case of the conventional DRAM, and the right side shows the case of the DRAM of the present invention. In the conventional DRAM, the back gate potential V _{SUb of} the P-type substrate P is lowered to −2 V by the substrate bias generating circuit BI, and the write potential V _S of “0” restore of 0 V is applied to the bit line BL. , Capacitor C
_In case of “L” data, 0V is written in 2 and “H” is written.
In case of the data of, 3V is written. Also, the gate potential V
_G requires about 5.5 V plus 3 V plus the threshold voltage V _t1 , as shown by the dashed line.

On the other hand, in the DRAM of the present invention, the P-type substrate P is
Since it is fixed to the ground potential of V, the write potential V _S of “0” restore of 2 V, which is higher than the ground potential, is applied to the bit line BL, so that the capacitor C ₂ becomes
2V is written in the case of "L" data, and 5V is written in the case of "H" data. The gate potential V _G is
Approximately 6.5 V obtained by adding the threshold voltage V _t2 to 5 V as shown by the broken line
Need.

In this way, even if the write potential V _S for "0" restoration higher than the ground potential is applied to the bit line BL,
Data can be written like DRAM. Therefore, a substrate bias generation circuit for lowering the back gate potential V _SUb of the P-type substrate P _{below the} potential of the source electrode S is not required, and the standby current does not flow, so that the consumption current can be reduced and the pattern occupying area can be reduced. .. In this embodiment, the case of writing the data to the capacitor C ₂ has been described, but the data can be written to the other capacitors in the same manner, and the data can be similarly read out.

[0020]

As described above in detail, the semiconductor memory device of the present invention does not have a substrate bias generation circuit for lowering the potential of the substrate of the memory cell below the source potential. It can be reduced. Further, the area occupied by the pattern can be reduced, and the size can be reduced. Further, when the well of the memory cell and the well of the peripheral circuit are separated from each other like a large capacity DRAM, the number of process steps is increased and the cost is increased, but such an increase in cost does not occur. And so on.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a DRAM.

FIG. 2 is a schematic enlarged sectional view of a DRAM memory cell.

FIG. 3 is a configuration diagram of a main part of a semiconductor memory device according to the present invention.

FIG. 4 is a schematic enlarged cross-sectional view of a memory cell of a semiconductor memory device according to the present invention.

FIG. 5 is an explanatory diagram showing a potential change of each memory cell of the conventional DRAM and the semiconductor memory device of the present invention.

[Explanation of symbols]

Q ₂ , Q ₃ , Q ₄ n-channel MOS transistors C ₂ , C ₃ , C ₄ Capacitor BL Bit line WL ₂ , WL ₃ , WL ₄ Word line CPL Cell plate VSL Write potential line P P type substrate (P well) C _j junction capacity

Claims (1)

[Claims] 1. A semiconductor memory device in which a junction capacitance is reduced by providing a potential difference between a substrate of a memory cell and a source electrode of a transistor forming the memory cell. A semiconductor memory device characterized in that the substrate is connected to zero potential.