JPH05108343A - Musical signal arithmetic processor - Google Patents

Abstract

PURPOSE:To attain an effective programming operation and also to reduce the hardware related to a data transfer instruction. CONSTITUTION:The microprogram stored in a microprogram memory 10 is carried out by a control part based on a prescribed clock. A coefficient memory 11 stores the prescribed coefficients like B2 and B1, etc. Then a temporary memory 12 stores the prescribed data like DO-1, Di0, etc. These coefficients and data undergo the arithmetic processing through an ALU 2 with an instruction of the control part. Under such conditions, the date read out of the memory 12 are temporarily stored in a D register 13 and also supplied to a selector 14. At the same time, the arithmetic result of the ALU 2 is also supplied to the selector 14. The control part controls the selector 14 based on the microprogram and writes the data or the arithmetic result into a prescribed address of the memory 12. Thus the data transfer instruction can be omitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tone signal arithmetic processing unit suitable for use as a sound source for generating tone and imparting effects to tone.

[0002]

2. Description of the Related Art In an arithmetic processing unit (DSP) used for generating musical tones and imparting effects to musical tones, an arithmetic processing unit (ALU) performs various arithmetic operations according to a micro program. FIG. 8 is a block diagram showing a configuration of a part of a conventional arithmetic processing device, particularly, a main part near the arithmetic processing unit. In this figure, the DSP is a control unit (not shown) that uses a coefficient memory 1 according to a microprogram.
The coefficient is read from the multiplier 2a of the arithmetic processing unit 2
Supply to one input terminal.

Similarly, the data and the calculation result obtained in the previous process are read from the temporary memory 3 and supplied to the other input end of the multiplier 2a of the calculation processing unit 2. The data multiplied by the multiplier 2a is
It is supplied to one input terminal of the adder 2b. This adder 2
b adds the data stored in the R register 2c and the data from the multiplier 2a, and adds this to the R register 2c.
Store to. The data stored in the R register 2c is
At the next timing, the data is supplied to the adder 2b and stored in the temporary memory 3 described above. The data stored in the temporary memory 3 is read by the multiplier 2a at a predetermined time according to the microprogram and used for the calculation.

In such a DSP, as shown in FIG.
When the next operation of the IIR filter 5 is performed, a series of processing including the following steps is performed. In this figure, A0 to A2 and B1 and B2 are multiplication coefficients in the multiplier, and T1, T2, T5, T6 and T7 are
This is signal data in each signal path. In this case, it is assumed that the input data is written in the buffer T5 of the temporary memory 3 shown in FIG. 8 and the output data is stored in T7. Step 1 ... LDR T5 Step 2 ... MAC T1, B1 Step 3 ... MAC T2, B2 Step 4 ... MUL T1, A1 STR T6 Step 5 ... MAC T2, A2 Step 6 ... MAC T6, A0 Step 7 ...... STR T7 Step 8 ...... TRF T1, T2 Step 9 ...... TRF T6, T1

First, in step 1, the data stored in the buffer T5 is loaded into the R register 2c. In step 2, the data in the buffer T1 is multiplied by the coefficient B1 and cumulatively added to the data loaded in step 1 in the R register 2c. Next, in step 3, the buffer T
The data of 2 is multiplied by the coefficient B2, and the R register 2c performs cumulative addition with the result of cumulative addition in step 2 above. In step 4, the data in the buffer T1 and the coefficient A1 are multiplied,
At the same time, the result of step 3 stored in the R register 2c is stored in the buffer T6 of the temporary memory 3.

Then, in step 5, the data in the buffer T2 and the coefficient A2 are multiplied and cumulatively added in the R register 2c. Next, in step 6, the data in the buffer T6 (result of step 4) is multiplied by the coefficient A0, and the R register 2c performs cumulative addition. In step 7, the result of step 6 is stored in the buffer T7 of the temporary memory 3. In step 8, the data in the buffer T1 is transferred to the buffer T2 to prepare for the process of step 3 in the next stage. Then, in step 9, the data in the buffer T6 is transferred to the buffer T1 to prepare for the process of step 2 in the next stage. As described above, the conventional tone signal arithmetic processing apparatus requires nine steps of processing.

[0007]

By the way, the above-mentioned musical tone signal arithmetic processing unit requires the transfer command (TRF) in steps 8 and 9 which is not related to the arithmetic operation.
The number of processing steps increased, which caused a problem that efficient programming could not be performed.

The present invention has been made in view of the above-mentioned circumstances, and provides a tone signal arithmetic processing apparatus capable of efficient programming, reducing the hardware related to transfer instructions, and reducing the cost. It is an object.

[0009]

In order to solve the above-mentioned problems, according to the present invention, storage means for storing a plurality of data, and the data read from the storage means are temporarily stored. , Temporary storage means for outputting the temporarily stored data to the storage means again, arithmetic means for performing arithmetic operation on the data read from the storage means in accordance with a predetermined program, and storage in the storage means And a control means for reading the stored data and writing the data output from the temporary storage means to a predetermined address of the storage means.

[0010]

The data stored in the storage means is read out by the control means and stored in the temporary storage means, and the arithmetic means performs arithmetic processing according to a predetermined program. The data temporarily stored in the temporary storage means is written in a predetermined address of the storage means by the control means.

[0011]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this figure, a micro program memory 10 stores a micro program for controlling various processes in the DSP. This microprogram is executed by a control unit (control means) (not shown) according to a predetermined clock, and various control signals are output to each unit. In the case of this example (IIR filter), five coefficients B2, B1, A2, A are stored in the coefficient memory 11.
1 and A0 are stored. These coefficients are supplied to one input terminal of the multiplier 2a of the ALU 2 according to the instruction of the microprogram.

Next, the temporary memory 12 is a two-port memory in which reading and writing can be specified separately, and when reading and writing are simultaneously performed on the same address, the data before writing is written. It is designed to read. In the case of this example, the temporary memory 12 stores four data DO-1, Di0, D-2 and D-1 in the buffers T3 to T0, respectively. These data are supplied to the other input terminal of the multiplier 2a of the ALU 2 and to the D register 13 according to the instruction of the microprogram. The D register 13 temporarily stores data and is supplied to one input terminal S1 of the selector 14 in accordance with a microprogram command. Also,
At the other input terminal S0 of the selector 14, the data stored in the R register 2c of the ALU 2 is connected to the common data bus DB2.
It is designed to be supplied via. Selector 14
Responds to the select control signal supplied to the select terminal S, and supplies either data supplied to the input terminal S0 or S1 to the temporary memory 12 via the common data bus DB1. The configuration of the ALU 2 described above is the same as that of the conventional DSP described above.

Next, the IIR of the DSP having the above-mentioned configuration
The calculation operation of the filter will be described with reference to the block diagrams of FIGS. First, as shown in FIG. 1, the data Di0 in the buffer T2 is loaded into the D register 13 and the R register 2c. Next, as shown in FIG. 2, the data D-1 of the buffer T0 and the coefficient B1 are multiplied in the multiplier 2a, and this is accumulated in the R register 2c. As a result, the R register 2c stores Di0 + B1 as data.
・ D-1 is stored.

Next, as shown in FIG. 3, the data D-2 of the buffer T1 and the coefficient B2 are multiplied in the multiplier 2a,
This is accumulated in the R register 2c. As a result, R
The register 2c stores data as Di0 + B1 · D-1 + B2.
・ D-2 (hereinafter referred to as D0) is stored. Next, FIG.
As shown in, the data D-1 of the buffer T0 and the coefficient A1 are multiplied by each other in the multiplier 2a, and the content (data D0) of the R register 2c is selected via the common data bus DB2.
Supply to. At this time, since the select control signal is "0", the selector 14 transfers the data D0 to the data bus D.
The data is supplied to the buffer T0 of the temporary memory 12 via B1. In addition, the control unit (not shown) is a temporary memory 1
Since the write address WA of 2 is used as the buffer T0, the data D0 is stored in the buffer T0. Then, the data A1.D- multiplied by the multiplier 2a.
1 is stored in the R register 2c.

Next, as shown in FIG. 5, the data D-2 of the buffer T1 and the coefficient A2 are multiplied in the multiplier 2a,
This is accumulated in the adder 2b and stored in the R register 2c. As a result, A1.D-1 + A2.D-2 is stored as data in the R register 2c. At this time, the control section sets the select control signal to "1" and supplies the previous contents (data D-1) of the D register to the buffer T1 of the temporary memory 12 via the data bus DB1 and also to the temporary memory 12 The write address WA is used as the buffer T1 and is stored in the buffer T1.

Next, as shown in FIG. 6, the data D0 of the buffer T0 and the coefficient A0 are multiplied in the multiplier 2a, and this is accumulated in the adder 2b with the previous contents of the R register 2c, and R is added. Store in register 2c. As a result, the R register 2c stores data as A0.D0 + A1.D-1 +
A2 and D2 are stored. In this case, D0 is D0 = Di0 + B1.D-1 as shown in FIG. 2, so the above data is actually A0.Di0 + A0.B1.D-1 + A0.B2.D-
It becomes 2 + A1 ・ D1 + A2 ・ D-2.

Next, as shown in FIG. 7, the control unit supplies the data DO0 of the R register 2c to the temporary memory 12 through the selector 14 and sets the write address WA of the temporary memory 12 as the buffer T3. Store in buffer T3. This data DO0 becomes output data. The above processing operation is expressed as steps of the microprogram as follows. Step 1 ... LDR T2 Step 2 ... MAC T0, B1 Step 3 ... MAC T1, B2 Step 4 ... MUL T0, A1 STR T0 Step 5 ... MAC T1, A2 STD T1 Step 6 ... MAC T0, A0 Step 7 ... STR T3 Here, STD indicates a store instruction in which the select control signal becomes "1". That is, according to the present embodiment, the arithmetic processing of the IIR filter is completed in a total of 7 steps.

The capacity of the above temporary memory and coefficient memory is not limited. Further, the D register in the embodiment may be appropriately changed in the number of stages and the operation timing according to the structure of the arithmetic processing unit, the number of pipeline stages of arithmetic processing, and the like. Further, the address of the temporary memory may be specified by installing an index register or the like separately. The input / output signal (data) is
Data may be exchanged by separately providing an input / output register or the like.

[0019]

As described above, according to the present invention, the data stored in the storage means is read out by the control means, stored in the temporary storage means, and operated by the operation means in accordance with a predetermined program. On the other hand, the processing is performed, while the data temporarily stored in the temporary storage means is written to the predetermined address of the storage means by the control means, so that efficient programming can be performed and the transfer instruction can be executed. The advantage is that the hardware can be reduced and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention (step 1).

FIG. 2 is a block diagram for explaining the operation of the arithmetic processing according to the embodiment (step 2).

FIG. 3 is a block diagram for explaining the operation of the arithmetic processing according to the embodiment (step 3).

FIG. 4 is a block diagram for explaining the operation of the arithmetic processing according to the embodiment (step 4).

FIG. 5 is a block diagram for explaining the operation of the arithmetic processing according to the embodiment (step 5).

FIG. 6 is a block diagram for explaining the operation of the arithmetic processing according to the embodiment (step 6).

FIG. 7 is a block diagram for explaining the operation of the arithmetic processing according to the embodiment (step 7).

FIG. 8 is a block diagram showing a configuration of a conventional tone signal calculation processing device.

FIG. 9 is a circuit diagram showing a configuration of an IIR filter realized by an example of arithmetic processing of the musical tone signal arithmetic processing apparatus.

[Explanation of symbols]

2 ... Arithmetic processing unit (arithmetic means), 10 ... Micro program memory, 11 ... Coefficient memory, 12 ... Temporary memory (storage means), 13 ... D register (temporary storage means), 14 ... Selector.

Claims (1)

[Claims] 1. Storage means for storing a plurality of data, and temporary storage for temporarily storing the data read from the storage means and outputting the temporarily stored data to the storage means again. Means, an arithmetic means for performing an arithmetic operation on the data read from the storage means in accordance with a predetermined program, and reading the data stored in the storage means and outputting the data output from the temporary storage means. A musical tone signal arithmetic processing apparatus, comprising: a control means for writing to a predetermined address of the storage means.