JPH05108028A - Interlaced scanning circuit - Google Patents

Abstract

PURPOSE:To equalize the operating frequency of a circuit to that of a simple linear sequential driving and to prevent the circuit from increasing in cost by turning ON two switching elements connected to control lines at the same time and changing the combinations of clock signals applied to the control lines. CONSTITUTION:Two among thin film transistors 25, 26, 29, and 30 connected to the control lines 27, 28, 31, and 32 are turned ON at the same time with pulse signals outputted from output terminals Qn and Qn of respective stages of a shift register 21. Therefore, two adjacent lines of a display device can be driven at the same time for the horizontal period of one frame. Further, the combinations of the control signals applied to the control lines are changed by a clock circuit, frame by frame, to change the combinations of two adjacent lines of the display device which are scanned, frame by frame, so double-speed sequential driving is available without increasing the operating frequency of the circuit by twice and a high-definition image display is available.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlace scanning circuit which is used in a liquid crystal display device for displaying an image by a television (TV) signal and interlaces and scans pixels of each line of the liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, NTSC (National T
elevision SystemCommitte
The e) type TV signal has 48 out of 525 scanning lines.
Interlace scanning is performed with 0 lines as the effective display period. That is, as shown in FIG. 9, the 480 scanning lines are divided into a first field 100 and a second field 101 of 240 lines each.
Forty scanning lines are scanned, and in the next second field 101, interlaced scanning is performed so as to fill in the spaces scanned in the first field 100. Then, one screen (frame) is configured by the two fields of the first field 100 and the second field 101, and the TV image is displayed by updating 30 frames per second.

When displaying a TV image on a liquid crystal display device, two methods are known: simple line sequential driving and double speed line sequential driving. In the simple line sequential drive, the scanning lines for each field correspond to the same one line of the liquid crystal panel, and the liquid crystal panel has 240 lines corresponding to the scanning lines as shown in FIG. Then, in the first field 101, each line of 240 scanning lines is sequentially scanned with a positive polarity, and in the next second field, each line of 240 scanning lines is sequentially scanned with a negative polarity. In this simple line sequential drive, the first field 100 and the second field 10
Since one scan produces a signal with one cycle, the alternating frequency is
The frame frequency is 30 Hz, which is the same as the frame frequency, and the number of pixels in the vertical direction is 240 pixels as described above.

However, in the simple line sequential drive, since the scanning lines of the first field 100 and the second field 100 are sequentially driven in correspondence with the same line of the liquid crystal panel, the definition of the TV image is lacking. There is a problem.

On the other hand, as another driving method, there is a method in which the liquid crystal panel is driven every other line in the first field and the lines not driven in the first field are driven every other line in the next second field. As shown in FIG. 11, the liquid crystal panel has a total of 480 lines corresponding to the scanning lines scanned in the first field 100 and the scanning lines scanned in the second field 101. And
In the first field 100, each line of 240 scanning lines is scanned with one polarity, and in the next second field, each line of the other 240 scanning lines is driven with the same polarity. At this time, since the signal of one polarity is driven for each frame, the alternating frequency is 1/2 of the frame frequency.
Of 15 Hz.

However, in this driving method, although the number of pixels in the vertical direction is 480 pixels, since the liquid crystal element of the liquid crystal panel is driven at 15 Hz, the alternating frequency is low and the screen flickers (flicker). However, there is a problem in that the quality of the displayed image deteriorates.

Therefore, in order to prevent the occurrence of flicker on the TV screen by increasing the alternating frequency of the liquid crystal display screen,
A double-speed line sequential drive method has been devised and actually employed by driving what has been driven once per frame twice per frame (once per field). See Handbook HD66300T).

In this double speed line sequential drive, as shown in FIG. 11, the first line and the second line in the first field 100 are driven by the positive polarity in the first half and the second half of one horizontal scanning period,
Hereinafter, the third and fourth lines and the fifth and sixth lines are similarly driven. Next, in the second field, by changing this combination, the first line is driven in the latter half of one horizontal scanning period, and then the second line and the third line are driven in the first half and latter half of the next horizontal scanning period. As described above, in the above double speed line sequential drive, the pixels of each line of the liquid crystal panel are set to 1
Since it is driven once, the alternating frequency can be set to 30 Hz, which is the same as the frame frequency, and the occurrence of flicker can be prevented.

[0009]

However, the above-mentioned prior art has the following problems. That is, in the case of the above-mentioned double speed line sequential drive, it is 2 for each frame.
Since it is driven once (once per field), the number of pixels in the vertical method is 480 pixels, which is twice the number of simple line sequential drive, and the alternating frequency can be set to 30 Hz, which is the same as the frame frequency, and the image quality can be improved. Finer definition is possible. However, in the case of this double-speed line sequential driving, it is necessary to drive two lines of liquid crystal in one horizontal scanning period, so the operating frequency of the interlaced scanning circuit must be doubled.
There is a problem that the cost of the interlaced scanning circuit is significantly increased.

[0010]

Therefore, the present invention has been made in order to solve the above-mentioned problems of the prior art.
The objective is that even if the number of pixels in the vertical direction is 480, high-definition images can be displayed without causing flicker, and the operating frequency of the circuit may be the same as that of simple line sequential driving. An object of the present invention is to provide an interlaced scanning circuit capable of preventing a significant increase in cost.

That is, the interlaced scanning circuit according to the present invention is an interlaced scanning circuit for interlacing scanning pixels of each line of a liquid crystal display device, by shifting two pulse signals from two output terminals of each stage by a predetermined interval. ON / OFF control is performed by a shift register that sequentially outputs and a pulse signal that is output from one output terminal of this shift register, and a clock signal that is applied to the first control line and the second control line is output when it is turned on. ON / OFF control is performed by the first and second switching elements and the pulse signal output from the other output terminal of the shift register, and a clock signal applied to the third control line and the fourth control line is applied. Third and fourth switching elements that output respectively when turned on, and the first to fourth control lines And a clock circuit for sequentially switching and outputting a clock signal applied to each of the shift registers, and the pixels of each line of the liquid crystal display device are controlled by the outputs of the first to fourth switching elements connected to each stage of the shift register. It is configured to perform sequential interlaced scanning.

As the first to fourth switching elements, for example, field effect type thin film transistors are used.

[0013]

In the present invention, of the first to fourth switching elements respectively connected to the first to fourth control lines, two switching elements are pulse output from the output terminals of each stage of the shift register. By turning on at the same time by a signal, two adjacent lines of the liquid crystal display device can be simultaneously driven only during the horizontal scanning period of one frame. Moreover, by changing the combination of the clock signals applied to the first to fourth control lines for each frame by the clock circuit, the combination of two adjacent lines of the liquid crystal display device that scans for each frame is changed. Therefore, double-speed line sequential driving can be performed without doubling the operating frequency of the circuit, and high-definition image display can be performed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to illustrated embodiments.

FIG. 2 shows a liquid crystal display device to which an embodiment of the interlaced scanning circuit according to the present invention is applied.

In this liquid crystal display device 1, as shown in FIG. 3, a predetermined number of liquid crystal pixels 2, 2, ... Are linearly arranged along the horizontal direction is defined as one line, and this line is along the vertical direction. It has a total of 480. The 480 scanning lines include a first field 3 formed by a combination of the first line and the second line, the third line and the fourth line, the fifth line and the sixth line, ... It is divided into a second field 4 consisting of a combination of two lines and a third line, a fourth line and a fifth line ....

As shown in FIG. 4, each liquid crystal pixel 2 of the liquid crystal display device 1 is provided with a transparent electrode 6 on the back surface laminated on a substrate 5, and this transparent electrode 6 is provided for each pixel 2, 2 ...
A predetermined number of rows are arranged in the vertical direction and the horizontal direction. Further, on the substrate 3, a thin film transistor 7 for driving the transparent electrode 6 on the back surface side is provided for each pixel 2,
2 is laminated corresponding to. Further, on the substrate 3, a substrate 9 on which a transparent electrode 8 on the front surface is entirely formed is opposed to be disposed with a predetermined gap, and the transparent electrode 8 on the front surface is common to each pixel. And is entirely formed. A liquid crystal material 7 is filled between the transparent electrode 6 on the back surface side and the transparent electrode 8 on the front surface side. By applying a predetermined voltage between the transparent electrodes 6 and 8, the liquid crystal material 7 is filled. An image is displayed by orienting 10.

FIG. 2 shows a drive circuit of the liquid crystal display device.

Each of the liquid crystal pixels 2, 2, ... Of the liquid crystal display device 1
Are driven by circuits forming a matrix as shown in FIG. That is, in the thin film transistor 7 corresponding to each liquid crystal pixel 2, 2, ..., The scanning signal line 1 whose gate electrode is common to the pixels of each line
, And their source electrodes are connected to the image data lines 12, 12 ... Common to the m-th (m = 1, 2 ...) Pixels. Further, the drain electrode of the thin film transistor 7 is connected to the transparent electrodes 6, 6 ... Divided for each pixel 2, 2 ... And the transparent electrode 8 facing the transparent electrodes 6, 6 ... like,
It is a common electrode common to each of the pixels 2, 2.

Further, the scanning signal lines 11 and 1 for the respective lines described above.
1 are level shift circuits 1 via the buffer circuit 13.
4 and the level shift circuit 14 is connected to the interlace scanning circuit 15 according to the present embodiment. Then, from the interlace scanning circuit 15,
A selection signal for sequentially selecting the scanning signal lines 11, 11 ... Of each line in a predetermined order is output.
After the output level is adjusted by the level shift circuit, it is applied to the transparent electrodes 6, 6 of each pixel 2, 2 ... While being held for a certain period by the buffer circuit.

On the other hand, each of the image data lines 12, 12 ...
Is connected to the data driver 16, and from this data driver 16, the m-th line (m = 1, 2) of each line.
.) Pixels are sequentially output. The image data is sequentially applied to the pixels 2, 2, ... Of each line which are interlaced scanned by the interlace scanning circuit 15, and the image corresponding to the image data is displayed by the pixels 2, 2 ,. ing.

FIG. 1 is a circuit diagram showing an embodiment of an interlace scanning circuit according to the present invention.

This interlaced scanning circuit has two stages for each stage.
A shift register that sequentially outputs two pulse signals from one output terminal at a predetermined interval, and on / off control by a pulse signal output from one output terminal of this shift register. ON / OFF control is performed by the first and second switching elements that respectively output the clock signal applied to the second control line when turned on, and the pulse signal output from the other output terminal of the shift register, Third and fourth switching elements that respectively output the clock signals applied to the control line and the fourth control line when turned on, and the clock signals applied to the first to fourth control lines are sequentially switched and output. And a clock circuit that operates.

That is, this interlaced scanning circuit 1
As shown in FIG. 1, the reference numeral 5 includes a shift register 21. The shift register 21 sequentially shifts two pulse signals 22 and 23 from two output terminals Qn and Qn of each stage by a predetermined interval. It is designed to output. Further, in each stage of the shift register 21, the gates of the first and second thin film transistors 25 and 26 are respectively connected to one output terminal Qn thereof via an inverter 24, and the first and second Thin film transistor 2
The source electrodes 5 and 26 have a first control line 27 and a second control line 27.
Control lines 28 are connected respectively. From the drain electrodes of the first and second thin film transistors 25 and 26, the line selection signal G _4n-3 of the liquid crystal display device 1,
G _4n-2 is output respectively.

Further, in each stage of the shift register 21, the gates of the third and fourth thin film transistors 29 and 30 are directly connected to the other output terminal Qn, respectively, and the third and fourth thin film transistors are provided. 29,
A third control line 31 and a fourth control line 32 are connected to the source electrode of 30, respectively. And the third
And from the drain electrodes of the fourth thin film transistors 29 and 30, line selection signals G _4n-1 and G _4n of the liquid crystal display device 1 are obtained.
Are output respectively.

Further, the shift register 21 has a clock signal CLK and first to fourth control signals S1 to S.
4 is connected to the clock circuit 35. From the clock circuit 35, the first to fourth control lines 27,
28, 31, 32 to the first to fourth control signals S1 to S4
Are output at predetermined timings.

In the above structure, the interlace scanning circuit according to this embodiment is configured to interlace scan the liquid crystal display device as follows.

That is, in the first field 3,
In the shift register 21 of the interlaced scanning circuit 15,
As shown in FIG. 2, the clock signal CLK as shown in FIG. 5A is inputted from the clock circuit 35, and the two output terminals Qn (bar) and Qn of a stage of the shift register 21 are Two pulse signals 22 and 23 as shown in FIGS. 5 (b) and 5 (c) are sequentially output while being shifted by a predetermined interval.

The pulse signal 22 output from one output terminal Qn (bar) of the shift register 21 is transmitted through the inverter 24 to the first and second thin film transistors 2.
5 and 26 are applied to the gate electrodes. The first and second thin film transistors 25 and 26 are turned on when the inverted pulse signal 22 is in the H state, and the first and second control lines connected to the source electrodes of the respective transistors 25 and 26. The control signals S1 and S2 as shown in FIGS.
Line selection signals G _4n-3 and G _4n-2 from the drain electrodes of 26
Are output respectively. as a result,
Line selection signals G _4n-3 and G _4n-2 as shown in FIGS. 6A and 6B are output from the drain electrodes of the first and second thin film transistors 25 and 26, respectively, and the liquid crystal display device 1 is displayed. Two lines are scanned, such as the first line and the second line.

Next, the pulse signal 23 output from the other output terminal Qn of the same stage of the shift register 21 is
It is directly applied to the gate electrodes of the third and fourth thin film transistors 29 and 30. These third and fourth thin film transistors 29 and 30 are turned on when the pulse signal 23 as shown in FIG. 5C is in the H state, and the third thin film transistors 29 and 30 connected to the source electrodes of the respective transistors 29 and 30 are connected. And the fourth
Control signals S3 and S4 as shown in FIG. 5 (h) (i) applied to the control lines 31 and 32 of
The 30 drain electrodes output line selection signals G _4n-1 and G _4n , respectively. As a result, the line selection signals G _4n-1 and G _4n as shown in FIGS. 6C and 6D are output from the drain electrodes of the third and fourth thin film transistors 29 and 30, respectively.

Thereafter, from the first to fourth thin film transistors connected to the output terminals Qn + 1 (bar) and Qn + 1 of the next stage of the shift register 21, the line selection signal G _{4n + 1} as shown in FIG. G _{4n + 2} , G _{4n + 3} and G _{4n + 4} are sequentially output.

As described above, in the first field 3, the first line, the second line, and the third line of the liquid crystal display device 1 are used.
Two lines consisting of a combination of the line and the fourth line, the fifth line and the sixth line, etc. are simultaneously and sequentially scanned.

On the other hand, in the following second field 4,
The control signals S1 to S4 output from the clock circuit 35 to the shift register 21 change as shown in FIGS. That is, the second and fourth control lines 2
The control signals S2 and S4 applied to 8, 32 are inverted as compared with the first field 3 and the first and fourth control lines 27,
The control signals S1 and S4 applied to 32 are equal to the control signals S2 and S3 applied to the second and third control lines 28 and 31, respectively.

Therefore, in the second field 4,
The pulse signal 22 output from one output terminal Qn (bar) of the shift register 21 is applied to the gate electrodes of the first and second thin film transistors 25 and 26 via the inverter 24. The first and second thin film transistors 25 and 26 are turned on when the inverted pulse signal 22 is in the H state, and the transistors 25 and 26 are turned on.
First and second control lines 27 connected to the source electrodes of
Control signals S1 and S2 shown in FIGS. 7 (f) and (g) applied to 28 are output from the drain electrodes of the transistors 25 and 26 as line selection signals G _4n-3 and G _4n-2 , respectively. It has become. As a result, from the drain electrodes of the first and second thin film transistors 25 and 26, the line selection signal G as shown in FIGS.
_4n-3 and G _4n-2 are output, and only the first line of the liquid crystal display device 1 is selected and scanned first, and then the second line is scanned.

Next, the pulse signal 23 output from the other output terminal Qn of the same stage of the shift register 21 is
It is directly applied to the gate electrodes of the third and fourth thin film transistors 29 and 30. The third and fourth thin film transistors 29 and 30 are turned on when the pulse signal 23 shown in FIG. 7C is in the H state, and the third thin film transistors 29 and 30 connected to the source electrodes of the transistors 29 and 30 are connected. And the fourth
Control signals S3 and S4 applied to the control lines 31 and 32 of FIG.
The 30 drain electrodes output line selection signals G _4n-1 and G _4n , respectively. As a result, the drain electrodes of the third and fourth thin film transistors 29 and 30 output line selection signals G _4n-1 and G _4n as shown in FIGS. After the third line of device 1 has been selected and scanned first, the fourth line is subsequently scanned. By the way, the timing when the third line is selected is as shown in FIG.
Since the second line is synchronized with the timing of selection, the second line and the third line are simultaneously scanned.

Thereafter, from the first to fourth thin film transistors connected to the output terminals Qn + 1 (bar) and Qn + 1 of the next stage of the shift register 21, the line selection signal G _{4n + 1} as shown in FIG. G _{4n + 2} , G _{4n + 3} and G _{4n + 4} are sequentially output.

Thus, in the second field 4, as shown in FIG. 3, after the first line of the liquid crystal display device 1 is independently scanned first, the second line and the third line,
Two lines, which are combinations of the fourth line and the fifth line, the sixth line and the seventh line, are simultaneously and sequentially scanned.

As described above, the first to fourth control lines 27,
Of the first to fourth thin film transistors 25, 26, 29, 30 respectively connected to 28, 31, 32, two transistors are output from the output terminals Qn (bar), Qn of each stage of the shift register 21. Pulse signal 22, 2
By turning on simultaneously by 3, the two adjacent lines of the liquid crystal display device 1 can be simultaneously driven only during the horizontal scanning period of one frame. Moreover,
The first to fourth control lines 27, 28, 31,
By changing the combination of the control signals S1 to S4 respectively applied to 32 by the clock circuit 35,
Since it is possible to change the combination of two adjacent lines of the liquid crystal display device 1 that scans for each frame, double-speed line sequential drive is possible without doubling the operating frequency of the circuit, and high-definition image display is possible. Is possible.

[0039]

According to the present invention, which has the above-described structure and operation, it is possible to display a high-definition image without causing flicker even if the number of pixels in the vertical direction is 480, and the operation of the circuit is also possible. The frequency may be the same as the simple line sequential drive,
It is possible to provide an interlaced scanning circuit capable of preventing a large increase in the cost of the circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an interlace scanning circuit according to the present invention.

FIG. 2 is a block diagram showing a drive circuit of a liquid crystal display device.

FIG. 3 is an explanatory diagram showing a scanning state of interlaced scanning.

FIG. 4 is a cross-sectional view showing a pixel of a liquid crystal display device.

5A to 5I are timing charts showing signals of the interlaced scanning circuit, respectively.

FIGS. 6A to 6H are timing charts showing signals of the interlaced scanning circuit.

FIGS. 7A to 7I are timing charts showing signals of the interlaced scanning circuit.

8A to 8H are timing charts showing signals of the interlaced scanning circuit.

FIG. 9 is an explanatory diagram showing conventional interlaced scanning.

FIG. 10 is an explanatory diagram showing another conventional interlaced scanning.

FIG. 11 is an explanatory diagram showing still another conventional interlaced scan.

[Explanation of symbols]

2 liquid crystal pixels, 15 interlaced scanning circuit, 21
Shift register, 25, 26, 29, 30 first to fourth thin film transistors, 27, 28, 31, 32 first
Through fourth control line, 35 clock circuit.

Claims (1)

[Claims] 1. An interlace scanning circuit for interlacing scanning pixels of each line of a liquid crystal display device, a shift register for sequentially outputting two pulse signals from two output terminals of each stage at a predetermined interval, and the shift register. First and second switching elements that are on / off controlled by a pulse signal output from one output terminal of the register, and output a clock signal applied to the first control line and the second control line, respectively, when the register is on. And a third and a third clock signal, which are on / off controlled by a pulse signal output from the other output terminal of the shift register and output a clock signal applied to the third control line and the fourth control line, respectively, when the clock signal is on. 4 switching elements and the clock signals applied to the first to fourth control lines are sequentially switched and output. An interlace scanning circuit, comprising a clock circuit, and sequentially interlacing pixels of each line of the liquid crystal display device by outputs of first to fourth switching elements connected to each stage of the shift register. ..