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JPH0510679B2 - - Google Patents

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Publication number
JPH0510679B2
JPH0510679B2 JP58027006A JP2700683A JPH0510679B2 JP H0510679 B2 JPH0510679 B2 JP H0510679B2 JP 58027006 A JP58027006 A JP 58027006A JP 2700683 A JP2700683 A JP 2700683A JP H0510679 B2 JPH0510679 B2 JP H0510679B2
Authority
JP
Japan
Prior art keywords
matrix
voltage
driving
nonlinear resistance
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58027006A
Other languages
Japanese (ja)
Other versions
JPS59154491A (en
Inventor
Seigo Togashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP58027006A priority Critical patent/JPS59154491A/en
Publication of JPS59154491A publication Critical patent/JPS59154491A/en
Publication of JPH0510679B2 publication Critical patent/JPH0510679B2/ja
Granted legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

【発明の詳細な説明】 本発明は時分割マトリクス表示装置のコントラ
ストの改善にかかわり、詳しくは液晶等のような
時分割性の劣る表示素子を用いても、高分割迄十
分なコントラストの表示を可能とし得る方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the contrast of a time-division matrix display device, and more specifically, to improve the contrast of a time-division matrix display device, and more specifically, to improve the contrast of a time-division matrix display device, and more specifically, to improve the contrast of a time-division matrix display device. Regarding possible methods.

近年、液晶、EC、EL等を用いた高密度表示パ
ネルの開発が盛んである。この様な時分割性の劣
る表示素子に用いて高密度表示を行う場合、次の
2つの方法が用いられる。第1の方法は時分割度
は適当な値に抑えて多重配線等で逃げる方法でパ
ツシブ・マトリクスと呼ばれる。第2の方法はト
ランジスタ、非線形抵抗等の能動素子をスイツチ
としてパネル上に形成し、各画素に電圧を蓄積さ
せる方法でアクテイブ・マトリクスと呼ばれる。
In recent years, development of high-density display panels using liquid crystals, EC, EL, etc. has been active. When performing high-density display using such a display element with poor time-division performance, the following two methods are used. The first method is called a passive matrix, in which the degree of time division is suppressed to an appropriate value and avoided by multiple wiring, etc. The second method is called an active matrix, in which active elements such as transistors and nonlinear resistors are formed as switches on the panel, and voltage is accumulated in each pixel.

前者はパネル製造は比較的易しいが、配線多重
度を上げるのにも限界があり表示密度はそう上げ
られない。後者は表示密度は十分上げられるもの
の、電荷を十分蓄積させるに十分な高性能スイツ
チング素子を高密度無欠陥均一に作り込む技術は
非常に難しくまだ大面積パネルとしては実用化に
至つていない。
The former panel is relatively easy to manufacture, but there is a limit to increasing the wiring multiplicity, and the display density cannot be increased that much. Although the latter can sufficiently increase display density, the technology to fabricate high-density, defect-free and uniform switching elements sufficient to store enough charge is extremely difficult, and has not yet been put into practical use as a large-area panel.

本発明は従来アクテイブ・マトリクスに使われ
ていた非線形抵抗を電荷蓄積素子としてではなく
パツシブ・マトリクスに用いて電圧一部減算型素
子として最適化して使用する方法に関し、電荷蓄
積素子としては十分な性能を持たない素子でも使
用可能で、パツシブ・マトリクスの時分割度を数
倍から10倍上げる事ができる。
The present invention relates to a method of optimizing and using a nonlinear resistor conventionally used in an active matrix, not as a charge storage element, but as a voltage partial subtraction type element in a passive matrix. It can be used even with elements that do not have a passive matrix, and the time division degree of the passive matrix can be increased from several times to 10 times.

以下、図面に基づいて説明する。 The description will be given below based on the drawings.

第1図はパツシブ・マトリクスの等価回路であ
る。Sは行電極、Dは列電極、C(i,j)(i,
jは整数)は表示要素である。
FIG. 1 is an equivalent circuit of a passive matrix. S is a row electrode, D is a column electrode, C(i,j)(i,
j is an integer) is a display element.

第2図は非線形抵抗NL(i,j)を付加した
マトリクス要素M(i,j)を有するマトリクス
の等価回路である。従来はアクテイブ・マトリク
スとして用いられており詳しくはB.Lechner等の
論文(Proc.IEEE、vol.59、p1566〜1579、
(1971))及びD.Castle berryの論文(IEEE
Trans、ED−26、p1123〜1128(1979))で述べら
れているが、本発明によるパツシブ・マトリクス
も第2図の等価回路で表わせる。
FIG. 2 is an equivalent circuit of a matrix having matrix elements M(i,j) to which nonlinear resistances NL(i,j) are added. Traditionally, it has been used as an active matrix, and details can be found in the paper by B. Lechner et al.
(1971)) and D. Castle berry's paper (IEEE
Trans., ED-26, p. 1123-1128 (1979)), the passive matrix according to the present invention can also be represented by the equivalent circuit shown in FIG.

第3図は本発明に用いる非線形抵抗素子の電流
I対電圧V特性の一例であり閾値電圧Vthの前後
でオフ抵抗ROFFからオン抵抗RONに変化し折れ曲
つた特性を示す。
FIG. 3 shows an example of the current I vs. voltage V characteristic of the nonlinear resistance element used in the present invention, and shows a curved characteristic that changes from off-resistance R OFF to on-resistance R ON before and after the threshold voltage V th .

第4図は本発明のマトリクス表示装置の一実施
例のブロツク図である。151は表示パネル、1
52は第5図φo,φo+1の様な走査信号を表示パネ
ルの行電極SI〜SNに印加する行電極ドライバ、1
54は第5図Dnの様なデータ信号を列電極DI
DMに印加する列電極ドライバ、153は表示情
報155、タイミング信号158,159、電源
156,157等を各ドライバに供給するコント
ローラである。
FIG. 4 is a block diagram of an embodiment of the matrix display device of the present invention. 151 is a display panel, 1
Reference numeral 52 denotes a row electrode driver 1 that applies scanning signals such as φ o and φ o+1 in FIG. 5 to the row electrodes S I to S N of the display panel.
54 connects the data signal as shown in FIG. 5 D n to the column electrode D I ~
A column electrode driver 153 that applies voltage to D M is a controller that supplies display information 155, timing signals 158, 159, power supplies 156, 157, etc. to each driver.

第5図は本発明の一実施例の駆動波形図であ
る。aのφo,φn+1は走査信号であり選択位相
TAでは±aの電圧、非選択位相TBでは基準電圧
0をとる。bのDmはデータ信号でありデータに
応じて±1の電圧をとる。(ここでは、データ信
号の電圧振巾Vpとした時各電圧はVpで規格化し
てある。この走査、データ両信号の形自体は従来
のパツシブ・マトリクスの1/aバイアス法と全
く同じである。しかしこの波形を非線形抵抗素子
を用いたマトリクスに応用するには駆動電圧Vp
と非線形抵抗素子の閾値電圧Vthとの関係及びa
の値を最適化する必要があり、本発明は従来と異
なる条件を採用する事により従来より程度の低い
非線形抵抗素子でも使用可能とするものである。
FIG. 5 is a drive waveform diagram of an embodiment of the present invention. φ o and φn+1 of a are scanning signals and selection phases
A voltage of ±a is taken at T A , and a reference voltage of 0 is taken at the non-selected phase T B. Dm in b is a data signal and takes a voltage of ±1 depending on the data. (Here, when the voltage amplitude of the data signal is V p , each voltage is normalized by V p . The shapes of both the scanning and data signals are exactly the same as the conventional passive matrix 1/a bias method. However, in order to apply this waveform to a matrix using nonlinear resistance elements, the driving voltage V p
The relationship between and the threshold voltage V th of the nonlinear resistance element and a
It is necessary to optimize the value of , and the present invention makes it possible to use even a nonlinear resistance element with a lower degree than the conventional one by adopting conditions different from the conventional one.

第6図は前記Castle berryの論文中に示された
(Fig.7)駆動条件の一例である。彼によれば次の
2つの条件を満す事が必要という。
FIG. 6 is an example of the driving conditions shown in Castle Berry's paper (Fig. 7). According to him, the following two conditions must be met.

a−1<th (但しth=Vth/Vp (1) 1+ONth (但しON=VON/Vo (2) (1)、(2)は電荷蓄積型アクテイブ.マトリクスの
必要条件である。
a-1< th (where th = V th /V p (1) 1+ ON < th (where ON = V ON /Vo (2) (1) and (2) are the necessary conditions for a charge storage type active matrix. be.

しかし本発明では(1)、(2)の条件は用いず、逆に
次の条件(3)を用いる。
However, in the present invention, conditions (1) and (2) are not used, but the following condition (3) is used instead.

th 第5図c,dは条件(3)を用いた場合の各マトリ
クス要素に印加される電圧波形である。斜線部が
表示要素に印加される電圧波形である。この波形
の特徴は、マトリクス要素に印加される電圧の絶
対値はほとんど位相に於てVthよりほぼ等しいか
大きく、表示要素に印加される電圧の絶対値は、
マトリクス要素に印加される電圧からVthをおお
よそ差し引いた値に一致する点にある。即ち、従
来の条件(1)、(2)を用いると非線形抵抗素子は電荷
蓄積用のスイツチとして働くのに対し、本発明の
条件(3)を用いると非線形抵抗素子は単なる電圧差
し引き型の抵抗素子として働かせる事ができる。
1 th FIG. 5c and d are voltage waveforms applied to each matrix element when condition (3) is used. The shaded area is the voltage waveform applied to the display element. The characteristics of this waveform are that the absolute value of the voltage applied to the matrix element is approximately equal to or larger than V th in most phases, and the absolute value of the voltage applied to the display element is
It is at a point that approximately corresponds to the voltage applied to the matrix element minus V th . In other words, when conventional conditions (1) and (2) are used, the nonlinear resistance element acts as a charge storage switch, whereas when the present invention's condition (3) is used, the nonlinear resistance element acts as a simple voltage subtraction type resistance. It can be used as an element.

第5図c,dに於ける表示要素に印加される電
圧の実効値はそれぞれオン電圧VON、オフ電圧
VOFFに対し、時分割数nに対し次式で表わされ
る。
The effective values of the voltages applied to the display elements in Figures 5c and d are the on-voltage V ON and the off-voltage, respectively.
For V OFF , the number of time divisions n is expressed by the following equation.

VON=Vp√〔(+1−th2+(−1)(1−
th2〕/n(4) VOFF=Vp√〔(−1−th2+(−1)(1−
th2〕/n(5) ここで、a、thを最適化するためには次の点
を考慮する必要がある。第1に(6)で定義される駆
動マージンMと呼ばれる量をできるだけ大きくす
る事である。
V ON =V p √ [(+1- th ) 2 + (-1) (1-
th ) 2 ]/n(4) V OFF = V p √ [(-1- th ) 2 + (-1) (1-
th ) 2 ]/n(5) Here, in order to optimize a and th, it is necessary to consider the following points. The first thing is to make the amount called drive margin M defined in (6) as large as possible.

M=VON/VOFF (6) 液晶、EL等ではMを大きくする程コントラス
ト視野角等の表示品質は向上する。
M=V ON /V OFF (6) In liquid crystal, EL, etc., display quality such as contrast viewing angle improves as M increases.

第7図はn=400の時のa−th平面での等M
線図である。液晶の場合現状ではMは最低でも
1.1程度は欲しいので、thは次の式を満たす事が
望ましい。
Figure 7 shows equal M on the a- th plane when n=400.
It is a line diagram. In the case of liquid crystals, at present M is at least
Since we want about 1.1, it is desirable that th satisfy the following formula.

0.5∠〜Vth/Vo∠〜1 (7) 第2に考慮する点はVthのばらつきに対する
VONの変化である。一般に非線素子のVthはそろ
えるのが難しく駆動法はその影響をできるだけ少
なく出来る事が望ましい。次の式でばらつきによ
る変動率mを定義すると m=(VONの変化率)/(Vthの変化率) (8) Castle berryの駆動法ではm=1.5となる。本
発明では第8図に示す如く条件を選べばm∠〜0.2
も可能であり少なくともm1の曲線の外側を使
えば十分使用に耐える。
0.5∠〜V th /Vo∠〜1 (7) The second point to consider is the variation in V th .
This is a change in V ON . In general, it is difficult to align the V th of non-linear elements, and it is desirable for the driving method to minimize the effect of this. Defining the rate of variation m due to variation using the following formula: m = (rate of change in V ON ) / (rate of change in V th ) (8) In Castle Berry's driving method, m = 1.5. In the present invention, if the conditions are selected as shown in Fig. 8, m∠~0.2
It is also possible to use the curve at least outside the m1 curve.

第3に考慮する点は閾値電圧Vthの絶対値であ
る。第3図の如き理想的閾値を持つた非線形抵抗
素子は現実には存在しないが、例えば本出願人に
よる出願である出願番号57−167945で示したアモ
ルフアスシリコン(a−Si)ダイオード・リング
等はそれに近い特性を有している。しかしこの素
子の欠点はVthが低い事で、一段では0.7〜1.0Vし
かなくそれ以上必要な場合は多段連結必要で、段
数が多くなる程製造が複雑になる。
The third point to consider is the absolute value of the threshold voltage V th . Although a nonlinear resistance element with an ideal threshold value as shown in FIG. 3 does not actually exist, for example, an amorphous silicon (a-Si) diode ring shown in application number 57-167945 filed by the present applicant, etc. has similar characteristics. However, the drawback of this element is that V th is low, with only 0.7 to 1.0 V in one stage, and if more is required, multiple stages must be connected, and the greater the number of stages, the more complicated the manufacturing becomes.

よつて表示電圧VONで規格化したVth/VONはで
きれば小さい方が望ましい。第9図はa−th
面での等Vth/VON図である。液晶の場合VON
2V程度なのでVth/VON=3の曲線の外側を使え
ばa−Siダイオードなら6段以内ですむ。
Therefore, it is desirable that V th /V ON normalized by the display voltage V ON be as small as possible. FIG. 9 is an equal V th /V ON diagram in the a- th plane. For LCD, V ON
Since it is about 2V, if you use the outside of the curve of V th /V ON = 3, you can use an a-Si diode within 6 stages.

以上の説明から明らかな如く、本発明は従来例
に比較して電荷蓄積を行わず電圧差し引きを行う
のみという特徴を有し、条件の最適化により閾値
変動に対する駆動電圧変動率が従来のm=1.5か
らm=1.0〜0.2以下と大巾に小さくなり、又、従
来のパツシブ・マトリクスに比較して十分な
VON/VOFFがとれ、n400〜1000の高分割も可
能となつた。しかも電荷蓄積を全く行わない事か
ら第3図の特性におけるオフ抵抗ROFFはそれ程大
きくなくても十分使用可能となつた。即ち従来で
は負荷容量CLCに対し次式を満す必要があつたが、 ROFF≫nTA/CLC (9) 本発明では次式でよく ROFF>TA/CLC (10) n=100〜1000としても条件は大巾に緩和され
ている。この事は例えばa−Siダイオード・リン
グを用いた場合に外光によるROFFの低下を抑制し
なくても十分可能であり、又、製造条件の制御も
楽になる等歩留向上、プロセス短縮が可能で、従
来に比べパネル製造コストもかなり低減できる。
As is clear from the above description, compared to the conventional example, the present invention has the feature of only performing voltage subtraction without charge accumulation, and by optimizing the conditions, the driving voltage fluctuation rate with respect to threshold fluctuation is lower than the conventional m = 1.5 to less than m = 1.0~0.2, and it is also much smaller than the conventional passive matrix.
V ON /V OFF can be obtained, and high division of n400 to 1000 is also possible. Furthermore, since no charge is accumulated at all, the off-resistance R OFF in the characteristics shown in FIG. 3 is not so large to be usable. That is, in the past , it was necessary for the load capacity C LC to satisfy the following formula, but in the present invention, the following formula is sufficient: R OFF > T A / C LC (10) n = 100 to 1000, the conditions are greatly relaxed. For example, when using an a-Si diode ring, this is possible even without suppressing the decrease in R OFF due to external light, and it also makes it easier to control manufacturing conditions, improving yields and shortening the process. This is possible, and panel manufacturing costs can be significantly reduced compared to conventional methods.

尚、第5図の実施例の走査信号φo、データ信
号DnはTA/2毎に基準レベルを第10図の如く
前半で0、後半でa−1とシフトさせピーク・ピ
ーク電圧を低減しても勿論かわらない。
Incidentally, the scanning signal φ o and the data signal D n of the embodiment shown in FIG. 5 have their reference levels shifted every T A /2 from 0 in the first half to a-1 in the second half as shown in FIG. Of course, it will not change even if it is reduced.

尚、実施例では表示要素として液晶を用いてお
り、液晶は本発明では最も有効であるが、エレク
トロクロミズム、エレクトロルミネツセンス等他
の表示要素を用いてもかまわない。
In the embodiments, liquid crystal is used as the display element, and liquid crystal is most effective in the present invention, but other display elements such as electrochromism and electroluminescence may also be used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のパツシブ・マトリクスの等価回
路図、第2図は非線形抵抗素子を用いた本発明の
パツシブ・マトリクスの等価回路図、第3図は本
発明に用いる非線形抵抗素子の特性図、第4図は
本発明の表示装置のブロツク図、第5図は本発明
の一実施例の駆動波形図、第6図は従来の駆動波
形図、第7,8,9図は本発明による駆動法を用
いた場合の駆動条件と評価パラメータの関係を示
す特性図、第10図は本発明の他の実施例の駆動
波形図である。 S,SI〜SN……行電極、D,DI〜DM……列電極、
C(i,j)……表示要素、NL(i,j)……非
線形抵抗素子、M(i,j)……マトリクス要素、
Vth……非線形抵抗素子の閾値電圧、Vo……デー
タ信号の片側電圧振巾。
Fig. 1 is an equivalent circuit diagram of a conventional passive matrix, Fig. 2 is an equivalent circuit diagram of a passive matrix of the present invention using a nonlinear resistance element, and Fig. 3 is a characteristic diagram of the nonlinear resistance element used in the present invention. FIG. 4 is a block diagram of the display device of the present invention, FIG. 5 is a drive waveform diagram of an embodiment of the present invention, FIG. 6 is a conventional drive waveform diagram, and FIGS. 7, 8, and 9 are drive waveform diagrams of the present invention. FIG. 10 is a characteristic diagram showing the relationship between driving conditions and evaluation parameters when the method is used, and FIG. 10 is a driving waveform diagram of another embodiment of the present invention. S, S I ~ S N ... Row electrode, D, D I ~ D M ... Column electrode,
C(i,j)...display element, NL(i,j)...nonlinear resistance element, M(i,j)...matrix element,
V th ...Threshold voltage of the nonlinear resistance element, Vo...One side voltage amplitude of the data signal.

Claims (1)

【特許請求の範囲】 1 表示要素と非線形抵抗素子が直列に接続され
たマトリクス要素をマトリクス状に配列し、該マ
トリクス要素の一端を行電極に他端を列電極に接
続し、各行電極を順次選択し、列電極に印加され
た信号に基づいて表示要素にデータを表示するマ
トリクス表示装置の駆動方法に於いて、前記各行
電極の選択位相および非選択位相のいずれの位相
においても、前記非線形抵抗素子の両端の電圧の
絶対値が非線形抵抗素子のしきい値電圧以上とな
る行電極駆動信号、列電極駆動信号を各行電極、
列電極に印加することを特徴とするマトリクス表
示装置の駆動方法。 2 行電極に印加される駆動信号は選択位相と非
選択位相を有する走査信号であり、列電極に印加
される駆動信号は表示データに依存したデータ信
号であり、非選択位相の走査信号を基準としたデ
ータ信号の絶対値の最大値はしきい値電圧Vth
ほぼ等しいか大きい事を特徴とする特許請求の範
囲第1項記載のマトリクス表示装置の駆動方法。 3 非線形抵抗素子のしきい値をVth、非選択位
相に於いてマトリクス要素に印加される電圧の最
大値をVpとすると、Vth/Vpはおおよそ0.5〜1.0
の間にある事を特徴とする特許請求の範囲第1項
記載のマトリクス表示装置の駆動方法。 4 非線形抵抗素子は、アモルフアスシリコンダ
イオードの順逆並列接続素子である事を特徴とす
る特許請求の範囲第1項記載のマトリクス表示装
置の駆動方法。
[Claims] 1. Matrix elements in which a display element and a nonlinear resistance element are connected in series are arranged in a matrix, one end of the matrix element is connected to a row electrode, the other end is connected to a column electrode, and each row electrode is connected in sequence. In the method for driving a matrix display device that displays data on display elements based on signals applied to column electrodes, the nonlinear resistance A row electrode drive signal and a column electrode drive signal for which the absolute value of the voltage across the element is equal to or higher than the threshold voltage of the nonlinear resistance element are applied to each row electrode,
A method for driving a matrix display device, characterized in that a voltage is applied to column electrodes. 2 The drive signal applied to the row electrodes is a scanning signal having a selection phase and a non-selection phase, and the drive signal applied to the column electrodes is a data signal dependent on display data, with the scanning signal of the non-selection phase as a reference. 2. The method of driving a matrix display device according to claim 1, wherein the maximum absolute value of the data signal is approximately equal to or larger than the threshold voltage Vth . 3 If the threshold value of the nonlinear resistance element is V th and the maximum value of the voltage applied to the matrix element in the non-selected phase is V p , then V th /V p is approximately 0.5 to 1.0.
2. The method of driving a matrix display device according to claim 1, wherein the driving method is between. 4. The method for driving a matrix display device according to claim 1, wherein the nonlinear resistance element is a forward-reverse parallel connected element of amorphous silicon diodes.
JP58027006A 1983-02-22 1983-02-22 Driving of matrix display Granted JPS59154491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58027006A JPS59154491A (en) 1983-02-22 1983-02-22 Driving of matrix display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58027006A JPS59154491A (en) 1983-02-22 1983-02-22 Driving of matrix display

Publications (2)

Publication Number Publication Date
JPS59154491A JPS59154491A (en) 1984-09-03
JPH0510679B2 true JPH0510679B2 (en) 1993-02-10

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JP58027006A Granted JPS59154491A (en) 1983-02-22 1983-02-22 Driving of matrix display

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758190A (en) * 1980-09-25 1982-04-07 Suwa Seikosha Kk Active matric type liquid crystal indicator driving system
JPS5758191A (en) * 1980-09-25 1982-04-07 Suwa Seikosha Kk Active matric type liquid crystal indicator driving system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758190A (en) * 1980-09-25 1982-04-07 Suwa Seikosha Kk Active matric type liquid crystal indicator driving system
JPS5758191A (en) * 1980-09-25 1982-04-07 Suwa Seikosha Kk Active matric type liquid crystal indicator driving system

Also Published As

Publication number Publication date
JPS59154491A (en) 1984-09-03

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