JPH05103074A - Radio communication equipment - Google Patents

Abstract

PURPOSE:To provide the small sized and light weight radio communication equipment provided with an automatic answering recording function and an automatic answering reply recording function with excellent operability. CONSTITUTION:In the radio communication equipment in which a speech signal is digitized by a prescribed coding decoding system as the radio communication system for transmission and reception set in the digital mode, while the automatic answering recording mode is set, an error correction coding decoding circuit 8 stores a reception digital signal subject to error correction coding to an IC memory card 10 and when the automatic answering recording reproduction mode is set, the reception digital signal stored in the IC memory card 10 is read and the signal is decoded and reproduced by a voice coding decoding circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio communication device used in a mobile radio communication system such as an automobile radio telephone system, and more particularly to a device having an answering machine function.

[0002]

2. Description of the Related Art Generally, in a mobile radio communication system such as a mobile radio telephone system or a car telephone system, an analog voice signal is FM-modulated and transmitted by a transmitting station,
The receiving station receives the signal sent from the transmitting station and then FM demodulates it to reproduce the original analog audio signal. As described above, the mainstream of the conventional mobile wireless communication system is an analog wireless communication system in which all audio signals are treated as analog signals.

By the way, each mobile station of the mobile radio communication system cannot naturally respond to an incoming call that arrives when the subscriber is absent. Therefore, in the above-described car telephone system, when the subscriber cannot answer, such as when the subscriber is absent in the vehicle, a voice recording device in which a voice (message) from the caller is separately provided by automatically answering the incoming call. There is one that has a so-called answering machine function that can record automatically.

[0004]

However, the car telephone system to which the answering machine function has been added has the following problems to be solved. That is, as described above, in mobile radio communication systems such as car telephone systems, all voice information is processed by analog signals. In order to store such an analog signal, an analog recording device such as a tape recorder using a magnetic tape as a recording medium is usually used. However, since these recording devices require a mechanism part for driving the magnetic tape, there is a limit to miniaturization thereof. Therefore, for example, if the tape recorder is installed in the vehicle as the audio recording device, the aesthetics of the vehicle may be impaired, and the recording device such as the tape recorder is separately provided in the car telephone terminal as described above. The operation was very complicated. Therefore, an object of the present invention is to provide a wireless communication device that is small in size, lightweight, and has a good operability and has an absence recording function. Another object of the present invention is to provide a wireless communication device which is compact and lightweight and has an operability and an answering machine recording function.

[0005]

In order to achieve the above object, the present invention provides a received digital signal in a wireless communication apparatus having a digital mode in which a call signal is digitized by a predetermined coding / decoding method and transmitted / received as a wireless communication method. Error-correction decoding means for error-correction decoding and outputting, and speech decoding means for decoding the received digital signal output from the error-correction decoding means to reproduce an analog reception signal and providing the analog reception signal for loud output. And a digital signal storage element for storing the received digital signal output from the error correction decoding means, and an absence recording control means. Then, while the absence recording mode is set by the absence recording control means, the received digital signal output from the error correction decoding means is stored in the digital signal storage element, and the absence recording reproduction mode is set. In this state, the received digital signal stored in the digital signal storage element is read out and decoded and reproduced by the voice decoding means.

According to another aspect of the present invention, in a wireless communication apparatus having a digital mode in which a call signal is digitized by a predetermined code decoding method as a wireless communication method and transmitted / received, an error of error correction decoding of a received digital signal and output of the error A correction decoding unit, a decoding unit for decoding the received digital signal output from the error correction decoding unit to reproduce an analog reception signal, and a voice decoding unit for providing the analog reception signal for a loud output, and encoding the analog transmission signal. The audio coding means for outputting the transmission digital signal and the error correction coding means for error-correcting coding the transmission digital signal outputted from the speech coding means for transmission are provided, and output from the error correction decoding means. The received digital signal and the transmitted digital signal output from the voice encoding means are recorded. A digital signal storage device for, and to and a message recording control means. And
When the answering recording mode is set by the answering recording control means, the transmission digital signal output from the voice encoding means is stored in the digital signal storage element, and the answering recording mode is set. When an incoming call occurs, the transmission digital signal stored in the digital signal storage element is read and supplied to the error correction coding means, and the reception digital signal output from the error correction decoding means is stored in the digital signal storage. The received digital signal stored in the digital signal storage element is read out and stored in the element, and the voice decoding means decodes and reproduces the received digital signal in a state where the absence recording / playback mode is set.

Further, according to the present invention, as the above-mentioned absence recording control means, when an incoming call occurs in a state where the absence recording mode is set, the operation of reading the transmission digital signal stored in the digital signal storage element and the error correction decoding are performed. The storage operation of the received digital signal output from the means is performed in synchronization with the timing of the transmission slot and the reception slot of the time division multiplex transmission signal, respectively.

[0008]

As a result of taking the above measures, the following effects occur. That is, since the reception signal and the transmission signal are stored in the state of the digital signal encoded by the voice encoding circuit already provided in the digital wireless communication device, a digital storage element such as an IC memory card is used as a recording medium. Can be used. For this reason, the device can be significantly reduced in size and weight as compared with the case where an analog recording device using a magnetic tape is used. This reduction in size and weight is an extremely important effect for improving portability in mobile phones and cordless phones. Further, in the digital wireless telephone device, highly efficient encoding is performed as compared with a general voice encoding system. Therefore, by storing the high-efficiency coded digital signal as it is, it is possible to record for a long time without preparing a large-capacity memory.

Further, the digital radio communication device carries out time division multiplex transmission. Therefore, paying attention to this point,
By performing the read operation of the answering machine response signal and the storage operation of the received voice signal respectively in synchronization with the timings of the transmission slot and the reception slot, it is possible to apparently simultaneously perform the answering machine response and the absence recording.

[0010]

EXAMPLE An example of the present invention will be described below.

FIG. 1 is a circuit block diagram showing the configuration of an automobile radio telephone apparatus according to an embodiment of the present invention. This car radio telephone device is a digital mode type device, which digitizes a voice signal and, for example, QPSK (Quad
raturePhase Shift Keying) is used for communication with a base station (not shown).

In FIG. 1, this vehicle radio telephone device includes an antenna 1, a duplexer (DUP) 2, and a receiving circuit (R).
X) 3, frequency synthesizer (SYN) 4, transmission circuit (TX) 5, and digital modulation / demodulation circuit (MOD) 6
, An equalizer (EQL) 7, an error correction code decoding circuit (C
H-COD) 8, IC memory card interface circuit 9, IC memory card 10, voice code decoding circuit (SP-COD) 11, receiver 12, and transmitter 13.
And a control circuit (CONT) 14 and a console unit (CU) 15.

The digital modulation / demodulation circuit 6 digitally demodulates the received intermediate frequency signal and outputs a digital demodulated signal, and also generates a modulated signal of an intermediate frequency according to the digital transmission signal supplied from the error correction code decoding circuit 8. To do. The error correction code decoding circuit 8 error-correction-codes or error-correction-decodes the received digital speech signal or the transmitted digital speech signal, respectively, and outputs them.
The voice code decoding circuit 11 encodes or decodes the input analog voice signal or digital voice signal, for example, at a rate of 8 kbps, respectively.

IC memory card interface circuit 9
Is provided between the error correction code decoding circuit 8 and the voice code decoding circuit 11 as shown in the figure, and performs a predetermined interface operation for the IC memory card. FIG. 2 is a circuit block diagram showing the configuration of the IC memory card interface circuit 9 together with its peripheral circuits.

In this figure, the interface circuit 9
Are selectors 9a, 9b, 9c, a serial / parallel converter (S / P) 9d, a parallel / serial converter (P / S) 9e, and a 3-state bus transceiver (I / P).
O) 9f and a timing control circuit 9g.
The selector 9a receives the received digital speech signal supplied from the error correction code decoder 8 and the voice code decoder 1
The transmission digital call signal supplied from 1 is selectively supplied to the serial / parallel converter 9d according to a predetermined control. The serial / parallel converter 9d is the selector 9 described above.
The received digital call signal or the transmitted digital call signal output from a is converted into parallel data, and this parallel data is supplied to the IC memory card 10 via the 3-state bus transceiver 9f. The parallel / serial converter 9e converts parallel data read from the IC memory card 10 via the 3-state bus transceiver 9f into serial data.

The selector 9b selectively supplies the serial data supplied from the parallel / serial converter 9e and the transmission digital speech signal supplied from the error correction code decoding circuit 8 to the voice code decoder 11 according to a predetermined control. .. The selector 9c selectively supplies the serial data supplied from the parallel / serial converter 9e and the digital audio signal supplied from the audio code decoder 11 to the error correction code decoder 8 under predetermined control. The timing control circuit 9g controls the operation timing of each circuit, and supplies the address data to the IC memory card according to the address instruction data supplied from the control circuit 14 via the IC memory card address instruction data bus 9j. .. 9h is an IC memory card data bus, 9i
Is an IC memory card address bus.

The IC memory card 10 is a high-density integrated semiconductor memory device, which stores the digital audio signal supplied from the interface circuit 9 and outputs the stored digital audio signal to the interface circuit 9.

The control circuit 14 includes interface circuit control means 14a in addition to normal control such as call channel establishment control associated with incoming and outgoing calls. The interface circuit control means 14a controls the operation of the interface circuit 9 according to each operation mode of the answering machine mode, the incoming message reproduction mode and the response message recording mode.
The answering machine mode automatically responds when an incoming call signal arrives, reproduces a response message stored in advance in the IC memory card 10 and sends it to the calling party, and at the same time, a receiving digital signal coming from the calling party. A call signal (incoming message) is stored in the IC memory card 10. In the incoming message reproduction mode, the received digital call signal stored in the IC memory card 10 is read and the voice is output from the handset 12. In the response message recording mode, the response message sent to the calling side after the incoming call response is stored in the IC memory card 10.

The console unit 15 is provided with a switch unit such as a group of dial keys and function keys and a display unit such as a light emitting diode and a liquid crystal display, and specifies a desired operation among the above operation modes. In addition to inputting information and supplying this mode information to the control circuit 14, a predetermined operation instruction signal relating to the operation of the interface circuit 9 is supplied to the control circuit 14 during operation in each of the above modes. Reference numeral 16 is a power supply circuit that generates a predetermined operating voltage based on the output of the battery 16a. Next, the operation of the automobile telephone device configured as described above will be described with reference to FIG. 3 and FIG.

First, when the normal operation mode is set, the selectors 9b and 9c are set to the L side. In this state, a wireless communication signal sent from a base station (not shown) in a predetermined time slot is transmitted to the antenna 1
And the receiving circuit (RX) 3 via the duplexer (DUP) 2
Is input to the frequency synthesizer (SYN) 4 and is combined with the local oscillation signal output from the frequency synthesizer (SYN) 4 to be converted into an intermediate frequency signal. The received intermediate frequency signal is digitally demodulated after being frame-synchronized and bit-synchronized by a digital modulation / demodulation circuit (MOD) 6.
The synchronization signal obtained by the frame synchronization and the bit synchronization is supplied to the control circuit (CONT) 15.

The digital demodulation signal output from the digital modulation / demodulation circuit 6 includes a digital speech signal and a digital control signal, of which the digital control signal is supplied to the control circuit 15 for identification. On the other hand, the digital speech signal is supplied to an equalizer (EQL) 7, where signal demodulation of the demodulated waveform is performed. Then, after being subjected to error correction decoding by the error correction code decoding circuit (CH-COD) 8, it is input to the selector 9b in the IC memory card interface circuit 9. At this time, since the selector 9b is set to the L side as described above, this selector 9b
The digital speech signal input to the above is supplied to a voice code decoding circuit (SP-COD) 9. Then, after being decoded by the voice code decoding circuit 9 and converted back into an analog call signal, the voice signal is supplied to the handset 11, and the voice is output from the handset 11.

On the other hand, the transmission signal output from the transmitter 12 is input to the voice encoding / decoding circuit 9 where it is encoded. The digital transmission signal obtained by this encoding is supplied to the selector 9c in the interface circuit 9. At this time, since the selector 9c is set to the L side as described above, the digital transmission signal input to the selector 9c is processed by the error correction code decoding circuit 8 together with the digital control signal output from the control circuit 14. After being error-correction coded, it is input to the digital modulation / demodulation circuit 6.
The digital modulation / demodulation circuit 6 generates a modulation signal of an intermediate frequency according to the digital transmission signal supplied from the error correction code decoding circuit 8 and inputs it to the transmission circuit (TX) 5. In the transmission circuit 5, the above-mentioned modulated signal is combined with the local oscillation signal output from the frequency synthesizer 4 and converted into a high frequency signal. This high frequency signal is high frequency amplified and then transmitted from the antenna 1 to the base station via the duplexer 2. Sent to you.

Next, the operation in the response message recording mode will be described. It is assumed that an instruction signal to start recording the response message is input to the control circuit 14 from the console unit 15. When the control circuit 14 detects the arrival of the instruction signal in step 5a as shown in FIG. 5, the selector 9a is set to the L side in step 5b and the IC memory card address instruction data bus 9j is used. The start address data for storing the response message 11 is supplied to the timing control circuit 9g. On the other hand, the response message input from the transmitter 13 is subjected to predetermined processing as described above and then input to the selector 9a as serial data. Since the selector 9a is set to the L side as described above,
The serial data is guided to the serial / parallel converter 9d and converted into parallel data, and then sequentially stored from the response message start address of the IC memory card 10 via the bus transceiver 9f. At this time, the timing control circuit 9g sequentially increments the access address of the IC memory card 10 according to the address data supplied from the control circuit 14 via the memory card address designation data bus 9j. And
In step 5d, when the console unit 15 detects a signal to end the recording of the response message, the recording operation of the response message ends. Next, the operation in the answering machine mode will be described.

It is assumed that the control signal for designating the answering machine mode is supplied from the console unit 15 to the control circuit 14. Then, the control circuit 14 enters the incoming call waiting state based on the mode information sent by the control signal.

In this state, it is assumed that an incoming call signal (ringing signal) arrives from the base station (not shown) to the car telephone device. When the arrival of the incoming call signal is detected, the control circuit 14 first makes a ringer call a predetermined number of times in step 3a and then performs a response (off-hook) control to this ringer call, as shown in FIG. Then, in step 3b, the selector 9c is set to the H side, and in step 3c, reading of the response voice data from the IC memory card 10 is started. That is, the control circuit 1
4 is the IC memory card address designation data bus 9j
The start address data of the storage area in which the response digital voice data (response message) is stored is supplied to the timing control circuit 9g via. The timing control circuit 9g outputs I according to the start address data.
The start address of the response voice data stored in the C memory card 11 is accessed to start reading the response voice data. The response voice data read from the IC memory card 10 is input to the parallel / serial converter 9d via the bus transceiver 9f and is converted into serial data here. The timing control circuit 9g sequentially increments the access address of the IC memory card 10 while reading the response voice data. The serial data output from the parallel / serial converter 9d is input to the selector 9c. Since the selector 9c is set to the H side as described above, the serial data is input to the error correction code decoding circuit 6, subjected to the predetermined processing as described above, and then transmitted to the base station.

When the reading and transmission of the response voice data are completed as described above, the control circuit 1 is operated at step 3d.
4 sets the selector 9a to the H side, and starts recording the incoming message in step 3e. That is, an incoming message coming from the base station is received by the antenna 1 and then subjected to the above-mentioned processing to be supplied as a digital call signal to the interface circuit 9. Then, it is supplied to the serial / parallel converter 9d via the selector 9a in the interface circuit 9 and converted into, for example, 8-bit parallel data, and then the bus transceiver 9f.
Is supplied to the IC memory card 10 via. On this occasion,
The control circuit 14 supplies the address instruction data to the timing control circuit via the IC memory card address instruction data bus 9j. The timing control circuit 9g accesses the top address of the empty area of the IC memory card 10 and sequentially outputs the above 8-bit parallel data to the IC memory card 10.
Write in. During the writing of the parallel data, the timing control circuit 9g sequentially increments the access address of the IC memory card 10.

Now, when the caller finishes speaking the message and goes on-hook, the end signal is sent from the base station, but the control circuit 14 monitors the arrival of the end signal in step 3f. When the end-of-call signal is detected, the recording of the incoming message is completed, and the selectors 9a and 9 are selected in step 3g.
After setting c to the L side and returning to the incoming call waiting state, the call end control is performed in step 3h. It should be noted that the procedure similar to the above can be performed when the response message is reproduced for confirmation after recording the response message.
Next, the operation in the incoming message reproduction mode will be described.

In the above answering machine mode, there is an incoming call and I
It is assumed that an incoming message is stored in the C memory card 10. In order to output this incoming message from the handset 12 as voice, it is assumed that an instruction signal for starting the reproduction of the incoming message is input to the control circuit 14 from the console unit 15. When the control circuit 14 detects the control signal in step 4a as shown in FIG.
After setting the selector 9b to the H side with b, step 4
In c, the reproduction control of the incoming message stored in the IC memory card 10 is performed. That is, the control circuit 14
First, the start address data of the address in which the incoming message is stored is supplied to the timing control circuit 9g via the IC memory card address designating data bus 9j. The timing control circuit 9g accesses the start address of the incoming message stored in the IC memory card 10 in accordance with the stard address data,
Start reading audio data. Since the read voice data is parallel data, it is input to the parallel / serial converter 9e and converted into serial data, and then input to the selector 9b. As described above, the selector 9b is H
Since it is set to the side, the serial data is guided to the voice code decoding circuit 11 and subjected to a predetermined process, and then output as voice from the handset 13. During the reading of the incoming message, the timing control circuit 9g sequentially increments the access address of the IC memory card 10. When all the reading of the incoming message is completed in this way, the timing control circuit 9g generates an end signal for notifying that, and this end signal is supplied to the control circuit 14. The control circuit 14 monitors the arrival of the end signal in step 4d. When the arrival of the end signal is detected, the selector 9b is set to the L side in step 4f and the reproduction of the incoming message is ended. Also,
In step 4e, the control circuit 14 monitors the arrival of the control signal for instructing the suspension of reading. Then, when the control signal comes from the console unit 15 during the reading of the incoming message, the control circuit 14 sets the selector 9b to the L side in step 4f in the same manner as described above, and ends the incoming message reproduction.

As described above, according to this embodiment, since the digital speech signal encoded by the voice code decoding circuit 11 provided as an indispensable circuit in the digital car telephone system is recorded, the recording medium is used. As a semiconductor memory such as an IC memory card can be used as the device, the size and weight of the device can be significantly reduced as compared with the case where a recording device using a magnetic tape is used. Further, since the existing code decoding circuit is used, it is not necessary to provide a new code decoding circuit, and as a result, there is an advantage that the circuit can be realized without complication. Moreover, the digital radio telephone apparatus performs highly efficient encoding as compared with a general voice encoding method. Therefore, by storing such a high-efficiency coded digital speech signal, it is possible to store for a long time in a small capacity storage element. By the way, in the present embodiment, the coding speed of the voice code decoding circuit 11 is set to 8 kb.
If ps is set and the storage capacity of the IC memory card 10 is set to 2 Mbytes, recording can be performed for about 35 minutes.

The IC memory cards 10 and I
Since the C memory card interface circuit 9 is integrated with the automobile telephone device, it is possible to realize a device that is very easy to operate. Further, the circuit to be added to the digital car telephone device is only the IC memory card interface circuit 9 and the control software corresponding to each mode. Even if the answering machine function is added, the car telephone body can be easily miniaturized, and at the same time, it is very It is possible to add an answering machine function at low cost. Further, since IC memory cards with various capacities are available, it is possible to select the optimum memory capacity according to the request of the subscriber. If an IC memory card using a RAM having a backup power supply is used, incoming messages and response messages can be stored.

The present invention is not limited to the above embodiment. For example, in the present embodiment, it has been individually described that the voice data write control to the IC memory card 10 and the storage content recall control stored in the IC memory card 11 are not performed at the same time. However, in the digital car telephone system, the time division multiplexing technique is used for the communication system, and the reception slot and the transmission slot do not overlap in time, so that the IC memory card 11 described above is used.
By controlling the writing of the received message to and the reading of the response message in synchronization with the reception slot and the transmission slot, respectively, it is possible to apparently simultaneously perform the recording of the reception message and the reproduction of the response message.

Further, in the above embodiment, the case where the voice data is recorded on the so-called answering machine function of automatically recording the incoming message after automatically responding to the incoming call has been described.
It can also be applied when recording information data in fax communication. In addition, it goes without saying that various modifications can be made to the configuration of the digital wireless communication device, the communication system to which it is applied, the storage element for storing voice data, and the like without departing from the scope of the present invention.

[0033]

Since the voice signal and the voice signal are encoded by the voice encoding circuit already provided in the digital radio communication device, it is possible to use a digital storage element as a recording medium. For this reason, the device can be significantly reduced in size and weight compared to the case where an analog recording device is used, and the digital wireless telephone device performs highly efficient encoding as compared with a general voice encoding method. Therefore, the digital storage element used can have a small capacity. Further, since the digital storage element and the circuit for controlling the input / output of digital signals to / from the digital storage element are integrated with the automobile telephone device, it is possible to realize a device which is very easy to operate. As a result, it is possible to provide a small and lightweight wireless communication device having an answering recording function and an answering recording function which are excellent in operability.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing the configuration of a car telephone system according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a configuration of the IC memory card shown in FIG.

FIG. 3 is a flowchart showing a control procedure and control contents of the control circuit shown in FIG. 1 in an answering machine mode.

FIG. 4 is a flowchart showing a control procedure and control contents of the control circuit shown in FIG. 1 in an incoming message reproduction mode.

5 is a flowchart showing a control procedure and control contents of the control circuit shown in FIG. 1 in a response message recording mode.

[Explanation of symbols]

1 ... Antenna, 2 ... Duplexer (DUP), 3 ... Reception circuit (RX), 4 ... Frequency synthesizer (SYN), 5 ... Transmission circuit (TX), 6 ... Digital modulation / demodulation circuit (MO)
D), 7 ... Equalizer (EQL), 8 ... Error correction code decoding circuit (CH-COD), 9 ... IC memory card interface circuit, 9a, 9b, 9c ... Selector, 9d ... Serial / parallel converter (S / P), 9e ... Parallel-serial converter (P / S), 9f ... 3-state bus transceiver (I / O), 9g ... Timing control circuit, 9h ... I
C memory card data bus, 9i ... IC memory card address bus, 9j ... IC memory card address instruction data bus, 10 ... IC memory card, 11 ... Voice code decoding circuit (SP-COD), 12 ... Receiver, 13 ... Transmitting vessel,
14 ... Control circuit (CONT), 15 ... Console unit (CU), 16 ... Power supply circuit, 16a ... Battery.

Claims (3)

[Claims] 1. A wireless communication apparatus having a digital mode as a wireless communication system for digitizing a call signal by a predetermined code decoding system and transmitting and receiving the same, and an error correction decoding means for performing error correction decoding of a received digital signal and outputting it. The received digital signal output from the error correction decoding means is decoded to reproduce the analog reception signal, and the voice decoding means for providing the analog reception signal for the loud output, and the reception digital signal output from the error correction decoding means With the digital signal storage element for storing and the answer recording mode set, the received digital signal output from the error correction decoding means is stored in the digital signal storage element, and the answer recording playback mode is set. Received signal stored in the digital signal storage element under Wireless communication apparatus according to claim Le signal reads it has and a message recording control means for decoding reproduced to the audio decoding means. 2. An error correction decoding means for performing error correction decoding on a received digital signal and outputting the received digital signal in a wireless communication device having a digital mode for digitizing and transmitting and receiving a call signal by a predetermined code decoding system as a wireless communication system. A voice decoding means for decoding the received digital signal output from the error correction decoding means to reproduce the analog reception signal and providing the analog reception signal for the loud output, and for encoding the analog transmission signal to output the transmission digital signal. Audio coding means, error correction coding means for error-correcting coding the transmission digital signal output from the speech coding means for transmission, and the received digital signal and the speech output from the error correction decoding means. Digital signal storage for storing the transmitted digital signal output from the encoding means When the answering recording mode is set, the transmission digital signal output from the voice coding means is stored in the digital signal storage element, and an incoming call occurs in the absence recording mode. In this case, the transmission digital signal stored in the digital signal storage element is read and supplied to the error correction coding means, and the reception digital signal output from the error correction decoding means is stored in the digital signal storage element. And an answering / recording control means for reading the received digital signal stored in the digital signal storage element and for decoding / reproducing by the voice decoding means in a state where the answering / recording / playback mode is set. Wireless communication device. 3. The answering machine recording control means reads out the transmission digital signal stored in the digital signal storage element and outputs from the error correction decoding means when an incoming call occurs in a state where the answering machine recording mode is set. 3. The wireless communication apparatus according to claim 2, wherein the storage operation of the received digital signal thus received is performed in synchronization with the timing of the transmission slot and the reception slot of the time division multiplex transmission signal.