JPH05103021A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by inactivating a line driver when a transmission line has no signal in the semiconductor integrated circuit provided with a line receiver and the line driver. CONSTITUTION:A signal on a transmission line received by a line receiver 3 is shifted by 3-stages shift registers 13-15 and output signals at terminal Q S0-S2 are inputted to an OR gate 16. The integrated circuit 1 is provided with a standby circuit 12 receiving a standby signal STBY being an output signal of the OR gate and applying the signal to an operating state control terminal C of a line driver 4. When the standby signal STBY in at a low level, the line driver 4 is inactivated and when the standby signal STBY is at a high level, the line driver 4 is activated, then useless power consumption is avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit having a line driver and a line receiver.

[0002]

2. Description of the Related Art CCITT Recommendation I. In the basic interface defined by 430, the signal when communicating at the point S which is the specified point is AMI (Alternate Mark Inverse).
ion) code is used. In this AMI code, no signal on the line represents a binary "1", and a binary "0" represents a positive or negative pulse. A dedicated line driver and line receiver are required to transmit and receive such signals.

Conventionally, a line driver and a line receiver of a semiconductor integrated circuit and a digital circuit are block-structured as shown in FIG. The integrated circuit 1a is a digital circuit 2a for inputting the line receiver 3 for inputting the received signal 5 through the receiving transformer 7, the line receiver "+0" side output signal LI1 and the line receiver "-0" side output signal LI2. And a line driver 4 that receives the output signal and outputs a transmission signal 6 via a transmission transformer 8.
have.

VDD is a power supply terminal, GND is ground,
Reference numeral 9 is a general output terminal, 10 is a general input / output terminal, and 11 is a general input terminal. The line receiver input terminal LIN is connected to one terminal of the coil L1 of the receiving transformer 7, and the line receiver reference terminal REF is connected to the coil L1.
Of the transformer 7, and the coil L2 of the transformer 7 is connected to the reception line having point S, which is a specified point on the transmission line. The line driver positive side output terminal LO + is connected to one terminal of the coil L1 of the transmission transformer 8, the line driver negative side output terminal LO− is connected to the other terminal of the coil L1, and the coil L2 of the transformer 8 is connected. Is connected to the transmission line at point S.

CCITT I.D. If the integrated circuit is for a network terminating device (hereinafter referred to as NT), the received signal at the point S is INFO0, INFO1, I as defined in 430.
There are three types of NFO3. If the integrated circuit is for a terminal device (hereinafter referred to as TE), the received signal at point S is IN.
There are three types, FO0, INFO2, and INFO4. INFO0 is no signal, INFO1 and INFO2 are activation request frames, and INFO3 and INFO4 are general data frames.

Normally, when NT and TE are communicating, INFO4 is transmitted from NT to TE, and INFO3 is transmitted from TE to NT. On the other hand, in the stopped state, N
There is no signal from T to TE direction and from TE to NT direction I
NFO0 is being transmitted.

[0007]

Conventionally, since the line driver and line receiver of the semiconductor integrated circuit described above are in the operating state while receiving INFO0 and even while transmitting INFO0, a current flows and the integrated circuit It has the disadvantage of wasting most of the power.

[0008]

In the semiconductor integrated circuit of the present invention, a transmission signal and a reception are provided between an external transmission line having a defined point S and an internal logic circuit via a line driver and a line receiver, respectively. In a semiconductor integrated circuit for exchanging signals, the received signal of the line receiver is input to the D terminal input of an n-stage shift register, and CL
A clock having the same speed as the bit rate of the received signal is input to the K terminal, the Q terminal is connected to each input terminal of an n-input OR gate, and the OR output signal is used as a standby signal to operate the line driver. A standby circuit supplied to the control end is added to the logic circuit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A and 1B are block diagrams of an embodiment of the present invention and an example of a standby circuit. In FIG. 1A, the integrated circuit 1 is a digital circuit 2 and the integrated circuit 1 of FIG.
The standby circuit 12 is added to the digital circuit 2a of a,
Further, it is the same as the conventional integrated circuit 1a of FIG. 5 except that an operation state control circuit based on a signal from the operation state control terminal C is added to the line driver 4a. Here, the output signal STBY of the standby circuit 12 is input to the operation state control terminal C of the line driver 4.

FIG. 1B is a circuit diagram of a standby circuit for TE. The terminal TI2 supplies the line receiver [−0] side output signal LI2 to the first stage D input terminals of the three-stage D flip-flops with a set (hereinafter referred to as D-FF) 13 to 15. The Q-terminal output signals S0 to S2 of Q0 to Q2 of the D-FFs 13 to 15 are input to the 3-input OR gate 16, and this output is used as the standby signal STBY. D
A 192 KHz clock CLK is input to the CK end of the -FF. At the S input terminal of D-FF, TE status display signal F
Enter 47. Here, as for the signal F47, the transition state of TE is F4 (a state in which INFO1 which is a start request signal of itself is transmitted and is waiting for a signal from NT) or F7.
It is a signal that becomes high level when it is in the (starting state).

Next, the operation of the block of FIG. 1 will be described with reference to the timing chart of FIG. Since the line receiver input terminal LIN is connected to the reference terminal REF in a DC manner by the receiving transformer 7, the terminal REF
The same DC voltage as is applied. Therefore, the terminal REF
The AMI code is applied based on the voltage of. LI1,
LI2 is the "+0" side and [-0] side output of LIN, respectively, and both outputs are low level when "1".
Therefore, the output signal LI2 is always at the low level when receiving INFO0, and becomes as shown in the timing chart when receiving INFO2. The signal rule of INFO2 is "+
Since three of either "0" or "1" do not continue, the low level of the signal LI2 does not last for three clocks of the clock CLK.

From the above, STBY which is the output of the OR gate 16 is low level when INFO0 is received, and INFO is
2 High level when receiving. In addition, transition state F4,
In the case of F7, the TE state display signal F47 is set to high level and STBY is forcibly set to high level. This STBY
Is low, the line driver 4 is inactive, and high is active.

FIG. 3 is a block diagram of the standby circuit for NT. The terminal TI2 receives the output signal LI2 on the line receiver [−0] side of FIG. To be done. The Q terminal output signals S0 to S7 of Q0 to Q7 of the D-FF are input to the input terminals of the OR gate 16a, and this OR output signal is used as the standby signal STBY. The S input terminal of the D-FF is connected to the ET status display signal G23.
Enter. Here, as for the display signal G23, the transition state of NT is G2 (a state in which INFO2, which is a start request signal of itself, is transmitted and a signal from TE is waiting) or G3.
It is a signal that becomes high level when it is (starting state).

Next, the operation of the block shown in FIG. 3 will be described with reference to the timing chart shown in FIG. As described above, the output signal LI2 is always at the low level when receiving INFO0, and becomes as shown in the timing chart when receiving INFO1. According to the signal rule of INFO1, the combination of “+0” and “−0” sandwiches six “1”, so the output signal L
The low level of I2 does not last for 8 clocks of CLK.

From the above, STBY, which is the OR output signal of the OR gate 25, is low level when INFO0 is received,
It becomes high level when receiving INFO1. In the case of the transition states G2 and G3, the NT state display signal G23 is set to the high level, and STBY is forcibly set to the high level. When this STBY is at a low level, the line driver 4 is inactive, and when it is at a high level, it is in operation.

[0016]

As described above, the present invention is based on INFO.
At the time of 0 reception, the line driver is made inactive so that the current consumption is almost only the line receiver consumption. Therefore, the power consumption of the semiconductor integrated circuit is reduced, and the terminal device is reduced in the power supply at the time of the limited power supply. The private branch exchange has the effect of reducing the average power consumption.

[Brief description of drawings]

1A and 1B are block diagrams of an embodiment of the present invention and an example of a standby circuit.

FIG. 2 is a timing chart of each signal for explaining the operation of the block of FIG.

FIG. 3 is a block diagram of another example of the standby circuit of FIG.

4 is a timing chart of each signal for explaining the operation of the block of FIG.

FIG. 5 is a block diagram of an example of a conventional integrated circuit.

[Explanation of symbols]

 1 integrated circuit 2 digital circuit 3 line receiver 4 line driver 5 reception signal 6 transmission signal 7 reception transformer 8 transmission transformer 9 general output terminal 10 general input / output terminal 11 general input terminal 12, 12a standby circuit 13-20 with set D Type flip-flop 16,16a OR gate LIN line receiver input terminal REF line receiver reference terminal LO + line driver positive side output terminal LO− line driver negative side output terminal C operating state control end LI1 line receiver “+0” Side output signal LI2 Line receiver [-0] side output signal F47 TE F4 or F7 status display signal G23 NT G2 or G3 status display signal STBY Standby signal CLK clock S0 to S7 Q terminal output signal

Claims (1)

[Claims] 1. A semiconductor integrated circuit for exchanging a transmission signal and a reception signal between an external transmission line having a defined point S and an internal logic circuit via a line driver and a line receiver, respectively. The reception signal of the receiver is input to the D-terminal input of the n-stage shift register, and the clock having the same speed as the bit rate of the reception signal is input to the CLK terminal, and the Q-terminal is each input of the n-input OR gate. A semiconductor integrated circuit characterized in that a standby circuit, which is connected to an end of the line driver and supplies an OR output signal as a standby signal to an operation state control end of the line driver, is added to the logic circuit.