JPH05102830A - Buffer circuit - Google Patents

Abstract

PURPOSE:To suppress an excess current of the output buffer circuit including a load capacity charge/discharge current to a setting current or below. CONSTITUTION:The buffer output circuit connected in cascade to an inverter circuit comprising a P-channel MOS transistor(TR) 1 and an N-channel MOS TR 2 is provided with an N-channel MOS TR 3 whose source receives an output 102 of the inverter circuit and whose gate is connected to a power supply via a resistor 7, a P-channel MOS TR 4 whose source receives the output 102 of the inverter circuit and whose gate is connected to a ground potential via a resistor 8, a P-channel MOS TR 5 whose source is connected to a gate of the TR 3, whose gate is connected to a drain of the TR 3 and whose drain is connected to an output terminal, and an N-channel MOS TR 6 whose source is connected to a gate of the TR 4, whose gate is connected to a drain of the TR 4 and whose drain is connected to the output terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit, and more particularly to a buffer circuit having a CMOS structure.

[0002]

2. Description of the Related Art Conventionally, a buffer circuit having a CMOS structure has an inverter formed of a P channel MOS transistor 23 and an N channel MOS transistor 24 corresponding to a load capacitance 27, as shown in FIG. Inverter-type circuits composed of an inverter formed by a P-channel MOS transistor 25 and an N-channel MOS transistor 26 are often used, and the gate output of the preceding stage is often directly connected to the input side of the buffer circuit. ..

[0003]

In the conventional buffer circuit described above, since the steep rising / falling waveform of the preceding stage gate output is directly input to the buffer circuit, the waveform of the buffer output also rises / falls. Both have steep waveforms, and in addition, a maximum current transiently flows due to charging / discharging of the load capacitance, causing the potentials of the source power supply and ground to float due to the voltage drop of the wiring, etc. There is a drawback that it causes malfunctions and the like.

[0004]

According to a first aspect of the present invention, in a buffer circuit having a CMOS structure, a buffer output circuit cascade-connected to an inverter circuit forming a predetermined preceding stage serves as a source and outputs the inverter circuit. Is input, a gate is connected to a high-potential power supply through a first resistor, an output of the inverter circuit is input to a source, and a gate is input via a second resistor. A first P-channel MOS transistor connected to a low-potential power source, a source connected to the gate of the first N-channel MOS transistor, and a gate connected to the drain of the first N-channel MOS transistor, A second P-channel MOS transistor having a drain connected to the output terminal, and a source having the first P-channel Is connected to the gate of the OS transistor, a gate connected to the drain of said first P-channel MOS transistor, a second N-channel MOS transistor having a drain connected to said output terminal,
It is configured with.

The buffer circuit of the second invention is a CM.
In a buffer circuit having an OS configuration, as a buffer output circuit that is cascade-connected to an inverter circuit that forms a predetermined preceding stage, the output of the inverter circuit is input to the source, and the gate serves as a high-potential power source via the first resistor. A first N-channel MOS transistor connected to the source, an output of the inverter circuit is input to the source, a first P-channel MOS transistor having a gate connected to a low-potential power source through a second resistor, and a source Is connected to the gate of the first N-channel MOS transistor, the gate is connected to the drain of the first N-channel MOS transistor via a third resistor, and the drain is connected to the output terminal. A P-channel MOS transistor and a source connected to the gate of the first P-channel MOS transistor, Said first P but via a fourth resistor
Connected to the drain of the channel MOS transistor,
A second N-channel MOS transistor having a drain connected to the output terminal, a source connected to a high-potential power supply, a gate connected to the gate of the second P-channel MOS transistor, and a drain connected to the output terminal. A third P-channel MOS transistor connected to the second P-channel MOS transistor, a source connected to a low-potential power supply, a gate connected to the gate of the second N-channel MOS transistor, and a drain connected to the output terminal. 3 N-channel MOS
And a transistor.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, an inverter circuit formed of P channel MOS transistor 1 and N channel MOS transistor 2, N channel MOS transistor 3 and P channel MOS transistor are provided corresponding to load capacitance 9. 4, an P-channel MOS transistor 5, an N-channel MOS transistor 6, and an inverter buffer circuit formed by resistors 7 and 8.

In FIG. 1, an input signal 101 is input to an inverter circuit formed by P channel MOS transistor 1 and N channel MOS transistor 2, output as signal 102, and N channel MOS transistor 3 and P channel MOS transistor 4 are input. of,
Input to each source. This inverter circuit itself is a circuit that has been conventionally used, but the feature of the present invention resides in the inverter buffer circuit having the above-described configuration.

Charging of the load capacitor 9 through the buffer output signal 107 output from the drain of the P channel MOS transistor 5 forming the inverter buffer circuit is completed, and the P channel MOS transistor 5 is completed.
When the signal 106 output from the source of the N channel MOS transistor 6 becomes the power supply voltage level and the signal 106 at the source of the N channel MOS transistor 6 becomes the ground potential level, the N channel M
OS transistor 3 and P-channel MOS transistor 4
Are both turned on. In the case where the signal 102 output from the inverter circuit in the previous stage is at “1” level,
P-channel MOS transistor 5 is in the off state, N-channel MOS transistor 6 is in the on state, and buffer output signal 107 tends to decrease in level to the ground potential via resistor 8 and N-channel MOS transistor 6. However, a current flows through the resistor 8 and the N-channel MOS transistor 6, and the resistor 8 is caused by this current.
The gate potential of the P-channel MOS transistor 4 floats due to the voltage drop at, and the P-channel MOS transistor 4 is turned off. For this purpose, P-channel MOS
The drain of the transistor 4 is in the level holding state, the potential immediately before that is held as it is, and the current limited by this potential level is in the state of flowing into the N-channel MOS transistor 6 and the resistor 8.

When the discharge in the load capacitance 9 approaches the completion and the discharge current decreases, the voltage drop in the resistor 8 decreases, the P-channel MOS transistor 4 returns to the ON state, and the drain potential of the P-channel MOS transistor 4 changes. It rises, and correspondingly increases the current flowing through the N-channel MOS transistor 6 to operate so as to maintain the current at a predetermined set value. However, the current required in the load is the N-channel MOS transistor 6
When the driving capacity is less than that, the current more than required cannot flow, and the buffer output signal 107 eventually reaches the ground potential level, and the current stops flowing. Similarly, the voltage drop across the resistor 7 limits the potential of the drain of the N-channel MOS transistor 3, thereby limiting the drive capability of the P-channel MOS transistor 5 and setting the current flowing through the P-channel MOS transistor 5. It is possible to limit it to a value or less.

As described above, the excessive current generated in the inverter buffer circuit, including the current due to the charging / discharging of the load capacitance and the through current resulting from the simultaneous ON state of the P-channel MOS transistor 5 and the N-channel MOS transistor 6, It can be limited to a predetermined set value or less.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. As shown in FIG. 2, this embodiment corresponds to the load capacitance 22 and corresponds to the P-channel MOS transistor 10.
And an inverter circuit formed by N channel MOS transistor 11, N channel MOS transistors 12, 17 and 21, P channel MOS transistors 13, 16 and 20, resistors 14, 15, 18 and 1.
And an inverter buffer circuit formed by 9.

The difference between this embodiment and the first embodiment is that in the inverter buffer circuit, the resistors 14 and 15 are used.
By expanding the control range of the drain potentials of the N-channel MOS transistor 12 and the P-channel MOS transistor 13, and as a function of the P-channel MOS transistor 16 and the N-channel MOS transistor 17 connected to the resistors 18 and 19. , Resistance 18
The main focus is to expand the control range of the resistance voltage dividing ratio with respect to 19 and 19, and for driving the load capacitance 22,
P-channel MOS transistor 20 and N-channel MOS
That is, the transistor 21 is mainly used. The basic operation is the same as in the case of the first embodiment described above.

[0014]

As described above, according to the present invention, in the inverter type buffer circuit, the level of the source power supply and the ground potential is lowered by limiting the current flowing through the MOS transistor in the output buffer circuit to the set value or less. There is an effect that it is possible to prevent the deterioration of the characteristic and the malfunction caused by the phenomenon.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1, 4, 5, 10, 13, 16, 20, 23, 25
P-channel MOS transistors 2, 3, 6, 11, 12, 17, 21, 24, 26
N-channel MOS transistor 7, 8, 14, 15, 18, 19 Resistance 9, 22, 27 Load capacitance

Claims (2)

[Claims] 1. In a buffer circuit having a CMOS structure, as a buffer output circuit cascade-connected to an inverter circuit forming a predetermined preceding stage, an output of the inverter circuit is input to a source and a gate is connected via a first resistor. A first N-channel MOS transistor connected to a high-potential power source, and a first P-channel whose output is input to the source and whose gate is connected to a low-potential power source through a second resistor. A MOS transistor and a source are connected to the gate of the first N-channel MOS transistor, and the gate is the first N-channel MOS transistor.
A second P-channel MOS transistor connected to the drain of the transistor and having a drain connected to the output terminal; a source connected to the gate of the first P-channel MOS transistor; and a gate connected to the first P-channel MOS transistor.
A second N-channel MOS transistor connected to the drain of the transistor, the drain of which is connected to the output terminal. 2. In a buffer circuit having a CMOS structure, as a buffer output circuit cascade-connected to an inverter circuit forming a predetermined preceding stage, an output of the inverter circuit is input to a source and a gate is connected via a first resistor. A first N-channel MOS transistor connected to a high-potential power source, and a first P-channel whose output is input to the source and whose gate is connected to a low-potential power source through a second resistor. A MOS transistor and a source are connected to the gate of the first N-channel MOS transistor, and the gate is connected to the first N-channel MOS transistor via a third resistor.
Second P-channel MOS transistor connected to the drain of the N-channel MOS transistor of which the drain is connected to the output terminal, the source connected to the gate of the first P-channel MOS transistor, and the gate connected to the fourth The first through the resistor
Second N-channel MOS transistor connected to the drain of the P-channel MOS transistor, the drain of which is connected to the output terminal, and the source of which is connected to a high-potential power supply, and the gate of which is the second P-channel MOS transistor. Connected to the gate of
A third P-channel MOS transistor having a drain connected to the output terminal, a source connected to a low-potential power supply, and a gate connected to the gate of the second N-channel MOS transistor,
And a third N-channel MOS transistor having a drain connected to the output terminal.