JPH05102469A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize the characteristics that require a complicated circuit configuration in a macro device with a fine and single element. [Structure] The first gate electrode 6 is formed in a thin line shape, and the second
Gate electrodes 8 are laminated on the first gate electrode 6 with the insulating film 7 interposed therebetween, and a plurality of second gate electrodes 8 cross the first gate electrode 6 and are arranged in the channel direction in a thin line shape. A structure having an opening. [Effect] To provide a semiconductor device having a field-effect transistor which realizes new conduction characteristics by extremely strongly modulating the conductivity of the field-effect transistor by introducing a periodic potential into one-dimensional conduction with uniform propagation modes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a non-linear characteristic, and in particular, an energy band formed when a single-mode carrier due to one-dimensional conduction travels in a periodic potential. MI using the gap
S (metal Inshureita Semiconductor (M etal I ns
ulator about S emiconductor)) or MES (technique suitable for application to a semiconductor device having a metal Semiconductor (Me tal S emiconductor)) type field effect transistor.

[0002]

2. Description of the Related Art A conventional field effect transistor that modulates a current by utilizing one-dimensional conduction of carriers uses a carrier mobility modulation based on a sawtooth one-dimensional density of states.

Regarding the transistor using the carrier mobility modulation based on the sawtooth one-dimensional density of states,
For example, Applied Physics Letters, 54th
Volume, Number 12, March 1989, 1130-11
32 pages (Applied Physics Letters, vol.54, No.12, Ma
rch, 1989, pp.1130-1132).

[0004]

In the conventional transistor utilizing the carrier mobility modulation based on the sawtooth one-dimensional density of states, the current modulation is not sufficient.

It is an object of the present invention to provide a semiconductor device having a field effect transistor capable of more strongly modulating a carrier conducting one-dimensional conduction by utilizing a minienergy band gap formed in a periodic potential. It is in.

[0006]

In order to achieve the above object, the semiconductor device of the present invention is a semiconductor substrate of the first conductivity type and the above first semiconductor substrate provided on the surface of the semiconductor substrate with a predetermined space provided therebetween. A semiconductor device having a field effect transistor, comprising a source / drain region of a second conductivity type opposite to the conductivity type and a gate electrode provided on the semiconductor substrate between the source / drain regions, The gate electrode is electrically insulated from the first gate electrode forming a one-dimensional channel and the first gate electrode, the width of the channel is periodically changed, and charged particles traveling in the channel It is characterized by comprising a second gate electrode which gives periodical scattering to.

Also, in the semiconductor device of the present invention, the first gate electrode is formed in a thin line shape over the source / drain regions, and the second gate electrode is formed on the first gate electrode via an insulating film. The second gate electrode has a plurality of thin line-shaped openings arranged in the channel direction formed by the first gate electrode.

Further, in the semiconductor device of the present invention, the first gate electrodes are arranged and formed in a plurality of thin lines parallel to the channel direction over the source / drain regions and electrically connected to each other, and the second gate electrodes are electrically connected to each other. A plurality of gate electrodes are stacked on the first gate electrode via an insulating film, and a plurality of the second gate electrodes are arranged in the direction of the channel formed by the first gate electrode. It is characterized by having an opening.

Further, the semiconductor device of the present invention includes a semiconductor substrate of the first conductivity type and a second conductivity type which is the conductivity type opposite to the first conductivity type provided on the surface of the semiconductor substrate at a predetermined distance. In a semiconductor device having a field-effect transistor including a source / drain region and a gate electrode provided on the semiconductor substrate between the source / drain regions, a one-dimensional channel is formed, and the channel is formed. It is characterized in that the above-mentioned gate electrode is provided which gives periodical scattering to the charged particles traveling in the direction.

Further, the semiconductor device of the present invention is characterized in that the gate electrode has a shape having a different width in the channel direction.

Further, the semiconductor device of the present invention is characterized in that the width of the channel is 0.1 μm or less.

[0012]

The operation of the semiconductor device of the present invention will be described with reference to FIGS. 1 is a perspective view showing an example of the structure of a semiconductor device of the present invention, FIG. 2 is a plan view showing the shape of a channel of the semiconductor device of FIG. 1, and FIG. 3 is an energy band diagram in the channel of FIG. .. The horizontal axis of FIG. 3 is the wave number (10
⁷ / m), and the vertical axis represents energy (mV). Figure 4
It is a figure which shows the current-voltage characteristic of the semiconductor device of FIG. In FIG. 4, the horizontal axis represents the voltage (V) of the first gate electrode and the vertical axis represents the drain current (nA). MOS in Figure 1 (metal oxide semiconductor (M etal O xide S emiconduct
or)) is assumed to be an n-type MOS, and the following discussion will proceed. In each figure, W is the effective channel width defined by the first gate electrode 6, and the length a, b determined by the second gate electrode 8 defines the channel shape as shown in FIG. It is determined. Here, the first gate electrode 6
When a channel is formed by applying a positive potential to the first gate electrode 6, if the width of the first gate electrode 6 is sufficiently narrow, the electron energy in the channel is quantized due to the one-dimensional conduction of electrons, and the one-dimensional subband is quantized. Is formed.

When a negative potential is applied to the second gate electrode 8 in this state, the first gate electrode 6 and the second gate electrode 8
In the region overlapping with and, the inversion of the substrate is suppressed from the periphery, the potential of the channel is controlled, the width of the channel changes periodically and thinly, and the shape of the channel becomes as shown in FIG. The difference ΔW in channel width shown in FIG. 2 changes due to the action of the second gate electrode 8. Specifically, ΔW also increases as the negative potential applied to the second gate electrode 8 increases negatively. Although the electrons travel in the direction of the solid arrow in FIG. 2, they are periodically scattered in the direction of the dashed arrow, and as a result, a mini energy band and a mini energy band gap are formed as shown in FIG. However, here, the intervals between the one-dimensional sub-bands are equal, and the case where W = 0.1 μm and a + b = 0.3 μm is shown. In this state, the voltage of the first gate electrode 6 is raised. When the voltage of the first gate electrode 6 rises, the electron density in the channel portion rises. By the way, the Fermi energy E _F is given by the electron density n _s as follows.

E _F = h ² n _s ² / 8m where h is Planck's constant and m is the effective mass of the electron. That is, increasing the voltage of the first gate electrode 6 is equivalent to increasing the Fermi energy E _{F of} electrons. Explaining with reference to FIG. 3, the Fermi energy E _F rises as the voltage of the first gate electrode 6 is raised. That is, in FIG.
The Fermi energy E _F rises from the bottom. No current flows when the Fermi energy E _F passes through the mini-energy bandgap. As a result, the drain current-first gate voltage dependency of the present device is as shown in FIG. By making the conduction of electrons one-dimensional in this way, the coherency of the electrons is increased, that is, the conduction modes are aligned, and the periodic channel structure is introduced to form an energy band gap. Current modulation is possible.

[0015]

Embodiments of the semiconductor device of the present invention will be described below with reference to the drawings.

Example 1 FIGS. 5 to 8 are views showing the manufacturing process of Example 1, respectively. In this embodiment, a semiconductor device having the structure shown in FIG. 1 is manufactured. 5, 6 (a), 7 (a), and 8 are cross-sectional views, and FIGS. 6 (b) and 7 (b) are plan views, respectively. 6A and 7A are cross-sectional views taken along the line AA of FIGS. 6B and 7B, respectively. First, as shown in FIG. 5, an element isolation region 2 is formed by a resistivity 10 [Omega · cm p-type Si normal LOCOS in the substrate 1 (Loc al O xidation of S ilicon) method. Next, a gate oxide film 5 having a thickness of 10 nm is formed by a dry oxidation method at 850 ° C. for 30 minutes. Then, for the purpose of protecting the gate oxide film 5, a thickness 5
A 0 nm polycrystalline silicon film 6 is deposited. Next, a photoresist film (not shown) is applied to a thickness of 1 μm, and openings are formed at two predetermined portions for forming the source / drain regions of the photoresist film by the photo-etching method.
Arsenic ions are implanted at an accelerating voltage of 20 kV, and high concentration n
The type diffusion layer regions 3 and 4 are formed. Driving amount is 1 × 10
It was ¹⁵ cm ~ ² . Of course, these high-concentration n-type diffusion layer regions 3 and 4 may be formed by using phosphorus ions.
After that, a drive-in process is performed in a nitrogen atmosphere at 900 ° C. for 10 minutes to obtain the structure shown in FIG. Next, FIG.
As shown in (a), a thickness of 50 is formed on the polycrystalline silicon film 6.
A polycrystalline silicon film having a thickness of 10 nm is deposited (polycrystalline silicon film 6), and phosphorus is deposited at 875 ° C. for 20 minutes. After that, the polycrystalline silicon film was processed into a fine line shape by the photoetching method and the dry etching (first gate electrode 6), and the structure shown in FIGS. 6 (a) and 6 (b) was obtained. Then, as shown in FIGS. 7A and 7B, PSG (phosphosilicate) having a thickness of 50 nm is formed as an interlayer insulating film.
Glass (P hospho S ilicate G lass) ) silicon oxide film 7, such as a film is deposited by LPCVD. Next, a 100-nm-thick polycrystalline silicon film is deposited on the silicon oxide film 7, and phosphorus is deposited at 875 ° C. for 20 minutes.
After that, by photolithography and dry etching, as shown in FIG.
The shape as shown in (b) (the thin line-shaped first gate electrode 6
Then, the polycrystalline silicon film is processed into a shape in which a plurality of fine line-shaped openings crossing each other are arranged in the channel direction (second gate electrode 8). Thereafter, as shown in FIG. 8, a silicon oxide film 9 such as a PSG film having a thickness of 200 nm is deposited by LPCVD to form an interlayer insulating film 9, and a contact hole is opened by photo-etching and dry etching. Then, the structure shown in FIG. 8 was obtained. From the above, FIG.
A desired semiconductor device shown in FIG.

In the semiconductor device of this example obtained as a result of the above, the relationship between the voltage of the first gate electrode 6 and the drain current is shown in FIG. It came to be shown in. That is, by making the electron conduction one-dimensional, the coherency of the electrons is increased to align the conduction modes, and by further introducing a periodic channel structure, an energy band gap is formed, so that extremely strong current modulation is achieved. It became possible.
As described above, according to the present embodiment, the 1
The conductivity of the MISFET can be extremely strongly modulated by introducing a periodic potential into the dimensional conduction. INDUSTRIAL APPLICABILITY The present invention can realize the characteristics that require a complicated circuit configuration in a macro device with a fine and single element. In that sense, the present invention can be effectively applied to future LSIs and the like.

Second Embodiment FIG. 9A is a sectional view (a sectional view taken along the line AA in FIG. 9B) of a semiconductor device according to a second embodiment of the present invention, and FIG. 9B is a plan view. .. Using the same process as in Example 1, the shape of the first gate electrode 6 was such that a plurality of fine lines were arranged in parallel as shown in FIG. 9B. Silicon oxide film 7, second
The gate electrode 8, the silicon oxide film 9, and the aluminum wiring 10 are not shown. The difference from Example 1 is only the shape of the first gate electrode 6. In this example, the current could be significantly increased as compared with the case of the first example.

Third Embodiment FIGS. 10 to 12 are views showing a process for manufacturing a semiconductor device according to a third embodiment of the present invention. 10, FIG. 11A, and FIG. 12 are cross-sectional views, and FIG. 11B is a plan view. FIG. 11 (a)
FIG. 11 is a sectional view taken along line AA of FIG. First, FIG.
As shown in FIG. 5, the element isolation region 2 is formed on the p-type Si substrate 1 having a specific resistance of 10 Ω · cm by the normal LOCOS method. Next, a thickness of 10 n is obtained by a dry oxidation method at 850 ° C. for 30 minutes.
m gate oxide film 5 is formed. Then, for the purpose of protecting the gate oxide film 5, a polycrystalline silicon film 6 having a thickness of 50 nm is formed.
Deposit. Next, a photoresist film (not shown) with a thickness of 1 μm
Thickness is applied, and openings are provided at two predetermined portions for forming the source / drain regions of the photoresist film by the photoetching method, and then arsenic ions are implanted at an acceleration voltage of 120 kV to obtain a high concentration n. The type diffusion layer regions 3 and 4 are formed. The implantation amount was 1 × 10 ¹⁵ cm- ² . Of course, these high concentration n-type diffusion layer regions may be formed by using phosphorus ions. The drive-in process in a nitrogen atmosphere at 900 ° C. for 10 minutes results in the structure shown in FIG.
Next, as shown in FIG. 11A, a polycrystalline silicon film having a thickness of 50 nm is deposited on the polycrystalline silicon film 6, and 87
Deposition of phosphorus is performed at 5 ° C for 20 minutes. afterwards,
A polycrystalline silicon film having different widths in the channel direction was processed by photolithography and dry etching (first gate electrode 6) to obtain the structure shown in FIG. 11 (b). Then, as shown in FIG. 12, PSG is formed to a thickness of 200 nm.
A silicon oxide film 9 such as a film was deposited by the LPCVD method to form an interlayer insulating film, a contact hole was opened by photoetching and dry etching, and aluminum wiring 10 was formed to obtain a desired semiconductor device shown in FIG.

The semiconductor device obtained as a result of the above shows the desired characteristics with only one gate electrode 6, unlike Examples 1 and 2 having two gates.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made without departing from the scope of the invention. .. For example, in each of the above embodiments, p
Although the type substrate is used, it goes without saying that a p-channel MISFET using an n-type substrate can be realized by changing all polarities of the device. In the embodiment shown in FIG. 1, the first gate electrode 6 and the second gate electrode 8
Alternatively, the gate electrodes 6 may be provided on the gate electrode 8 with the interlayer insulating film 7 interposed therebetween.

[0022]

As described above, according to the semiconductor device of the present invention, the conductivity of the field effect transistor is extremely strongly modulated by introducing the periodic potential into the one-dimensional conduction in which the propagation modes are uniform. You can
Therefore, a characteristic that requires a complicated circuit configuration in a macro device can be realized with a fine and single element, which is effective for future LSIs and the like.

[Brief description of drawings]

FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a shape of a channel of a semiconductor device of the present invention.

FIG. 3 is an energy band diagram in the channel of FIG.

FIG. 4 is a diagram showing current-voltage characteristics of the semiconductor device of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

6A and 6B are a cross-sectional view (a) and a plan view (b) showing the manufacturing process of the first embodiment of the present invention.

7A and 7B are a cross-sectional view (a) and a plan view (b) showing the manufacturing process of the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

FIG. 9 is a sectional view (a) and a plan view (b) showing a manufacturing process of a second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing process of a third embodiment of the present invention.

FIG. 11 is a sectional view (a) and a plan view (b) showing a manufacturing process of a third embodiment of the present invention.

FIG. 12 is a cross-sectional view showing the manufacturing process of the third embodiment of the present invention.

[Explanation of symbols]

1 ... Si substrate, 2 ... Element isolation region, 3 ... Source region, 4
Drain region, 5 ... Gate oxide film, 6 ... First gate electrode, 7 ... Interlayer insulating film, 8 ... Second gate electrode, 9 ... Interlayer insulating film, 10 ... Aluminum electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7739-4M H01L 29/80 B

Claims (6)

[Claims] 1. A first-conductivity-type semiconductor substrate, and a second-conductivity-type source / drain region having a conductivity type opposite to the first-conductivity type, which is provided on the surface of the semiconductor substrate at a predetermined interval. In a semiconductor device having a field effect transistor including a gate electrode provided on the semiconductor substrate between the source / drain regions, the gate electrode is 1
A first gate electrode that forms a three-dimensional channel and is electrically insulated from the first gate electrode, periodically changes the width of the channel, and causes periodic scattering of charged particles traveling in the channel. A semiconductor device comprising a second gate electrode provided. 2. The first gate electrode is formed in a thin line shape over the source / drain regions, the second gate electrode is laminated on the first gate electrode via an insulating film, and 2. The semiconductor device according to claim 1, wherein the second gate electrode has a plurality of fine line-shaped openings arranged in the channel direction formed by the first gate electrode. 3. The first gate electrodes are arranged and formed in a plurality of parallel thin line shapes in the channel direction over the source / drain regions, and are electrically connected to each other, and the second gate electrodes are the first gate electrodes. Is laminated on the gate electrode via an insulating film, and the second gate electrode is formed on the first gate electrode.
2. The semiconductor device according to claim 1, further comprising a plurality of thin line-shaped openings formed in the channel direction by the gate electrode of FIG. 4. A first-conductivity-type semiconductor substrate, and a second-conductivity-type source / drain region which is opposite in conductivity to the first-conductivity type and is provided on the surface of the semiconductor substrate at a predetermined distance. In a semiconductor device having a field-effect transistor including a gate electrode provided on the semiconductor substrate between the source / drain regions, a one-dimensional channel is formed, and charged particles traveling in the channel are cycled. A semiconductor device provided with the above-mentioned gate electrode which gives a general scattering. 5. The semiconductor device according to claim 4, wherein the gate electrode has a shape having different widths in the channel direction. 6. The semiconductor device according to claim 1, wherein the width of the channel is 0.1 μm or less.