JPH05102319A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH05102319A JPH05102319A JP26020691A JP26020691A JPH05102319A JP H05102319 A JPH05102319 A JP H05102319A JP 26020691 A JP26020691 A JP 26020691A JP 26020691 A JP26020691 A JP 26020691A JP H05102319 A JPH05102319 A JP H05102319A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer wiring
- wiring
- pillar
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000007747 plating Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 37
- 239000011229 interlayer Substances 0.000 abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000007796 conventional method Methods 0.000 description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置及びその製
造方法にかかり、特に多層配線構造を有する半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a multilayer wiring structure.
【０００２】[0002]
【従来の技術】従来、この種の多層配線構造は、図１４
あるいは図１５乃至図２４に示すように形成される。2. Description of the Related Art Conventionally, a multilayer wiring structure of this type has been shown in FIG.
Alternatively, it is formed as shown in FIGS.
【０００３】すなわち図１４において、シリコンからな
る半導体基板４１０上に形成された絶縁膜４１１上に
は、アルミニウム等からなる第１層配線４１２が形成さ
れており、又その上には、層間絶縁膜４１３を介して第
２層配線４１５が形成されている。層間絶縁膜４１３に
は第１層配線４１２と第２層配線４１５を電気的に接続
する層間接続孔４１４が設けられている。That is, in FIG. 14, a first layer wiring 412 made of aluminum or the like is formed on an insulating film 411 formed on a semiconductor substrate 410 made of silicon, and an interlayer insulating film is formed thereon. A second layer wiring 415 is formed via 413. The interlayer insulating film 413 is provided with an interlayer connection hole 414 for electrically connecting the first layer wiring 412 and the second layer wiring 415.
【０００４】次に図１５〜図２４に示す他の従来技術に
ついて説明する。Next, another conventional technique shown in FIGS. 15 to 24 will be described.
【０００５】本例は、メッキ技術を利用して層間接続孔
の代わりに層間接続用の柱（ピラー）を使用するもので
ある。In this example, a pillar (pillar) for interlayer connection is used in place of the interlayer connection hole by utilizing a plating technique.
【０００６】まず、図１５に示すように、シリコンから
なる半導体基板５１０上に形成された絶縁膜５１１上に
は、メッキ用の給電膜５１２としてチタン・タングステ
ン，金を順次積層している。給電膜としては、他にチタ
ン・白金・パラジウム・窒化チタン等の組み合わせでも
可能である。First, as shown in FIG. 15, titanium / tungsten and gold are sequentially stacked as a power supply film 512 for plating on an insulating film 511 formed on a semiconductor substrate 510 made of silicon. Other than that, the power supply film may be a combination of titanium, platinum, palladium, titanium nitride and the like.
【０００７】次に、図１６に示すように第１層配線を形
成するためのホトレジストパターン５１３を配線形成部
以外に形成する。Next, as shown in FIG. 16, a photoresist pattern 513 for forming the first layer wiring is formed in a portion other than the wiring forming portion.
【０００８】次に、図１７に示すように金メッキを行な
い第１層の配線５１４を形成する。Next, as shown in FIG. 17, gold plating is performed to form a first layer wiring 514.
【０００９】次に、図１８に示すようにホトレジストを
除去した後、層間接続用の柱（ピラー）を形成する部分
以外にホトレジストパターン５１５を形成する。Next, as shown in FIG. 18, after removing the photoresist, a photoresist pattern 515 is formed on portions other than the portions where pillars (pillars) for interlayer connection are formed.
【００１０】次に、図１９に示すように金メッキを行な
い層間接続用の柱（ピラー）５１６を形成する。Next, as shown in FIG. 19, gold-plating is performed to form pillars (pillars) 516 for interlayer connection.
【００１１】次に図２０に示すようにホトレジストを除
去する。Next, as shown in FIG. 20, the photoresist is removed.
【００１２】次に図２１に示すように、第１層の配線５
１４をマスクとして給電膜５１２をエッチング除去す
る。給電膜の除去法としては、王水等によるウェットエ
ッチやイオンミリング等によるドライエッチが知られて
いる。Next, as shown in FIG. 21, the first layer wiring 5
The power supply film 512 is removed by etching using 14 as a mask. Known methods for removing the power supply film include wet etching using aqua regia and dry etching using ion milling.
【００１３】次に、図２２に示すように、層間絶縁膜５
１７を形成しエッチバック等を施すことにより、層間接
続用の柱（ピラー）が層間絶縁膜５１７の表面に出る様
に形成する。Next, as shown in FIG. 22, the interlayer insulating film 5 is formed.
By forming 17 and etching back or the like, pillars (pillars) for interlayer connection are formed so as to be exposed on the surface of the interlayer insulating film 517.
【００１４】次に、図２３，図２４に示すように、第１
層目と同様にして第２層の配線を形成する。多層配線の
場合は、上記を繰り返す。Next, as shown in FIGS. 23 and 24, the first
Second-layer wiring is formed in the same manner as the second layer. In the case of multilayer wiring, the above is repeated.
【００１５】[0015]
【発明が解決しようとする課題】この従来の多層配線構
造においては、配線の形成の為のホトレジスト工程と層
間接続の為のホトレジスト工程を交互に繰り返し行なう
必要がある。従って例えば４層配線の場合、７回ものホ
トレジスト工程が必要である。又、下層配線と層間接続
孔又は、ピラーの間には、目合わせズレを考慮したマー
ジンが必要であり、微細化の際に障害となっていた。In this conventional multilayer wiring structure, it is necessary to alternately repeat a photoresist process for forming wiring and a photoresist process for interlayer connection. Therefore, for example, in the case of 4-layer wiring, seven times of photoresist steps are required. Further, a margin considering misalignment is required between the lower layer wiring and the interlayer connection hole or the pillar, which is an obstacle to miniaturization.
【００１６】[0016]
【課題を解決するための手段】本発明の半導体装置は、
下層配線の線巾が一定の幅より太い部分に下層配線と上
層配線を電気的に接続する柱が下層配線に対して自己整
合的に形成されている事を特徴とする多層配線構造の半
導体装置である。即ち、下層配線の端部と柱（ピラー）
との距離が一定になっていることが特徴である。The semiconductor device of the present invention comprises:
A semiconductor device having a multi-layer wiring structure, in which a pillar for electrically connecting the lower layer wiring and the upper layer wiring is formed in a self-alignment manner with respect to the lower layer wiring in a portion where the line width of the lower layer wiring is thicker than a certain width. Is. That is, the end of the lower layer wiring and the pillar (pillar)
The feature is that the distance between and is constant.
【００１７】又、本発明の製造方法は、半導体基板上に
設けられた第１の絶縁膜上に給電膜を形成する工程と、
線巾が一定の巾より太い部分と細い部分とからなる下層
配線形成部分以外にたとえばホトレジスト又は、樹脂膜
からなるメッキ用のマスクパターンを形成する工程と、
前記マスクパターンの側面に第２の絶縁膜を形成し、前
記線巾が一定の幅より細い部分を埋設する工程と前記線
巾が一定の幅より太い部分で第２の絶縁膜に囲まれた給
電膜の露出した箇所に選択的に、金属膜を被着し下層配
線と上層配線を電気的に接続する柱を形成する工程と、
エッチングにより前記第２の絶縁膜を除去する工程と、
新たに露出した給電膜上に前記金属膜上に再びメッキ法
により、金属膜を形成する工程と、前記ホトレジスト又
は樹脂膜等よりなるマスクパターンを除去した後、前記
金属膜をマスクに給電膜をエッチング除去する工程と層
間膜を前記柱の高さ以下に形成する工程と上層配線を形
成する工程とを具備している半導体装置の製造方法であ
る。Further, the manufacturing method of the present invention comprises a step of forming a power feeding film on the first insulating film provided on the semiconductor substrate,
A step of forming a mask pattern for plating made of, for example, a photoresist or a resin film, in addition to a lower layer wiring forming portion having a line width thicker and a thinner portion than a certain width,
A step of forming a second insulating film on a side surface of the mask pattern and burying a portion where the line width is thinner than a certain width, and a portion where the line width is thicker than the certain width is surrounded by the second insulating film. A step of selectively depositing a metal film on the exposed portion of the power feeding film to form a pillar electrically connecting the lower layer wiring and the upper layer wiring,
A step of removing the second insulating film by etching,
A step of forming a metal film on the newly exposed power supply film by plating again on the metal film, and after removing the mask pattern made of the photoresist or the resin film, the power supply film is formed using the metal film as a mask. A method of manufacturing a semiconductor device, comprising: a step of removing by etching, a step of forming an interlayer film below the height of the pillar, and a step of forming an upper layer wiring.
【００１８】[0018]
【実施例】次に本発明の実施例について図面を参照して
説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１９】まず、第１の実施例として、図１に示すよ
うに、シリコン基板１１０上に設けられた第１の絶縁膜
１１１上に５００〜２０００オングストローム厚のチタ
ンタングステンと３００〜１０００オングストローム厚
の金または白金を順次スパッタ法により形成し給電膜１
１２を形成する。給電膜の機能としては、下地との密着
性の確保，メッキの為の電流経路及びメッキ可能な材質
であるだけでなく、耐熱性を確保するためのバリア膜と
しての機能が必要な場合もある。給電膜としては、チタ
ン・白金・パラジウム・窒化チタン等の組み合わせでも
可能である。First, as a first embodiment, as shown in FIG. 1, titanium-tungsten having a thickness of 500 to 2000 angstroms and titanium tungsten having a thickness of 300 to 1000 angstroms are formed on a first insulating film 111 provided on a silicon substrate 110. Power supply film 1 formed by sequentially forming gold or platinum by the sputtering method
12 is formed. As the function of the power supply film, not only the adhesion with the base, the current path for plating and the material that can be plated, but also the function as a barrier film for ensuring heat resistance may be required. .. The power supply film may be a combination of titanium, platinum, palladium, titanium nitride and the like.
【００２０】次に、図２に示すように、下層配線形成部
分以外のところにホトレジストパターン１１３を形成す
る。この際、後工程でピラーを形成する箇所１０２の巾
Ｘは、その他の箇所１０１の巾Ｙより間隔を広くする。
例えば通常の箇所１０１をＹを０．５μｍとすると、ピ
ラー形成部１０２の巾Ｘは０．７５μｍと広くする。Next, as shown in FIG. 2, a photoresist pattern 113 is formed in a portion other than the lower layer wiring forming portion. At this time, the width X of the portion 102 where the pillar is formed in the subsequent step is wider than the width Y of the other portion 101.
For example, when Y is 0.5 μm in the normal portion 101, the width X of the pillar forming portion 102 is widened to 0.75 μm.
【００２１】次に図３に示すように、例えばスパッタ法
により酸化膜を被着した後、リアクティブイオンエッチ
（ＲＩＥ）法によりホトレジスト側面部に酸化膜の第２
の絶縁膜１１４が残る様にエッチバックする。Next, as shown in FIG. 3, after depositing an oxide film by, for example, a sputtering method, a second oxide film is formed on the side surface of the photoresist by a reactive ion etching (RIE) method.
Etch back so that the insulating film 114 remains.
【００２２】この際ピラー形成部以外のところ１０１に
は、酸化膜１１４で埋設される。酸化膜の膜厚により、
ピラー形成箇所１０２において側面部に残る膜厚も制御
される。ピラー形成部１０２の巾Ｘを０．７５μｍとし
て、側面部の酸化膜厚Ｘは、０．２５〜０．３μｍ程度
が望ましい。At this time, an oxide film 114 is buried in the portion 101 other than the pillar forming portion. Depending on the thickness of the oxide film,
The film thickness remaining on the side surface at the pillar formation portion 102 is also controlled. The width X of the pillar forming portion 102 is 0.75 μm, and the oxide film thickness X on the side surface portion is preferably about 0.25 to 0.3 μm.
【００２３】次に、図４に示す様にメッキ法によりピラ
ー部の土台１１５を形成する。例えば電界金メッキを行
ない２μｍ厚程度形成する。Next, as shown in FIG. 4, the base 115 of the pillar portion is formed by the plating method. For example, electrolytic gold plating is performed to form a film having a thickness of about 2 μm.
【００２４】次に図５に示す様にエッチングにより側面
部の酸化膜１１４を除去する。Next, as shown in FIG. 5, the oxide film 114 on the side surface is removed by etching.
【００２５】次に、図６に示す様に再び金メッキ法によ
り、ピラー形成部分１０２及びそれ以外の箇所１０２の
配線部分１１６を形成する。配線部分を１μｍ厚とする
とピラー部は３μｍの高さに出来上る。Next, as shown in FIG. 6, the pillar forming portion 102 and the wiring portion 116 of the other portion 102 are formed again by the gold plating method. If the wiring portion has a thickness of 1 μm, the pillar portion has a height of 3 μm.
【００２６】次に図７に示す様にレジスト１１３を除去
した後、給電膜１１２の露出部分をエッチング除去す
る。Next, as shown in FIG. 7, after removing the resist 113, the exposed portion of the power supply film 112 is removed by etching.
【００２７】次に図８に示すように、層間絶縁膜１１７
をピラーの高さ以下となる様形成する。すなわち層間絶
縁膜の表面よりわずかにピラーの頭が突出するようにす
る。層間膜としては、プラズマＣＶＤ成長されたＳｉＯ
2 ，ＳｉＯＮ，ＳｉＮ等とスギンオングラス等の積層構
造又は、ポリイミド系の絶縁膜等を形成し、エッチバッ
ク等を行なって平坦化する。Next, as shown in FIG. 8, the interlayer insulating film 117 is formed.
Is formed so that the height is less than the height of the pillar. That is, the pillar heads are made to slightly project from the surface of the interlayer insulating film. As the interlayer film, SiO grown by plasma CVD is used.
2 , a laminated structure of SiON, SiN, etc. and Sgin-on-glass, or a polyimide-based insulating film is formed and flattened by etching back or the like.
【００２８】図９は平面図で、図９のＡ−Ａ部の断面が
図８となる。FIG. 9 is a plan view, and the section taken along the line AA of FIG. 9 is shown in FIG.
【００２９】次に図１０に示す様に、上層配線形成のメ
ッキ用の給電膜１１８を下層の給電膜１１２と同様に形
成し、さらにホトレジストパターン１１９を形成する。Next, as shown in FIG. 10, a power supply film 118 for plating for forming the upper layer wiring is formed in the same manner as the power supply film 112 of the lower layer, and a photoresist pattern 119 is further formed.
【００３０】次に図１１に示す様に、金メッキ法により
上層配線１２０を形成しレジストを除去し、露出する不
要な給電膜１１８をエッチング除去する。Next, as shown in FIG. 11, the upper wiring 120 is formed by a gold plating method, the resist is removed, and the exposed unnecessary power supply film 118 is removed by etching.
【００３１】同図から明らかのように、層間絶縁膜１１
７よりわずかに突出するピラー１３０の頭と層１２０と
下地膜１１８とから成る上層配線が接続し、これにより
この上層配線と層１１６と下地膜１１２とから成る下層
配線との所定の接続が行なわれる。As is clear from the figure, the interlayer insulating film 11
The head of the pillar 130 slightly protruding from 7 is connected to the upper layer wiring formed of the layer 120 and the base film 118, whereby a predetermined connection is made between the upper layer wiring and the lower layer wiring formed of the layer 116 and the base film 112. Be done.
【００３２】次に本発明の第２の実施例を説明する。第
１の実施例と同様、図３の工程まで形成した後、ピラー
の土台２１５の為のメッキを行なう際に、より安価なニ
ッケル等のメッキを行なう。その後は、第１の実施例と
同様ピラーの土台２１５は、後工程での金メッキ１１６
で完全におおわれてピラー１４０を形成するので、安価
な材料を使用しても腐蝕・劣化等の問題を生じない。
又、抵抗の高い材料を使用してもそれ程導通抵抗は増加
しない。この第２の実施例を示す図１２および図１３は
第１の実施例を示す図５および図６にそれぞれ対応して
いる。又、第１の実施例と同じ機能のところは同じ符号
で示している。Next, a second embodiment of the present invention will be described. Similar to the first embodiment, after forming up to the step of FIG. 3, when plating for the base 215 of the pillar, plating of less expensive nickel or the like is performed. After that, as in the first embodiment, the base 215 of the pillar has the gold plating 116 in the post process.
Since the pillar 140 is completely covered with, the problems such as corrosion and deterioration do not occur even if an inexpensive material is used.
Further, even if a material having high resistance is used, the conduction resistance does not increase so much. 12 and 13 showing the second embodiment correspond to FIGS. 5 and 6 showing the first embodiment, respectively. The same functions as those in the first embodiment are designated by the same reference numerals.
【００３３】次に本発明の第３の実施例を説明する。Next, a third embodiment of the present invention will be described.
【００３４】第２の実施例と同様、図３の工程まで形成
した後ピラーの土台を選択ＣＶＤ法で形成する。例えば
選択ＣＶＤタングステンを２μｍ厚に形成する。その後
は、第１の実施例と同様である。図面は、省略する。Similar to the second embodiment, the pillar base is formed by the selective CVD method after the formation up to the step of FIG. For example, selective CVD tungsten is formed to a thickness of 2 μm. After that, it is similar to the first embodiment. The drawings are omitted.
【００３５】[0035]
【発明の効果】以上説明したように、本発明は、１回の
ホトリソグラフ工程で下層配線とピラーが形成されるの
で、多層配線を有する半導体装置が、より少ない工程数
で生産可能となる。例えば４層の場合従来少なくとも７
回のホトリソ工程が必要だったのが本発明の場合、たっ
た４回となる。As described above, according to the present invention, since the lower layer wiring and the pillars are formed in one photolithography step, the semiconductor device having the multilayer wiring can be manufactured in a smaller number of steps. For example, in the case of 4 layers, at least 7
In the case of the present invention, it is only four times that the photolithography process is required twice.
【００３６】又、下層配線とピラーが自己整合されるの
でより微細な配線ピッチが可能となる。Further, since the lower layer wiring and the pillar are self-aligned, a finer wiring pitch is possible.
【００３７】さらに、第２の実施例の様にピラーの土台
を安価な金属で置換えても問題とならないので生産コス
トも低減できる。ピラー上部と配線が一回のメッキで形
成できるため金属のグレインが連続して形成され信頼性
も向上する。Furthermore, replacing the base of the pillar with an inexpensive metal as in the second embodiment does not cause any problem, so the production cost can be reduced. Since the upper part of the pillar and the wiring can be formed by one-time plating, the metal grain is continuously formed and the reliability is also improved.
【図１】本発明の第１の実施例を示す図面。FIG. 1 is a drawing showing a first embodiment of the present invention.
【図２】本発明の第１の実施例を示す図面。FIG. 2 is a diagram showing a first embodiment of the present invention.
【図３】本発明の第１の実施例を示す図面。FIG. 3 is a diagram showing a first embodiment of the present invention.
【図４】本発明の第１の実施例を示す図面。FIG. 4 is a drawing showing a first embodiment of the present invention.
【図５】本発明の第１の実施例を示す図面。FIG. 5 is a drawing showing a first embodiment of the present invention.
【図６】本発明の第１の実施例を示す図面。FIG. 6 is a drawing showing a first embodiment of the present invention.
【図７】本発明の第１の実施例を示す図面。FIG. 7 is a drawing showing a first embodiment of the present invention.
【図８】本発明の第１の実施例を示す図面。FIG. 8 is a diagram showing a first embodiment of the present invention.
【図９】本発明の第１の実施例を示す図面。FIG. 9 is a drawing showing a first embodiment of the present invention.
【図１０】本発明の第１の実施例を示す図面。FIG. 10 is a drawing showing a first embodiment of the present invention.
【図１１】本発明の第１の実施例を示す図面。FIG. 11 is a drawing showing a first embodiment of the present invention.
【図１２】本発明の第２の実施例を示す図面。FIG. 12 is a drawing showing a second embodiment of the present invention.
【図１３】本発明の第２の実施例を示す図面。FIG. 13 is a drawing showing a second embodiment of the present invention.
【図１４】従来技術を示す図面。FIG. 14 is a drawing showing a conventional technique.
【図１５】従来技術を示す図面。FIG. 15 is a drawing showing a conventional technique.
【図１６】従来技術を示す図面。FIG. 16 is a drawing showing a conventional technique.
【図１７】従来技術を示す図面。FIG. 17 is a drawing showing a conventional technique.
【図１８】従来技術を示す図面。FIG. 18 is a drawing showing a conventional technique.
【図１９】従来技術を示す図面。FIG. 19 is a drawing showing a conventional technique.
【図２０】従来技術を示す図面。FIG. 20 is a drawing showing a conventional technique.
【図２１】従来技術を示す図面。FIG. 21 is a drawing showing a conventional technique.
【図２２】従来技術を示す図面。FIG. 22 is a drawing showing a conventional technique.
【図２３】従来技術を示す図面。FIG. 23 is a drawing showing a conventional technique.
【図２４】従来技術を示す図面。FIG. 24 is a drawing showing a conventional technique.
１０１ ピラーを形成しない配線箇所 １０２ ピラーを形成する配線箇所 １１０ 半導体基板 １１１，１１４ 絶縁膜 １１２，１１８ メッキ用給電線 １１３ ホトレジストパターン １１５，２１５ ピラーの土台 １１６ 金メッキによる下層配線 １１７ 層間絶縁膜 １２ 金メッキによる上層配線 １３０，１４０ ピラー 101 Wiring point where pillar is not formed 102 Wiring point where pillar is formed 110 Semiconductor substrate 111, 114 Insulating film 112, 118 Plating power supply line 113 Photo resist pattern 115, 215 Pillar base 116 Lower layer wiring by gold plating 117 Interlayer insulating film 12 By gold plating Upper wiring 130,140 pillars
Claims (2)
に下層配線と上層配線を電気的に接続する柱が、下層配
線に対して自己整合的に形成されている事を特徴とする
多層配線構造の半導体装置。1. A pillar for electrically connecting a lower layer wiring and an upper layer wiring is formed in a portion where the line width of the lower layer wiring is thicker than a certain width in a self-aligned manner with respect to the lower layer wiring. A semiconductor device having a multilayer wiring structure.
上に給電膜を形成する工程と、線巾が一定の巾より太い
部分と細い部分とからなる下層配線形成部分以外にメッ
キ用のマスクパターンを形成する工程と、前記マスクパ
ターンの側面に第２の絶縁膜を形成し、前記線巾が一定
の巾より細い部分を埋設する工程と、前記線巾が一定の
巾より太い部分で第２の絶縁膜に囲まれた給電膜の露出
した箇所に、選択的に金属膜を被着し下層配線と上層配
線を電気的に接続する柱を形成する工程と、エッチング
により前記第２の絶縁膜を除去する工程と、新たに露出
した給電膜上と前記金属膜上に再びメッキ法により、金
属膜を形成する工程と、前記マスクパターンを除去した
後、前記金属膜をマスクに給電膜をエッチング除去する
工程と、層間膜を前記柱の高さ以下に形成する工程と、
上層配線を形成する工程とを具備していることを特徴と
する半導体装置の製造方法。2. A step for forming a power supply film on a first insulating film provided on a semiconductor substrate, and plating for a portion other than a lower layer wiring forming portion including a portion having a line width thicker than a certain width and a portion having a thin line width. Forming a mask pattern, forming a second insulating film on a side surface of the mask pattern, and burying a portion where the line width is thinner than a certain width, and a portion where the line width is thicker than the certain width. At the exposed portion of the power feeding film surrounded by the second insulating film, a step of selectively depositing a metal film to form a pillar electrically connecting the lower layer wiring and the upper layer wiring, and the second step by etching. Removing the insulating film, forming a metal film on the newly exposed power supply film and the metal film by plating again, and removing the mask pattern, and then supplying power to the metal film as a mask. Before removing the film by etching A step of forming the column below the height,
And a step of forming an upper wiring, the method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3260206A JP2884849B2 (en) | 1991-10-08 | 1991-10-08 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3260206A JP2884849B2 (en) | 1991-10-08 | 1991-10-08 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05102319A true JPH05102319A (en) | 1993-04-23 |
| JP2884849B2 JP2884849B2 (en) | 1999-04-19 |
Family
ID=17344817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3260206A Expired - Fee Related JP2884849B2 (en) | 1991-10-08 | 1991-10-08 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2884849B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010141178A (en) * | 2008-12-12 | 2010-06-24 | Mitsubishi Electric Corp | Etching method and method of manufacturing semiconductor device using the same |
| JP2014236177A (en) * | 2013-06-05 | 2014-12-15 | 日本電信電話株式会社 | Wiring structure and formation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH021125A (en) * | 1988-06-09 | 1990-01-05 | Matsushita Electron Corp | Manufacture of semiconductor device |
-
1991
- 1991-10-08 JP JP3260206A patent/JP2884849B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH021125A (en) * | 1988-06-09 | 1990-01-05 | Matsushita Electron Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010141178A (en) * | 2008-12-12 | 2010-06-24 | Mitsubishi Electric Corp | Etching method and method of manufacturing semiconductor device using the same |
| JP2014236177A (en) * | 2013-06-05 | 2014-12-15 | 日本電信電話株式会社 | Wiring structure and formation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2884849B2 (en) | 1999-04-19 |
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