JPH05101204A - Data processing system - Google Patents

Abstract

PURPOSE:To improve the timing margin of a data processing system by securing a constitution where all circuits of a microprocessor unit except a clock generating circuit work only with the clocks given from a radio wave trouble solving circuit. CONSTITUTION:A data processing system includes a microprocessor unit MPU 1 which contains an oscillation circuit 1A to produce the clocks and radio wave trouble solving circuit 1C which works to the clocks given from the circuit 1A. Then all circuits of the MPU 1 except the circuit 1A work only with the clocks given from the circuit 1C. The clock of the circuit 1C has its phase delayed from the clock 1B outputted from the circuit 1A, i.e., the MPU 1. However the system clock inputted to an external circuit 1E and the internal clocks inputted to an internal CPU 1F and a circuit 1G are given from the circuit 1C and have no phase shift.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system in which a clock generated from a clock generating circuit of a microprocessor unit is provided with a countermeasure against generated radio waves.

[0002]

2. Description of the Related Art Conventionally, an MPU having a built-in oscillation circuit has been known, and the clock from the built-in oscillation circuit is used as an MPU internal clock and also as a system clock through a filter or the like for measures against radio waves generated and generated. ..

[0003]

However, in the above-described conventional example, the system clock is set through a filter or the like as a countermeasure against generated radio waves, and the stray capacitance is present on the PCB. Therefore, the phase of the system clock is different from the MPU internal clock. Therefore, the actual access time of the memory was shortened, and in the worst case, a wait cycle had to be inserted.

An object of the present invention is to provide a data processing system which can solve the above problems and improve the timing margin of the system.

[0005]

In order to achieve such an object, the present invention provides a microprocessor unit having a clock generating circuit for generating a clock, and a clock from the clock generating circuit for generating a radio wave. In the data processing system having a radio wave countermeasure circuit, circuits of the microprocessor unit other than the clock generation circuit operate based on only the clock from the generated radio wave countermeasure circuit.

The present invention also provides a microprocessor unit having a clock generation circuit for generating a clock,
A data processing system having a generated radio wave countermeasure circuit for taking a countermeasure against a generated radio wave to a clock from the clock generation circuit, comprising a delay circuit for delaying the phase of the clock from the clock generation circuit by a predetermined delay value, and the microprocessor. The unit is characterized in that circuits other than the clock generation circuit operate based on the clock from the delay circuit.

[0007]

In the present invention, circuits other than the clock generation circuit of the microprocessor unit operate based on only the clock from the generated radio wave countermeasure circuit.

Further, in the present invention, circuits other than the clock generating circuit of the microprocessor unit operate based on the clock from the delay circuit.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First Embodiment FIG. 1 shows a first embodiment of the present invention.

In the figure, reference numeral 1 denotes an MPU, which is an oscillator circuit 1.
A, a CPU 1F, and a circuit 1G. Oscillation circuit 1
A is for generating an MPU external clock signal.

Reference numeral 1C is a radio wave countermeasure circuit, which is provided outside the MPU 1 and which takes measures against the radio waves generated by the MPU external clock signal from the oscillation circuit 1A and outputs a system clock. The system clock is a circuit 1E provided outside the MPU1 and a CPU 1F provided inside the MPU1.
And is output to the circuit 1G.

Since this is done, the generated radio wave countermeasure circuit 1
The clock output from C is delayed in phase with respect to the clock output from oscillator circuit 1A, that is, the clock output from MPU1, that is, MPU1 (see FIG. 2).
The system clock input to the external circuit 1E and the MPU
Since the MPU internal clocks input to the CPU 1F and the circuit 1G in 1 are clocks from the radio wave countermeasure circuit 1C, there is no phase shift.

Second Embodiment FIG. 3 shows a second embodiment of the present invention.

In this embodiment, as the clock input to the CPU 1F and the circuit 1G, either the system clock from the radio wave countermeasure circuit 1C or the clock from the oscillation circuit 1A can be selected by the switching circuit 33B. ..

FIG. 5 shows the configuration of the switching circuit shown in FIG.

In FIG. 5, 4E is an AND circuit for ANDing the clock from the oscillation circuit 1A and the selection signal 3A. 4D is a NOT circuit for inverting the level of the selection signal 3A. 4F is an AND circuit, NO
The AND operation is performed on the selection signal 3A whose level is inverted by the T circuit 4D and the clock from the radio wave countermeasure circuit 1C. 4G is an OR circuit for ORing the signals from the AND circuits 4E and 4F.

With this arrangement, when the selection signal 3A is "H", the output level of the NOT circuit 4D becomes "L" and the output level of the AND circuit 4F becomes "L". Clock 1D is selected. On the other hand, when the selection signal 3A is "L", the output level of the AND circuit 4E becomes "L", so the clock 1D from the radio wave countermeasure circuit 1C is selected.

In this embodiment, an example in which the clock is selected by the selection signal has been described, but the clock may be selected by software by register writing in the MPU. If this is done, noise may occur because the clock levels do not match, and the MPU may malfunction, but such malfunction can be prevented by the countermeasure circuit.

Third Embodiment FIG. 5 shows a third embodiment of the present invention.

In the present embodiment, the phase of the clock from the oscillation circuit 1A is delayed by the delay circuit 1C (see FIG. 6), and the delayed clock is input to the CPU 1F and the circuit 1G. The delay amount by the delay circuit 5C is
The clock 1B output from the oscillator circuit 1A to the outside of the MPU is equal to the delay amount delayed by the stray capacitance on the PCB or the radio wave countermeasure product inserted.

If a delay circuit that can change the delay value is used, it becomes easy to match the phases.
FIG. 7 shows an example of a delay circuit that can change the delay amount.
Shown in. This is an example of a delay circuit capable of selecting two types of delay values for the sake of simplicity.

In FIG. 7, 73A is a signal input to the delay circuit, and 73B is a delay value selection signal. 7
A delay circuit 3C has a delay value of 1. A delay circuit 73D has a delay value of 2. 73F is a logical product circuit, and a delay circuit 73C
And the delay value selection signal 73B. 73E is a negation circuit for inverting the level of the delay value selection signal 73B. 7
3G is a logical product circuit for calculating a logical product of the clock from the delay circuit 73D and the delay value selection signal 73B whose level is inverted by the NOT circuit 73C.
Reference numeral 73H is a logical sum circuit for calculating a logical sum of signals from the logical product circuits 73H and 73G.

Thus, when the delay value selection signal 73B is "H", the output level of the NOT circuit 73E becomes "L" and the output level of the AND circuit 73G is "L".
Therefore, the clock from the delay circuit 73C having the delay value of 1 is selected. On the other hand, the delay value selection signal 73
When B is “L”, the output level of the AND circuit 73F becomes “L”, so that the delay circuit 73D having the delay value 2 is used.
The clock from is selected. Therefore, two kinds of delay values can be selected.

In this embodiment, the delay value selection signal 73B
Although the example in which the clock is selected is described above, the clock may be selected by software by register writing in the MPU. If this is done, noise may occur because the clock levels do not match, and the MPU may malfunction, but such malfunction can be prevented by the countermeasure circuit.

[0026]

As described above, according to the present invention,
Since it is configured as described above, there is an effect that the timing margin of the system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of an MPU input / output phase difference.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a switching circuit 3B shown in FIG.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a diagram showing an example of a phase difference between MPU input and output.

FIG. 7 is a block diagram showing an example of a delay circuit capable of varying a delay value.

[Explanation of symbols]

 1 MPU 1A Oscillation circuit 1C Radio wave countermeasure circuit 1E, 1G circuit 1F CPU

Claims (3)

[Claims] 1. A data processing system comprising: a microprocessor unit having a clock generation circuit for generating a clock; and a generated radio wave countermeasure circuit for taking countermeasures against generated radio waves from a clock from the clock generation circuit, wherein the microprocessor unit is a clock. A data processing system, wherein circuits other than the generating circuit operate based on only the clock from the generated radio wave countermeasure circuit. 2. A data processing system comprising: a microprocessor unit having a clock generating circuit for generating a clock; and a generated radio wave countermeasure circuit for taking countermeasures against the generated radio wave on the clock from the clock generating circuit, wherein: A data processing system comprising a delay circuit for delaying the phase of a clock by a predetermined delay value, wherein the microprocessor unit operates based on a clock from the delay circuit in circuits other than the clock generating circuit. 3. The data processing system according to claim 2, further comprising delay value changing means for changing a delay value of the delay circuit.