JPH05100900A - Information processor - Google Patents

Abstract

PURPOSE:To recognize relation between a front and a rear when a fault occurs by storing the address of jump origin or interruption origin and the address of a jump destination or interruption destination in RAM when there are a jump instruction and interruption. CONSTITUTION:Unless the jump instruction or interruption of the software instruction comes, an address generating part 31 sets the address of the software instruction which is succeedingly executed in a successive program counter 1 and does not write it in a randam access memory(RAM) 15 while a program is under progress. When a jump instruction interruption detecting part 32 detects the jump instruction or interruption of the software instruction, the address generating part 31 merges the address of jump origin or interruption origin in the address of the jump destination or interruption destination so as to adopt it as write data 11 which is 64-bit data and transmits it to RAM 15 and RAM 15 stores the data 11. In this case, the start and stop of a writing operation to RAM 14 is executed by the indication of software.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a trace function of a software program when a failure occurs.

[0002]

2. Description of the Related Art A conventional information processing apparatus does not have a function of holding a jump source address and a jump destination address when a software jump / interrupt occurs, and the program counter always executes the current execution. It indicates an inside instruction or an instruction to be executed next. In the case of a failure due to an asynchronous interrupt or runaway of the processor, the program counter only indicates the instruction that caused the error, and it is possible to know from the register information of the processor what processing by the software was performed before that. It has a configuration without means.

[0003]

As described above, the conventional information processing apparatus has a function of holding the jump source address and the jump destination address when a software jump / interrupt occurs. Instead, the program counter always indicates the currently executing instruction or the next instruction to be executed. Therefore, in the case of a fault due to an asynchronous interrupt or a runaway of the processor, the program counter only indicates the instruction that caused the error, and the register information of the processor indicates from the register information of the processor what processing was performed before that. It has the drawback of not being able to know. In the case of an intermittent failure, comparing the case of normal operation with the case of occurrence of abnormality is the first step for solving the failure. It has a drawback that it is difficult to understand the cause and only superficial information such as the address of the instruction in which the error occurred can be obtained.

[0004]

An information processing apparatus according to the present invention comprises a decoder for inputting a jump instruction and detecting it, and an interrupt detection circuit for inputting an interrupt signal and detecting the interrupt signal. A jump instruction interrupt detection unit that outputs a write enable signal when either the instruction or the interrupt signal is detected, a (+1) signal, an (offset) signal, and the write enable signal from the jump instruction interrupt detection unit. A selector that outputs the (+1) signal when the software instruction to be input and executed is other than the jump instruction and the interrupt, and outputs the (offset) signal when the software instruction to be executed is the jump instruction or the interrupt. , A program counter for sequentially counting the addresses of executed software instructions, and the program counter Input address data from the selector and the address data from the selector are added, and the address data from the adder and the address data from the program counter are merged and the result is written as write data. An address generation unit having a merge unit for outputting and a random access memory for receiving the write data and the write enable signal and storing the write data are provided.

The information processing apparatus of the present invention further comprises a decoder for inputting a jump instruction and detecting it, and an interrupt detection circuit for inputting an interrupt signal and detecting the interrupt signal. A jump instruction interrupt detection unit that detects one of the signals and outputs a write enable signal when the RAM write on / off instruction signal from the outside is enabled, a (+1) signal, an (offset) signal, and the jump. When the software instruction to be executed by inputting the write enable signal from the instruction interrupt detection unit is other than the jump instruction and the interrupt, the (+1) signal is output and the software instruction to be executed is the jump instruction or the interrupt. In this case, specify the selector that outputs the (offset) signal and the address of the executed software instruction. Next, a program counter for counting, an adder for inputting and adding address data output from the program counter and address data from the selector, an address data from the adder and an address data from the program counter are added. An address generation section having a merge section for merging and outputting the result as write data, and an on / off inversion signal obtained by inverting the RAM write on / off instruction signal are input to perform an inversion operation of the flip-flop 23 to thereby perform two operations. A RAM select unit having a flip-flop that outputs one of the select signals, and the write data by inputting the select signal of the write data, the write enable signal, and the two select signals. Store data, Is obtained by a two random access memory to be output to the outside what stores As RAM output data by inputting the pump start command.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The embodiment shown in FIG. 1 includes an address generator 31 and
The jump instruction interrupt detector 32 and the random access memory (RAM) 15 are provided.

The jump instruction interrupt detector 32 has a decoder 5 for inputting the jump instruction 13 and detecting it, and an interrupt detecting circuit 6 for inputting the interrupt signal 14 and detecting it. When either the signal 13 or the interrupt signal 14 is detected, the write enable signal 12 is output to the RAM 15 and the selector 2 of the address generator 31.

When the software instruction to be executed is other than the jump instruction and the interrupt, the address generator 31
Address data 7 (32
Bit) and the address data 8 from the selector 2 that has output the (+1) signal 2a are added in the adder 3,
The address data 9 is output to the merge unit 4. If the software instruction to be executed is a jump instruction or an interrupt, the address data 7 output from the program counter 1
And the address data 8 from the selector 2 that has output the (offset) signal 2b are added in the adder 3 and the address data 9 (32 bits) is output to the merge unit 4. The merging unit 4 inputs the address data 7 (32 bits) from the program counter 1 and the address data 9 (32 bits) from the adder 3, merges both addresses, and the result is the write data 11 ( 64 bits). The address data 9 is also output to the program counter 1.

The RAM 15 is a random access memory having one block of 64 bits, and receives the write data 11 (64 bits) from the merge section 4 and stores it.

In the above-described embodiment having such a configuration, when the jump instruction of software instruction or the interrupt is not entered, the address generator 31 is
The address of the software instruction to be executed next is sequentially set in the program counter 1 and is not written in the RAM 15. When the jump instruction interrupt detection unit 32 detects a jump instruction or an interrupt of a software instruction, the address generation unit 31 merges the jump source or interrupt source address with the jump destination or interrupt destination address to generate a 64-bit interrupt. Write data 11 as data is RAM1
5 and the RAM 15 stores it.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

The embodiment shown in FIG. 2 includes an address generator 31 and
A jump instruction interrupt detection unit 33, two random access memories (RAM) 16 and 17, and a RAM selection unit 34 are provided.

The jump instruction interrupt detection unit 33 has a decoder 5 for inputting the jump instruction 13 and detecting it, and an interrupt detection circuit 6 for inputting the interrupt signal 14 and detecting it. When either the RAM 13 or the interrupt signal 14 is detected and the RAM write-on / off instruction signal 21 from the outside is enabled, the write enable signal 12 is output to the RAM 15 and the selector 2 of the address generator 31.

When the software instruction to be executed is other than the jump instruction and the interrupt, the address generator 31
Address data 7 (32
Bit) and the address data 8 from the selector 2 that has output the (+1) signal 2a are added in the adder 3,
The address data 9 is output to the merge unit 4. If the software instruction to be executed is a jump instruction or an interrupt, the address data 7 output from the program counter 1
And the address data 8 from the selector 2 that has output the (offset) signal 2b are added in the adder 3 and the address data 9 (32 bits) is output to the merge unit 4. The merging unit 4 inputs the address data 7 (32 bits) from the program counter 1 and the address data 9 (32 bits) from the adder 3, merges both addresses, and the result is the write data 11 ( 64 bits). The address data 9 is also output to the program counter 1.

The RAMs 16 and 17 have one block 64.
It is a random access memory having a bit structure, and receives write data 11 (64 bits) from the merge unit 4 and stores it.

When the software instruction RAM write-off instruction is issued, the RAM select section 34 inputs the on-off inversion signal 22 obtained by inverting the RAM write on-off instruction signal 21 and inverts the flip-flop 23, thereby activating the RAM 16. It operates to switch the use between and. That is, the state in which the RAM select unit 34 is selecting the RAM 16 or 17 is reversed, and R on the opposite side is reversed.
Select signal 19 for selecting AM 16 or 17
Or 20 is output to the RAMs 16 and 17, respectively. The write operation of the RAMs 16 and 17 is started when the on / off inversion signal 22 is turned on by a software instruction. When the dump instruction 18 is issued according to the software instruction, the contents of the RAMs 16 and 17 are output as RAM output data 24 and 25 to the outside.

In the second embodiment configured as described above, when the jump instruction of the software instruction or the interrupt is not entered, the address generator 31 is
The address of the software instruction to be executed next is sequentially set in the program counter 1 and is not written in the RAMs 16 and 17. When the jump instruction interrupt detection unit 33 detects a jump instruction or an interrupt of a software instruction, the address generation unit 31 merges the jump source or interrupt source address with the jump destination or interrupt destination address to obtain a 64-bit Write data 11 as data
To RAMs 16 and 17. The RAM 16 or 17 stores the write data 11 when one of the RAMs selected by the flip-flop 23 of the RAM selection unit 34 operates when the on / off inversion signal 22 is turned on by a software instruction. Next, when the on / off inversion signal 22 is turned off by the instruction of the software, the flip-flop 23 is inverted and the RA on the other side is inverted.
When M is selected and the on / off inversion signal 22 is turned on again, the RAM on the opposite side operates to store the write data 11. When a failure occurs, a dump start instruction 18 is issued according to a software instruction, and the contents of the RAMs 16 and 17 are output as RAM output data 24 and 25, respectively.

[0020]

As described above, the information processing apparatus of the present invention detects a jump instruction and an interrupt, and when there is a jump instruction and an interrupt, the address of the jump source or the interrupt source and the jump destination or the interrupt destination. By configuring the address and the RAM to be stored in the RAM, it is possible to confirm the connection before and after the asynchronous interrupt or the failure due to the runaway of the processor. Further, by starting and stopping the write operation to the RAM according to the instruction of the software, there is an effect that the range of addresses stored in the RAM can be arbitrarily set. Further, by setting the number of RAMs to two and making it possible to select the write operation for them, the information when a failure occurs and the information one event before the failure occurs are stored in separate RAMs. Therefore, it is possible to analyze the cause of the failure while comparing the information.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 1 Program Counter 2 Selector 2a (+1) Signal 2b (Offset) Signal 3 Adder 4 Merge Unit 5 Decoder 6 Interrupt Detection Circuit 7 Address Data 8 Address Data 9 Address Data 11 Write Data 12 Write Enable Signal 13 Jump Instruction 14 Interrupt Signal 15 Random access memory (RAM) 16 Random access memory (RAM) 17 Random access memory (RAM) 18 Dump command 19 Select signal 20 Select signal 21 RAM write on / off instruction signal 22 On / off inversion signal 23 Flip flop 24 RAM output data 25 RAM output data 31 address generation unit 32 jump instruction interrupt detection unit 33 jump instruction interrupt detection unit 34 RAM selection unit

Claims (2)

[Claims] 1. A decoder for inputting a jump instruction and detecting it, and an interrupt detection circuit for inputting an interrupt signal and detecting the interrupt signal, and detecting either the jump instruction or the interrupt signal. At this time, a jump instruction interrupt detection unit that outputs a write enable signal, a (+1) signal, an (offset) signal, and the write enable signal from the jump instruction interrupt detection unit are input and the software instruction to be executed is a jump instruction. And a selector other than the interrupt, which outputs the (+1) signal and outputs the (offset) signal when the software instruction to be executed is a jump instruction or an interrupt, and the address of the executed software instruction is sequentially counted. The program counter, address data of the output of the program counter, and the select Address having an adder for inputting and adding the address data from the data counter, and a merge unit for merging the address data from the adder and the address data from the program counter and outputting the result as write data. An information processing apparatus, comprising: a generation unit; and a random access memory that receives the write data and the write enable signal and stores the write data. 2. A decoder which inputs a jump instruction and detects it, and an interrupt detection circuit which inputs an interrupt signal and detects the interrupt signal, and detects either the jump instruction or the interrupt signal. And external RAM
A jump instruction interrupt detection unit that outputs a write enable signal when the write on / off instruction signal is enabled, a (+1) signal, an (offset) signal, and the write enable signal from the jump instruction interrupt detection unit are input. And a selector that outputs the (+1) signal when the software instruction to be executed is other than the jump instruction and the interrupt and outputs the (offset) signal when the software instruction to be executed is the jump instruction or the interrupt, and Program counter for sequentially counting the addresses of the software instructions, an adder for inputting and adding the address data output from the program counter and the address data from the selector, the address data from the adder and the program The address data from the counter An address generation section having a merge section for outputting the result as write data, and an on / off inversion signal obtained by inverting the RAM write on / off instruction signal to input the on / off inversion signal to perform an inversion operation of the flip-flop 23. A RAM select unit having a flip-flop that outputs one of the select signals, and the write data by inputting the write data, the write enable signal, and one of the two select signals. Stores the data in RAM by inputting the dump start command.
An information processing device, comprising: two random access memories that are output to the outside as output data.